CN111381144A - Power device avalanche tolerance test system and test method - Google Patents
Power device avalanche tolerance test system and test method Download PDFInfo
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- CN111381144A CN111381144A CN202010331303.7A CN202010331303A CN111381144A CN 111381144 A CN111381144 A CN 111381144A CN 202010331303 A CN202010331303 A CN 202010331303A CN 111381144 A CN111381144 A CN 111381144A
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
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Abstract
The application provides a power device avalanche tolerance test system and a test method, and relates to the technical field of semiconductor device testing. The system comprises a power device testing circuit, an electric signal acquisition circuit, an avalanche tolerance calculation subsystem and an environment temperature control subsystem for providing an adjustable working environment temperature for the power device to be tested. The electric signal acquisition circuit is connected with a power device to be tested in the power device test circuit. The avalanche tolerance calculation subsystem is connected with the electric signal acquisition circuit and is used for calculating the avalanche tolerance required by the secondary breakdown of the power device to be tested according to the voltage drop and the current acquired by the electric signal acquisition circuit. Therefore, the avalanche tolerance of the power device to be tested at different working environment temperatures is tested by changing the working environment temperatures of the power device to be tested, so that the avalanche tolerance of the power device to be tested is compared and analyzed.
Description
Technical Field
The application relates to the technical field of semiconductor device testing, in particular to a power device avalanche tolerance testing system and a testing method.
Background
When a large reverse roll-off bias is applied to the PN junction of the power device, the flow of the electric field roll-off current causes avalanche roll-off of the power device, and the energy that the power device can absorb at this time is called avalanche tolerance and is used to represent breakdown resistance characteristics when a voltage is applied. For those applications where a large voltage spike is generated across the power device, the avalanche tolerance of the power device is considered, and the energy concentrated by the voltage spike is mainly determined by the inductance and the current. For the application occasion of the flyback switching power supply, a large voltage spike can be generated when the circuit is turned off, and in this case, the rated voltage of the power device can be reduced, so that a sufficient voltage margin is reserved. However, when the output of some power supplies is short-circuited, the primary side of the transformer generates a large current, and the power device may be damaged by snow due to the primary inductance. Therefore, under such application conditions, the avalanche resistance of the power device is considered. In addition, since some motors are loaded by inductive load and extremely high rush current is generated during starting and blocking, the avalanche tolerance of the power device is also considered. However, the avalanche tolerance test of the existing power device is often performed at a constant test temperature, and cannot simulate the avalanche tolerance of the power device at different test temperatures, so that the avalanche tolerance of the power device at different environmental temperatures cannot be compared and analyzed.
It is noted that the information disclosed in this background section is only for enhancement of understanding of the general background of the application and should not be taken as an acknowledgement or any form of suggestion that this information constitutes prior art already known to a person skilled in the art.
Disclosure of Invention
In order to overcome the technical problems mentioned in the above technical background, embodiments of the present application provide a power device avalanche tolerance test system and a test method capable of performing an avalanche tolerance test on power devices at different test temperatures.
In a first aspect of the present application, a power device avalanche tolerance testing system is provided, including: the system comprises a power device test circuit, an electric signal acquisition circuit, an avalanche tolerance calculation subsystem and an environment temperature control subsystem;
the electric signal acquisition circuit is connected with a power device to be tested in the power device test circuit and is used for acquiring the voltage drop and the current of the power device to be tested when the power device to be tested is conducted;
the avalanche tolerance calculation subsystem is connected with the electric signal acquisition circuit and is used for calculating the avalanche tolerance required by the secondary breakdown of the power device to be tested according to the voltage drop and the current acquired by the electric signal acquisition circuit;
the environment temperature control subsystem provides adjustable working environment temperature for the power device to be tested.
In one possible embodiment of the present application, the ambient temperature control subsystem includes a temperature controlled box, and the power device to be tested is disposed in the temperature controlled box.
In one possible embodiment of the present application, the power device test circuit includes: the device comprises a direct current power supply, a power device to be tested, a driving voltage supply sub-circuit and a conduction control sub-circuit;
the power device to be tested comprises a control electrode, a first electrode and a second electrode, wherein the control electrode is connected with the driving voltage supply sub-circuit, the first electrode is connected with the anode of the direct current power supply, and the second electrode is respectively grounded with the cathode of the direct current power supply; the direct current power supply provides direct current bias voltage for the power device to be tested, and the driving voltage providing sub-circuit provides driving voltage for the power device to be tested;
the conduction control sub-circuit is connected between the driving voltage supply sub-circuit and the control electrode of the power device to be tested and is used for controlling the driving voltage applied to the control electrode of the power device to be tested so as to control the conduction time of the power device to be tested.
In one possible embodiment of the present application, the power device to be tested includes an insulated gate bipolar transistor, a metal-oxide semiconductor field effect transistor, and a bipolar junction transistor.
In one possible embodiment of the present application, the power device to be tested is an NPN bipolar junction transistor, the first electrode of the power device to be tested is a collector of the NPN bipolar junction transistor, the second electrode is an emitter of the NPN bipolar junction transistor, and the control electrode is a base of the NPN bipolar junction transistor.
In one possible embodiment of the present application, the driving voltage providing sub-circuit includes a second resistor, a third resistor, a first diode, a second diode, and a first pulse signal source;
the second resistor and the third resistor are connected in series between the first pulse signal source and a control electrode of the power device to be tested;
the cathode of the first diode is connected between the second resistor and the third resistor, the anode of the first diode is connected with the anode of the second diode, and the cathode of the second diode is grounded.
In one possible embodiment of the present application, the conduction control sub-circuit includes a first resistor, a fourth resistor, a third diode, a switching tube, and a second pulse signal source;
the switching tube comprises a control electrode, a first electrode and a second electrode, the first electrode of the switching tube is connected between the output end of the driving voltage supply sub-circuit and the control electrode of the power device to be tested, and the second electrode is grounded;
the first resistor is connected between the control electrode of the switching tube and the second pulse signal source;
the cathode of the third diode is connected between the first resistor and the control electrode of the switching tube, and the anode of the third diode is grounded;
one end of the fourth resistor is connected with the control electrode of the switch tube, and the other end of the fourth resistor is grounded.
In one possible embodiment of the present application, the switching tube is an enhancement MOSFET, the first electrode of the switching tube is a drain electrode of the enhancement MOSFET, the second electrode of the switching tube is a source electrode of the enhancement MOSFET, and the control electrode of the switching tube is a gate electrode of the enhancement MOSFET.
In one possible embodiment of the present application, the first pulse signal source inputs a high-frequency pulse signal, and the second pulse signal source inputs a single pulse signal.
In a second aspect of the present application, there is further provided a power device avalanche tolerance testing method, which is applied to the power device avalanche tolerance testing system described above, and the method includes:
adjusting the environmental temperature of the working environment of the power device to be tested;
collecting the voltage drop and the current when the power device to be tested is conducted;
calculating the energy of the power device to be tested when the power device is conducted according to the acquired voltage drop and current;
and controlling the conduction time of the power device to be tested, and accumulating the energy of the power device to be tested when the power device to be tested is conducted before the secondary breakdown occurs to obtain the avalanche tolerance required by the power device to be tested when the secondary breakdown occurs.
The embodiment of the application provides a power device avalanche tolerance test system and a test method, and the system comprises a power device test circuit, an electric signal acquisition circuit, an avalanche tolerance calculation subsystem and an environment temperature control subsystem for providing an adjustable working environment temperature for a power device to be tested. The electric signal acquisition circuit is connected with a power device to be tested in the power device test circuit and is used for acquiring the voltage drop and the current of the power device to be tested when the power device to be tested is conducted. The avalanche tolerance calculation subsystem is connected with the electric signal acquisition circuit and is used for calculating the avalanche tolerance required by the secondary breakdown of the power device to be tested according to the voltage drop and the current acquired by the electric signal acquisition circuit. The avalanche tolerance of the power device to be tested at different working environment temperatures is tested by changing the working environment temperatures of the power device to be tested, so that the avalanche tolerance of the power device to be tested is compared and analyzed.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are required to be used in the embodiments will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present application and therefore should not be considered as limiting the scope, and for those skilled in the art, other related drawings can be obtained from the drawings without inventive effort.
Fig. 1 is a block schematic diagram of a power device avalanche tolerance testing system according to an embodiment of the present application;
fig. 2 is a schematic block diagram of a power device testing circuit according to an embodiment of the present disclosure;
fig. 3 is an alternative circuit structure diagram of a power device testing circuit provided in the embodiments of the present application;
fig. 4 is a schematic flow chart of a power device avalanche tolerance testing method provided in the embodiment of the present application.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are some embodiments of the present application, but not all embodiments. The components of the embodiments of the present application, generally described and illustrated in the figures herein, can be arranged and designed in a wide variety of different configurations.
Thus, the following detailed description of the embodiments of the present application, presented in the accompanying drawings, is not intended to limit the scope of the claimed application, but is merely representative of selected embodiments of the application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures.
It should be noted that the features of the embodiments of the present application may be combined with each other without conflict.
In order to solve the technical problems mentioned in the above background art, the inventors have innovatively designed the following power device avalanche tolerance test system.
Referring to fig. 1, fig. 1 shows a block schematic diagram of a power device avalanche tolerance testing system 10 according to an embodiment of the present application. The power device avalanche tolerance test system 10 may include: the system comprises a power device test circuit 110, an electric signal acquisition circuit 120, an avalanche tolerance calculation subsystem 130 and an ambient temperature control subsystem 140.
The electrical signal collection circuit 120 is connected to a power device to be tested in the power device test circuit 110, and the electrical signal collection circuit 120 is used for collecting a voltage drop and a current of the power device to be tested when the power device to be tested is turned on.
The avalanche tolerance calculation subsystem 130 is connected with the electrical signal acquisition circuit 120, and is used for calculating the avalanche tolerance required by the secondary breakdown of the power device to be tested according to the voltage drop and the current acquired by the electrical signal acquisition circuit 120. Specifically, the avalanche tolerance calculation subsystem 130 obtains the avalanche tolerance of the power device to be tested by accumulating the working energy of the power device to be tested before the secondary breakdown occurs.
The power device test circuit 110 may control the on-time of the power device to be tested by inputting the pulse signal.
The environmental temperature control subsystem 140 may provide a temperature-adjustable working environment for the power device to be tested, and may place the power device to be tested or the entire power device testing circuit 110 within a spatial range in which the environmental temperature control subsystem 140 can adjust the temperature. Optionally, the ambient temperature control subsystem 140 may change the temperature of the area where the power device to be tested is located through a key set on the ambient temperature control subsystem 140, or may change the temperature of the area where the power device to be tested is located through a handheld terminal in a wireless communication manner.
In summary, the avalanche tolerance test system 10 for the power device provided by the present application can test the avalanche tolerance of the power device to be tested at different operating environment temperatures by changing the operating environment temperature of the power device to be tested, so as to compare and analyze the avalanche tolerance of the power device to be tested.
In the embodiment of the present application, the ambient temperature control subsystem 140 may be a temperature control box, and specifically, the power device to be tested may be disposed in the temperature control box.
Referring to fig. 2, fig. 2 is a block diagram of a power device testing circuit 110. The power device test circuit 110 may include: a direct current power source 1101, a power device to be tested 1102, a driving voltage supply sub-circuit 1103 and a conduction control sub-circuit 1104.
The power device to be tested 1102 includes a control electrode con, a first electrode p1 and a second electrode p2, wherein the power device to be tested 1102 may include, but is not limited to, an insulated-gate Bipolar Transistor (IGBT), a Metal-Oxide-semiconductor field-Effect Transistor (MOSFET) and a Bipolar junction Transistor (Bipolar junction Transistor-BJT). Accordingly, when the power device to be tested 1102 is a bipolar junction transistor, the control electrode con of the power device to be tested 1102 may be a base electrode, the first electrode p1 may be a collector electrode, and the second electrode p2 may be an emitter electrode; when the power device 1102 to be tested is a metal-oxide semiconductor field effect transistor, the control electrode con of the power device 1102 to be tested may be a gate, the first electrode p1 may be a drain, and the second electrode p2 may be a source.
The control electrode con of the power device to be tested 1102 is connected to the driving voltage providing sub-circuit 1103, the first electrode P1 of the power device to be tested 1102 is connected to the positive electrode of the dc power source 1101, and the second electrode P2 of the power device to be tested 1102 and the negative electrode of the dc power source 1101 are both grounded. The dc power source 1101 provides a dc bias voltage to the power device 1102 to be tested, and the driving voltage providing sub-circuit 1103 provides a driving voltage to the power device 1102 to be tested. Specifically, the driving voltage supply sub-circuit 1103 supplies a driving voltage to the power device 1102 to be tested by inputting a pulse signal.
The turn-on control sub-circuit 1104 is connected between the driving voltage providing sub-circuit 1103 and the control electrode of the power device 1102 to be tested, and is used for controlling the driving voltage applied to the control electrode of the power device 1102 to be tested, so as to control the turn-on time of the power device 1102 to be tested. Specifically, the turn-on control sub-circuit 1104 controls the driving voltage applied to the control electrode of the power device 1102 to be tested by inputting the pulse signal.
Referring to fig. 3, fig. 3 is a circuit diagram of an alternative circuit structure of the power device testing circuit 110, which is described by taking the power device 1102 to be tested (Q1 in the figure) as an NPN bipolar junction transistor. The first electrode P1 of the power device 1102 to be tested is a collector of the NPN bipolar junction transistor, the second electrode P2 is an emitter of the NPN bipolar junction transistor, and the control electrode con is a base of the NPN bipolar junction transistor.
The positive pole of the dc power source 1101 (VCC in the figure) is connected to the collector of the power device 1101 to be tested, and the negative pole is grounded.
The driving voltage supply sub-circuit 1103 may include a second resistor R2, a third resistor R3, a first diode D1, a second diode D2, and a first pulse signal source (HF pulse in the figure). The second resistor R2 and the third resistor R3 are connected in series, and the first pulse signal is sourced from the base of the NPN bipolar junction transistor.
The cathode of the first diode D1 is connected between the second resistor R2 and the third resistor R3, the anode of the first diode D1 is connected to the anode of the second diode D2, and the cathode of the second diode D2 is grounded.
Referring to fig. 4 again, the conduction control sub-circuit 1104 may include a first resistor R1, a fourth resistor R4, a third diode D3, a switch tube, and a second pulse signal source (Single pulse in the figure).
The switch tube comprises a control electrode, a first electrode and a second electrode, in this embodiment, the switch tube may be an enhancement MOSFET, the first electrode of the switch tube may be a drain electrode of the enhancement MOSFET, the second electrode may be a source electrode of the enhancement MOSFET, and the control electrode may be a gate electrode of the enhancement MOSFET.
The first electrode of the switch tube is connected between the output terminal of the driving voltage supply sub-circuit 1103 and the control electrode con of the power device 1101 to be tested, and the second electrode of the switch tube is grounded.
The first resistor R1 is connected between the control electrode of the switching tube and the second pulse signal source;
the cathode of the third diode D3 is connected between the first resistor R1 and the control electrode of the switching tube, and the anode of the third diode D3 is grounded;
one end of the fourth resistor R4 is connected with the control electrode of the switch tube, and the other end of the fourth resistor R4 is grounded.
In the embodiment of the application, a first pulse signal source inputs a high-frequency pulse signal, and a second pulse signal source inputs a single pulse signal.
The operation of the power device avalanche tolerance testing system 10 will be described with reference to fig. 3.
The first pulse signal source acts on the base of the power device 1101 to be tested through the second resistor R2 and the third resistor R3 to drive the power device 1101 to be tested. When the power device to be tested 1101 is forward biased to be on, the second pulse signal source controls the on-time of the power device to be tested 1101 through a driving switch tube (MOSFET). The electric signal acquisition circuit acquires voltage drop and conduction current when the power device 1101 to be tested is conducted, and the avalanche tolerance calculation subsystem calculates energy when the power device 1101 to be tested is conducted in a forward bias mode. By adjusting the input first pulse signal, the energy of the power device 1101 to be tested when the power device 1101 to be tested is turned on before the secondary breakdown occurs is accumulated to obtain the avalanche tolerance of the transistor Q1 to be tested.
Referring to fig. 4, an embodiment of the present application further provides a testing method based on the power device avalanche tolerance testing system 10, where the testing method specifically includes the following steps:
step S401, adjusting an ambient temperature of a working environment where the power device to be tested 1101 is located.
Optionally, the operating ambient temperature of the power device under test 1101 is changed by the ambient temperature control subsystem 140.
Step S402, collecting the voltage drop and the current when the power device 1101 to be tested is turned on.
Optionally, the voltage drop and the on-current of the power device to be tested 1101 when conducting are collected by the electrical signal collecting circuit 120. Specifically, the on-time and the on-energy of the power device to be tested 1101 may be controlled by adjusting the first pulse signal and the second pulse signal.
Step S403, calculating the energy of the to-be-tested power device 1101 when conducting according to the collected voltage drop and current.
Optionally, the energy of the power device to be tested 1101 when conducting is calculated by the avalanche tolerance calculation subsystem 130 according to the voltage drop and the current collected by the electrical signal collection circuit 120.
Step S404, controlling the conduction time of the power device to be tested 1101, and accumulating the energy of the power device to be tested 1101 before the secondary breakdown occurs, when the power device to be tested 1101 is conducted, to obtain the avalanche tolerance required by the power device to be tested 1101 when the secondary breakdown occurs.
To sum up, the embodiment of the present application provides a power device avalanche tolerance test system and a test method, including a power device test circuit, an electrical signal acquisition circuit, an avalanche tolerance calculation subsystem, and an environment temperature control subsystem for providing an adjustable working environment temperature for a power device to be tested. The electric signal acquisition circuit is connected with a power device to be tested in the power device test circuit and is used for acquiring the voltage drop and the current of the power device to be tested when the power device to be tested is conducted; the avalanche tolerance calculation subsystem is connected with the electric signal acquisition circuit and is used for calculating the avalanche tolerance required by the secondary breakdown of the power device to be tested according to the voltage drop and the current acquired by the electric signal acquisition circuit. The avalanche tolerance of the power device to be tested at different working environment temperatures is tested by changing the working environment temperatures of the power device to be tested, so that the avalanche tolerance of the power device to be tested is compared and analyzed.
The above description is only a preferred embodiment of the present application and is not intended to limit the present application, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present application shall be included in the protection scope of the present application.
Claims (10)
1. A power device avalanche tolerance testing system, comprising: the system comprises a power device test circuit, an electric signal acquisition circuit, an avalanche tolerance calculation subsystem and an environment temperature control subsystem;
the electric signal acquisition circuit is connected with a power device to be tested in the power device test circuit and is used for acquiring the voltage drop and the current of the power device to be tested when the power device to be tested is conducted;
the avalanche tolerance calculation subsystem is connected with the electric signal acquisition circuit and is used for calculating the avalanche tolerance required by the secondary breakdown of the power device to be tested according to the voltage drop and the current acquired by the electric signal acquisition circuit;
the environment temperature control subsystem provides adjustable working environment temperature for the power device to be tested.
2. The power device avalanche tolerance testing system according to claim 1, wherein the ambient temperature control subsystem includes a temperature controlled box, the power device to be tested being disposed within the temperature controlled box.
3. The power device avalanche tolerance testing system according to claim 1 or 2, wherein the power device testing circuit includes: the device comprises a direct current power supply, a power device to be tested, a driving voltage supply sub-circuit and a conduction control sub-circuit;
the power device to be tested comprises a control electrode, a first electrode and a second electrode, wherein the control electrode is connected with the driving voltage supply sub-circuit, the first electrode is connected with the anode of the direct current power supply, and the second electrode is respectively grounded with the cathode of the direct current power supply; the direct current power supply provides direct current bias voltage for the power device to be tested, and the driving voltage providing sub-circuit provides driving voltage for the power device to be tested;
the conduction control sub-circuit is connected between the driving voltage supply sub-circuit and the control electrode of the power device to be tested and is used for controlling the driving voltage applied to the control electrode of the power device to be tested so as to control the conduction time of the power device to be tested.
4. The power device avalanche tolerance testing system according to claim 3, wherein the power device to be tested includes insulated gate bipolar transistors, metal-oxide semiconductor field effect transistors and bipolar junction transistors.
5. The power device avalanche tolerance testing system according to claim 4, wherein the power device to be tested is an NPN bipolar junction transistor, the first electrode of the power device to be tested is a collector of the NPN bipolar junction transistor, the second electrode is an emitter of the NPN bipolar junction transistor, and the control electrode is a base of the NPN bipolar junction transistor.
6. The power device avalanche tolerance testing system according to claim 5, wherein the driving voltage providing sub-circuit includes a second resistor, a third resistor, a first diode, a second diode, and a first pulse signal source;
the second resistor and the third resistor are connected in series between the first pulse signal source and a control electrode of the power device to be tested;
the cathode of the first diode is connected between the second resistor and the third resistor, the anode of the first diode is connected with the anode of the second diode, and the cathode of the second diode is grounded.
7. The power device avalanche tolerance testing system according to claim 6, wherein the conduction control sub-circuit includes a first resistor, a fourth resistor, a third diode, a switch tube and a second pulse signal source;
the switching tube comprises a control electrode, a first electrode and a second electrode, the first electrode of the switching tube is connected between the output end of the driving voltage supply sub-circuit and the control electrode of the power device to be tested, and the second electrode is grounded;
the first resistor is connected between the control electrode of the switching tube and the second pulse signal source;
the cathode of the third diode is connected between the first resistor and the control electrode of the switching tube, and the anode of the third diode is grounded;
one end of the fourth resistor is connected with the control electrode of the switch tube, and the other end of the fourth resistor is grounded.
8. The system for testing avalanche tolerance of a power device of claim 7, wherein the switch is an enhancement MOSFET, the first electrode of the switch is a drain of the enhancement MOSFET, the second electrode of the switch is a source of the enhancement MOSFET, and the control electrode of the switch is a gate of the enhancement MOSFET.
9. The power device avalanche tolerance testing system according to claim 8, wherein said first pulsed signal source inputs a high frequency pulsed signal and said second pulsed signal source inputs a single pulsed signal.
10. A power device avalanche tolerance testing method applied to the power device avalanche tolerance testing system according to any one of claims 1 to 9, the method comprising:
adjusting the environmental temperature of the working environment of the power device to be tested;
collecting the voltage drop and the current when the power device to be tested is conducted;
calculating the energy of the power device to be tested when the power device is conducted according to the acquired voltage drop and current;
and controlling the conduction time of the power device to be tested, and accumulating the energy of the power device to be tested when the power device to be tested is conducted before the secondary breakdown occurs to obtain the avalanche tolerance required by the power device to be tested when the secondary breakdown occurs.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN202010331303.7A CN111381144A (en) | 2020-04-24 | 2020-04-24 | Power device avalanche tolerance test system and test method |
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| CN202010331303.7A CN111381144A (en) | 2020-04-24 | 2020-04-24 | Power device avalanche tolerance test system and test method |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112763880A (en) * | 2020-12-23 | 2021-05-07 | 广州广电计量检测（上海）有限公司 | Repeated avalanche tolerance test system |
| CN112763881A (en) * | 2020-12-23 | 2021-05-07 | 广电计量检测（湖南）有限公司 | Avalanche test parameter selection method and device, computer equipment and storage medium |
| CN113740696A (en) * | 2021-09-26 | 2021-12-03 | 上海陆芯电子科技有限公司 | Testing device and testing method for power diode |
-
2020
- 2020-04-24 CN CN202010331303.7A patent/CN111381144A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112763880A (en) * | 2020-12-23 | 2021-05-07 | 广州广电计量检测（上海）有限公司 | Repeated avalanche tolerance test system |
| CN112763881A (en) * | 2020-12-23 | 2021-05-07 | 广电计量检测（湖南）有限公司 | Avalanche test parameter selection method and device, computer equipment and storage medium |
| CN112763881B (en) * | 2020-12-23 | 2024-05-14 | 广电计量检测（湖南）有限公司 | Avalanche test parameter selection method, avalanche test parameter selection device, computer equipment and storage medium |
| CN113740696A (en) * | 2021-09-26 | 2021-12-03 | 上海陆芯电子科技有限公司 | Testing device and testing method for power diode |
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