CN221127122U - Gate driving circuit and electronic equipment - Google Patents
Gate driving circuit and electronic equipment Download PDFInfo
- Publication number
- CN221127122U CN221127122U CN202322926348.0U CN202322926348U CN221127122U CN 221127122 U CN221127122 U CN 221127122U CN 202322926348 U CN202322926348 U CN 202322926348U CN 221127122 U CN221127122 U CN 221127122U
- Authority
- CN
- China
- Prior art keywords
- gate
- turn
- branch
- resistor
- power device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000004146 energy storage Methods 0.000 claims description 4
- 238000002955 isolation Methods 0.000 description 11
- 238000010586 diagram Methods 0.000 description 6
- 238000000034 method Methods 0.000 description 4
- 238000006243 chemical reaction Methods 0.000 description 3
- 230000006978 adaptation Effects 0.000 description 2
- 238000013475 authorization Methods 0.000 description 1
- 238000011217 control strategy Methods 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000011084 recovery Methods 0.000 description 1
Landscapes
- Power Conversion In General (AREA)
Abstract
The disclosure relates to a gate driving circuit and electronic equipment in the technical field of power electronics. Comprising the following steps: the gate driving chip is respectively connected with each opening branch and each closing branch, each opening branch and each closing branch are respectively connected with a power device to be driven in the controller, each opening branch comprises a gate opening resistor and a gate opening switching tube which are connected in series, and each closing branch comprises a gate closing resistor and a gate closing switching tube which are connected in series; the gate driving chip is used for controlling the on state of each gate on-off switch tube according to the working condition of the controller so as to adjust the resistance value of the on-off drive resistor of the power device, and controlling the on state of each gate off-off switch tube so as to adjust the resistance value of the off-off drive resistor of the power device. Therefore, the resistance value of the gate electrode driving resistor can be adaptively adjusted according to the working condition of the controller, and the reliability of the gate electrode control loop is improved.
Description
Technical Field
The disclosure relates to the technical field of power electronics, in particular to a gate driving circuit and electronic equipment.
Background
In the field of new energy automobiles, a power device such as an IGBT (Insulated Gate Bipolar Transistor ) is used as one of core devices of a motor controller in an electric automobile, and the design of the gate resistance is a key factor for determining the working performance of the power device.
At present, the gate control of an electric drive power device of an electric automobile adjusts the switching speed of the power device by adjusting the value of a drive resistor, the switching speed of the power device influences the loss of the power device and also influences the safety of the power device in the switching process, the safety of the device in the switching process is ensured by selecting the drive resistor, and meanwhile, the loss is ensured to be as small as possible. After the design calibration is completed, the driving resistance is determined and cannot be changed. Because the switching speed of the power device is affected by the working condition of electric drive, such as direct current voltage, switching current and device junction temperature, the fixed driving resistor cannot ensure that the loss of the power device under different working conditions is optimal, so that the loss of the electric drive can be increased, and the overall efficiency of the electric drive is reduced.
Disclosure of utility model
In order to overcome the problems in the related art, the present disclosure provides a gate driving circuit and an electronic device.
According to a first aspect of embodiments of the present disclosure, there is provided a gate driving circuit including: the gate driving chip is respectively connected with each opening branch and each closing branch, each opening branch and each closing branch are respectively connected with a power device to be driven in the controller, wherein each opening branch comprises a gate opening resistor and a gate opening switching tube which are connected in series, and each closing branch comprises a gate closing resistor and a gate closing switching tube which are connected in series;
The gate driving chip is used for controlling the on state of each gate on-off switch tube according to the working condition of the controller so as to adjust the resistance value of the on-off drive resistor of the power device to be driven, and controlling the on state of each gate off-off switch tube so as to adjust the resistance value of the off-off drive resistor of the power device to be driven.
Optionally, the gate driving chip includes a plurality of open signal output interfaces, where the plurality of open signal output interfaces are connected with the plurality of open branches in a one-to-one correspondence manner;
The gate driving chip further comprises a plurality of turn-off signal output interfaces, and the turn-off signal output interfaces are connected with the turn-off branches in a one-to-one correspondence manner.
Optionally, the gate turn-off switch tube comprises a MOS tube or a triode; the gate turn-on switching tube comprises an MOS tube or a triode.
Optionally, the gate turn-on switching tube comprises a PMOS tube, and the gate turn-off switching tube comprises an NMOS tube;
For each opening branch, the source electrode of the PMOS tube included in the opening branch is connected with a preset opening power supply, the grid electrode of the PMOS tube is connected with an opening signal output interface corresponding to the opening branch, the drain electrode of the PMOS tube is connected with the first end of a gate electrode opening resistor included in the opening branch, and the second end of the gate electrode opening resistor included in the opening branch is connected with the grid electrode of the power device to be driven;
For each turn-off branch, a source electrode of an NMOS tube included in the turn-off branch is connected with a preset turn-off power supply, a grid electrode of the NMOS tube is connected with a turn-off signal output interface corresponding to the turn-off branch, a drain electrode of the NMOS tube is connected with a first end of a gate turn-off resistor included in the turn-off branch, and a second end of a gate turn-off resistor included in the turn-off branch is connected with a grid electrode of the power device to be driven.
Optionally, the plurality of parallel opening branches include a first opening branch and a second opening branch, and the gate opening resistances included in the first opening branch and the second opening branch are different in resistance value.
Optionally, the plurality of parallel turn-off branches include a first turn-off branch and a second turn-off branch, and the gate turn-off resistors included in the first turn-off branch and the second turn-off branch have different resistances.
Optionally, the resistance value of the gate electrode on resistance included in the first on branch is smaller than the resistance value of the gate electrode on resistance included in the second on branch, and the resistance value of the gate electrode off resistance included in the first off branch is smaller than the resistance value of the gate electrode off resistance included in the second off branch.
Optionally, when the controller is in the first working condition, the gate driving chip is used for controlling the gate turn-on switching tube included in the first turn-on branch and the second turn-on branch to be turned on in the stage of turning on the power device to be driven, and controlling the gate turn-off switching tube included in the first turn-off branch and the second turn-off branch to be turned on in the stage of turning off the power device to be driven;
The gate driving chip is further configured to control, when the controller is in a second working condition, the gate turn-on switching tube included in the second turn-on branch to be turned on in a stage of turning on the power device to be driven, and control the gate turn-off switching tube included in the second turn-off branch to be turned on in a stage of turning off the power device to be driven;
The gate driving chip is further configured to control, when the controller is in a third working condition, the gate turn-on switching tube included in the first turn-on branch to be turned on in a stage of turning on the power device to be driven, and control the gate turn-off switching tube included in the first turn-off branch to be turned on in a stage of turning off the power device to be driven.
According to a second aspect of embodiments of the present disclosure, there is provided an electronic device comprising a gate driving circuit and a controller as in any one of the first aspects of the present disclosure, the gate driving circuit being for driving a power device to be driven in the controller.
Optionally, the controller comprises at least one of a motor controller, a photovoltaic inverter, a wind power converter, and an energy storage converter.
By adopting the technical scheme, the resistance of the on-drive resistor and the resistance of the off-drive resistor can be adaptively adjusted according to the working condition of the controller, so that the overall efficiency of electric drive is improved. In addition, the gate driving chip directly controls the conduction state of each on branch and each off branch, and an I/O interface and an isolation channel are not required to be additionally added, so that the structure of the gate driving circuit is simplified, the occupied space and the hardware cost of the gate driving circuit are effectively reduced, and the reliability of a gate control loop is improved.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the disclosure and together with the description, serve to explain the principles of the disclosure.
Fig. 1 is a schematic diagram showing a related art gate driving circuit according to an exemplary embodiment.
Fig. 2 is a block diagram illustrating a gate drive circuit according to an exemplary embodiment.
Fig. 3 is a circuit diagram illustrating a gate driving circuit according to an exemplary embodiment.
Detailed Description
Reference will now be made in detail to exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, the same numbers in different drawings refer to the same or similar elements, unless otherwise indicated. The implementations described in the following exemplary examples are not representative of all implementations consistent with the present disclosure. Rather, they are merely examples of apparatus and methods consistent with some aspects of the present disclosure as detailed in the accompanying claims.
It should be noted that, all actions of acquiring signals, information or data in the present application are performed under the condition of conforming to the corresponding data protection rule policy of the country of the location and obtaining the authorization given by the owner of the corresponding device.
In an electric driving system of an electric automobile, a micro control unit MCU sends a pulse width modulation signal, and the pulse width modulation signal is converted into a gate signal capable of driving a power device through isolation driving to control the on and off of an IGBT or MOSFET of the power device, so that a motor is controlled.
Switching losses are generated during the switching on and off of the power device, and are an important component of the total loss of the electric drive, and have an important influence on the efficiency of the electric drive, so that the faster the switching speed is, the better the electric drive efficiency is. Meanwhile, in the switching process, voltage and current stress can be generated on the power device due to reverse recovery action of the diode and stray inductance on the direct current bus, and the faster the switching speed is, the larger the voltage and current stress is, and the damage of the power device can be caused by the overlarge voltage and current stress. Therefore, the control of the switching speed needs to be comprehensively considered, and the switching loss is reduced as much as possible on the premise of ensuring the safety of the device under the worst working condition.
Illustratively, fig. 1 is a schematic diagram of a gate driving circuit in the related art, which is shown according to an exemplary embodiment. As shown in fig. 1, in one scheme of the related art, firstly, the MCU generates and sends a PWM signal to the isolation driving module, for example, the isolation driving module receives the PWM signal sent by the MCU through one interface, for example, INP interface, then, the isolation driving module performs level conversion, outputs a converted signal through another interface, for example, gate interface, and then, the signal is input to the gates of the power devices S1 to S6 through the driving resistor R to control the power devices S1 to S6 to be turned on or off, thereby controlling the motor EM to operate.
Therefore, the driving resistor is fixed aiming at different working conditions, so that the switching speed is also fixed, under the working conditions of smaller voltage and current stress, the control of the switching speed is too conservative, the switching loss can be larger, and the overall efficiency of electric driving can be relatively lower.
In addition, in another scheme of the related art, each gate resistor corresponds to one MOS tube and one path of isolation channel, and the MCU can also control the MOS tube to be turned on and off through one path of isolation signal so as to change the resistance value of the driving resistor of the power device. However, in this scheme, each gate resistor requires one MOS transistor, one isolation channel, and one input/output (I/O), and n resistors, n MOS transistors, and n isolation channels are required for n channels. Considering an upper on stage and an off stage, the MCU needs to provide 2n paths of I/O ports, which is a huge burden on resources of the MCU; the use of a large number of devices not only has the problem of heat dissipation, but also brings the problem of reliability of a gate control loop; in addition, additional I/O interfaces and isolation channels are required, increasing hardware costs.
In view of this, the disclosure provides a gate driving circuit and an electronic device, which can adaptively adjust the resistance of the on driving resistor and the resistance of the off driving resistor according to the working condition of the controller, so as to improve the overall efficiency of electric driving. In addition, the structure of the gate driving circuit is simpler, the occupied space and hardware cost of the gate driving circuit are effectively reduced, and the reliability of a gate control loop is improved.
Fig. 2 is a block diagram illustrating a gate drive circuit according to an exemplary embodiment. As shown in fig. 2, the gate driving circuit includes a gate driving chip 10, a plurality of parallel turn-on branches 20, and a plurality of parallel turn-off branches 30. The number of the off branches and the number of the on branches can be the same or different.
The gate driving chip 10 is respectively connected with each on branch 20 and each off branch 30, each on branch 20 and each off branch 30 are respectively connected with a power device S to be driven in the controller, each on branch 20 comprises a gate on resistor 201 and a gate on switch tube 202 which are connected in series, and the off branch 30 comprises a gate off resistor 301 and a gate off switch tube 302 which are connected in series. The gate driving chip 10 is configured to control a conducting state of each gate on/off switching tube according to a working condition of the controller, so as to adjust a resistance value of an on/off driving resistor of the power device, and control a conducting state of each gate off/off switching tube, so as to adjust a resistance value of an off/off driving resistor of the power device.
In one embodiment, the gate driving chip 10 includes a plurality of on signal output interfaces, the on signal output interfaces are connected to the on branches in a one-to-one correspondence, and similarly, the gate driving chip 10 further includes a plurality of off signal output interfaces, and the off signal output interfaces are connected to the off branches in a one-to-one correspondence.
The driving signals output by each opening signal output interface are used for driving the on-off of the gate electrode opening switching tube included in the corresponding connected opening branch circuit, and the driving signals output by each closing signal output interface are used for driving the on-off of the gate electrode closing switching tube included in the corresponding connected closing branch circuit.
In the present disclosure, the controller may be any controller provided with a power device, such as a motor controller, a photovoltaic inverter, a wind power converter, and an energy storage converter. The power device S can be an IGBT or a MOS tube. Wherein, each on branch 20 and each off branch 30 are used for being connected with the power device S respectively, which means that each on branch 20 and each off branch 30 are used for being connected with the gate of the power device S respectively.
In one possible manner, first, according to parameters such as torque, rotational speed direct current bus voltage, junction temperature of a power device and the like, working conditions of a controller are divided into a first working condition used for representing an efficient area, a second working condition used for representing a low-efficient area and a third working condition used for representing a medium-efficient area. The first working condition corresponds to parameters such as higher torque, rotating speed direct current bus voltage, junction temperature of the power device, the second working condition corresponds to parameters such as lower torque, rotating speed direct current bus voltage, junction temperature of the power device, and the like, and the third working condition corresponds to parameters such as torque, rotating speed direct current bus voltage, junction temperature of the power device, and the like, and the parameters are located between the first working condition and the second working condition. The high-efficiency zone, the medium-efficiency zone and the low-efficiency zone are used for representing high working efficiency, medium working efficiency and low working efficiency of the controller respectively. For example, a condition in which the working efficiency is greater than the first threshold may be determined as a first condition, a condition in which the working efficiency is less than the second threshold may be determined as a second condition, and a condition in which the working efficiency is greater than the second threshold and less than the first threshold may be determined as a third condition.
It should be appreciated that the operating conditions of the controller may be divided according to actual requirements, for example, may be divided into more operating conditions and may be divided into fewer operating conditions, which is not limited by the present disclosure. In addition, the working conditions can be divided according to the parameters such as torque, rotating speed, direct current bus voltage, junction temperature of the power device and the like according to experience.
In the present disclosure, the gate driving chip 10 may control both the turn-on speed and the turn-off speed of the power device.
In the power device opening stage, the gate driving chip 10 may be connected to the MCU, and configured to obtain a PWM signal and a working condition of the controller from the MCU, further perform level conversion on the PWM signal based on the working condition of the controller, obtain a converted signal, and control a conductive state of each gate turn-on switching tube 202 based on the converted signal, so as to adjust a resistance value of an turn-on driving resistor of the power device. For example, the corresponding relation between different working conditions and the resistance value of the opening driving resistor is preset, the gate driving chip 10 determines the resistance value of the opening driving resistor corresponding to the working condition according to the working condition of the controller, and further determines the opening branch to be conducted based on the resistance value of the opening driving resistor and the resistance value of the gate opening resistor included in each opening branch, and controls the gate opening switching tube included in the opening branch to be conducted, and other gate opening switching tubes are disconnected. Or, as another example, the corresponding relation between different working conditions and each opening branch is preset, where the corresponding relation is used to indicate the opening branch to be turned on under each working condition, and the gate driving chip 10 determines the opening branch to be turned on corresponding to the working condition according to the working condition of the controller, so as to control the gate opening switching tubes included in the opening branch to be turned on, and other gate opening switching tubes to be turned off.
In the power device closing stage, the gate driving chip 10 acquires the PWM signal and the working condition of the controller from the MCU, further performs level conversion on the PWM signal based on the working condition of the controller, obtains a converted signal, and controls the on state of each gate turn-off switching tube 302 based on the converted signal, so as to adjust the resistance value of the switching driving resistor of the power device. The specific control manner is similar to that of the power device, and the disclosure will not be repeated.
It should be understood that the control strategy of the gate driving chip 10 for controlling the on state of the gate turn-on switching tube based on the working condition of the controller belongs to a more conventional technical means, and the disclosure is not limited thereto.
By adopting the technical scheme, the resistance of the on-drive resistor and the resistance of the off-drive resistor can be adaptively adjusted according to the working condition of the controller, so that the overall efficiency of electric drive is improved. In addition, the gate driving chip directly controls the conduction state of each on branch and each off branch, and an I/O interface and an isolation channel are not required to be additionally added, so that the structure of the gate driving circuit is simplified, the occupied space and the hardware cost of the gate driving circuit are effectively reduced, and the reliability of a gate control loop is improved.
In the present disclosure, the switching transistor may include a MOS transistor or a triode. Illustratively, the gate turn-off switching transistor includes a MOS transistor or a triode; the gate turn-on switching transistor comprises a MOS transistor or a triode. The MOS tube can be an N-type MOS tube (NMOS tube) or a P-type MOS tube (PMOS tube). In order to further simplify the structure of the gate driving circuit, the gate turn-on switching tube can be a PMOS tube or a triode, and the gate turn-off switching tube can be an NMOS tube or a triode.
In one embodiment, for each opening branch, a source electrode of a PMOS tube included in the opening branch is connected with a preset opening power supply, a grid electrode of the PMOS tube is connected with an opening signal output interface corresponding to the opening branch, a drain electrode of the PMOS tube is connected with a first end of a gate electrode opening resistor included in the opening branch, and a second end of the gate electrode opening resistor included in the opening branch is connected with a grid electrode of a power device to be driven; for each turn-off branch, the source electrode of an NMOS tube included in the turn-off branch is connected with a preset turn-off power supply, the grid electrode of the NMOS tube is connected with a turn-off signal output interface corresponding to the turn-off branch, the drain electrode of the NMOS tube is connected with the first end of a gate turn-off resistor included in the turn-off branch, and the second end of the gate turn-off resistor included in the turn-off branch is connected with the grid electrode of the power device to be driven.
For convenience of description, the following description will take an example that the plurality of parallel turn-on branches includes a first turn-on branch and a second turn-on branch, and the plurality of parallel turn-off branches includes a first turn-off branch and a second turn-off branch.
Fig. 3 is a circuit diagram illustrating a gate driving circuit according to an exemplary embodiment. As shown in fig. 3, the gate driving chip includes two ON signal output interfaces respectively denoted as a g_on1 interface and a g_on2 interface, and also includes two OFF signal output interfaces respectively denoted as a g_off1 interface and a g_off2 interface. The first switching-on branch circuit comprises a PMOS tube PMOS1 and a gate electrode switching-on resistor R1 which are connected in series, the second switching-on branch circuit comprises a PMOS tube PMOS2 and a gate electrode switching-on resistor R2 which are connected in series, the first switching-off branch circuit comprises an NMOS tube NMOS1 and a gate electrode switching-off resistor R3 which are connected in series, and the second switching-off branch circuit comprises an NMOS tube NMOS2 and a gate electrode switching-off resistor R4 which are connected in series. The gate turn-on resistor R1 and the gate turn-on resistor R2 have different resistance values, and the gate turn-off resistor R3 and the gate turn-off resistor R4 have different resistance values. For example, the resistance of the gate-on resistor R1 is smaller or larger than the resistance of the gate-on resistor R2, and the resistance of the gate-off resistor R3 is smaller or larger than the resistance of the gate-off resistor R4.
In fig. 3, the power device S to be driven includes a power device S1. The source electrode of the PMOS1 is connected with a preset power-ON source Vcc, the grid electrode of the PMOS1 is connected with a G_On1 interface, the drain electrode of the PMOS1 is connected with the first end of a gate-ON resistor R1, and the second end of the gate-ON resistor R1 is connected with the grid electrode of the power device S1; the source of PMOS2 is connected with a preset power-ON source Vcc, the grid of PMOS2 is connected with a G_On2 interface, the drain of PMOS2 is connected with the first end of a gate-ON resistor R2, and the second end of gate-ON resistor R2 is connected with the grid of a power device S1.
It should be understood that only one power device S1 is shown in fig. 3, and in practical applications, the gate driving circuit may be connected to the gates of the power devices, for driving the power devices on or off.
The source electrode of the NMOS1 is connected with a preset turn-OFF power supply Vee, the grid electrode of the NMOS1 is connected with a G_OFF1 interface, the drain electrode of the NMOS1 is connected with the first end of a gate turn-OFF resistor R3, and the second end of the gate turn-OFF resistor R3 is connected with the grid electrode of the power device S1; the source of NMOS2 is connected with a preset turn-OFF power source Vee, the grid of NMOS2 is connected with a G_OFF2 interface, the drain of NMOS2 is connected with the first end of a gate turn-OFF resistor R4, and the second end of gate turn-OFF resistor R4 is connected with the grid of a power device S1.
In one possible implementation manner, the resistance value of the gate-on resistor R1 included in the first switching-on branch is smaller than the resistance value of the gate-on resistor R2 included in the second switching-on branch, and the resistance value of the gate-off resistor R3 included in the first switching-off branch is smaller than the resistance value of the gate-off resistor R4 included in the second switching-off branch.
When the controller is in a first working condition, in the stage of turning ON the power device, the gate driving chip controls the PMOS1 and the PMOS2 to be turned ON, namely, the G_On1 interface and the G_On2 interface of the gate driving chip respectively output low-level signals, so that the PMOS1 and the PMOS2 are controlled to be turned ON, and at the moment, the resistance value of the turn-ON driving resistor of the power device is the equivalent resistance value of the parallel connection of the gate turn-ON resistor R1 and the gate turn-ON resistor R2. In the stage of turning OFF the power device, the gate driving chip controls the NMOS1 and the NMOS2 to be turned on, that is, the g_off1 interface and the g_off2 interface of the gate driving chip 10 output high level signals respectively, so as to control the NMOS1 and the NMOS2 to be turned on, and at this time, the resistance value of the turn-OFF driving resistor of the power device is the parallel equivalent resistance value of the gate turn-OFF resistor R3 and the gate turn-OFF resistor R4.
When the controller is in a first working condition for representing the high-efficiency area, the first switching-on branch and the second switching-on branch are all switched on in the stage of switching on the power device, at the moment, the resistance value of the switching-on driving resistor is minimum, and then the switching-on speed of the power device is maximum, and in the stage of switching-off, the first switching-off branch and the second switching-off branch are all switched on and connected in parallel, at the moment, the resistance value of the switching-off driving resistor is minimum, and then the switching-off speed of the power device is maximum. Therefore, the loss of the power device is minimized when turning on and off.
When the controller is in the second working condition for representing the low-efficiency area, in the stage of turning ON the power device, the gate electrode driving chip controls the PMOS2 to be turned ON and turned off, namely, the G_On1 interface of the gate electrode driving chip outputs a high-level signal, the G_On2 interface outputs a low-level signal, and then the PMOS2 to be turned ON and turned off, and at the moment, the resistance value of the ON driving resistor of the power device is the resistance value of the gate electrode ON resistor R2. In the stage of turning OFF the power device, the gate driving chip controls the NMOS2 to be turned on and turned OFF by NMOS1, namely, the G_OFF2 interface of the gate driving chip outputs a high level signal, the G_OFF1 interface outputs a low level signal, and then the NMOS2 to be turned on and turned OFF by NMOS1 is controlled, and at the moment, the resistance value of the turn-OFF drive resistor of the power device is the resistance value of the gate turn-OFF resistor R4.
When the controller is in a third working condition for representing the middle-effect area, in the stage of turning ON the power device, the gate electrode driving chip controls the PMOS1 to be turned ON and the PMOS2 to be turned off, namely, the G_On1 interface of the gate electrode driving chip outputs a low-level signal, the G_On2 interface outputs a high-level signal, and then the PMOS1 to be turned ON and the PMOS2 to be turned off, and at the moment, the resistance value of the ON driving resistor of the power device is the resistance value of the gate electrode ON resistor R1. In the stage of turning OFF the power device, the gate driving chip controls the NMOS1 to turn on and NMOS2 to turn OFF, namely, the G_OFF1 interface of the gate driving chip outputs a high level signal, the G_OFF2 interface outputs a low level signal, and then the NMOS1 to turn on and NMOS2 to turn OFF, and at the moment, the resistance value of the turn-OFF driving resistor of the power device is the resistance value of the gate turn-OFF resistor R3.
Therefore, three-gear adjustment of the driving resistor can be realized only through the two parallel switching-on branches and the two parallel switching-off branches so as to meet three different working conditions of the controller, and on the premise of ensuring the voltage and current stress safety of the power device, the switching loss of the power device is reduced, and the efficiency of the power device is improved.
It should be understood that more gear adjustment of the driving resistor can be realized by setting a greater number of parallel switching-on branches and switching-off branches so as to meet more working conditions of the controller.
In the present disclosure, the gate driving circuit is adopted, and the working condition of the controller is reasonably defined and the resistance included in each parallel branch is reasonably selected, so that the working efficiency of the electric drive under most working conditions is high, the total efficiency of the electric drive under all working conditions is improved, and the endurance of the electric automobile is improved.
Based on the same concept, the present disclosure also provides an electronic device including the gate driving circuit and the controller provided by the present disclosure, where the gate driving circuit is used to drive a power device to be driven in the controller.
The electronic device may be an electric automobile, a ship, an aircraft, or the like. The controller includes at least one of a motor controller, a photovoltaic inverter, a wind power converter, and an energy storage converter.
Other embodiments of the disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the disclosure. This application is intended to cover any adaptations, uses, or adaptations of the disclosure following, in general, the principles of the disclosure and including such departures from the present disclosure as come within known or customary practice within the art to which the disclosure pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the disclosure being indicated by the following claims.
It is to be understood that the present disclosure is not limited to the precise arrangements and instrumentalities shown in the drawings, and that various modifications and changes may be effected without departing from the scope thereof. The scope of the present disclosure is limited only by the appended claims.
Claims (10)
1. A gate drive circuit, comprising: the gate driving chip is respectively connected with each opening branch and each closing branch, each opening branch and each closing branch are respectively connected with a power device to be driven in the controller, wherein each opening branch comprises a gate opening resistor and a gate opening switching tube which are connected in series, and each closing branch comprises a gate closing resistor and a gate closing switching tube which are connected in series;
The gate driving chip is used for controlling the on state of each gate on-off switch tube according to the working condition of the controller so as to adjust the resistance value of the on-off drive resistor of the power device to be driven, and controlling the on state of each gate off-off switch tube so as to adjust the resistance value of the off-off drive resistor of the power device to be driven.
2. The gate driving circuit according to claim 1, wherein the gate driving chip comprises a plurality of on signal output interfaces, and the on signal output interfaces are connected with the on branches in a one-to-one correspondence manner;
The gate driving chip further comprises a plurality of turn-off signal output interfaces, and the turn-off signal output interfaces are connected with the turn-off branches in a one-to-one correspondence manner.
3. The gate drive circuit of claim 1, wherein the gate turn-off switching transistor comprises a MOS transistor or a triode; the gate turn-on switching tube comprises an MOS tube or a triode.
4. The gate drive circuit of claim 2, wherein the gate-on switching tube comprises a PMOS tube and the gate-off switching tube comprises an NMOS tube;
For each opening branch, the source electrode of the PMOS tube included in the opening branch is connected with a preset opening power supply, the grid electrode of the PMOS tube is connected with an opening signal output interface corresponding to the opening branch, the drain electrode of the PMOS tube is connected with the first end of a gate electrode opening resistor included in the opening branch, and the second end of the gate electrode opening resistor included in the opening branch is connected with the grid electrode of the power device to be driven;
For each turn-off branch, a source electrode of an NMOS tube included in the turn-off branch is connected with a preset turn-off power supply, a grid electrode of the NMOS tube is connected with a turn-off signal output interface corresponding to the turn-off branch, a drain electrode of the NMOS tube is connected with a first end of a gate turn-off resistor included in the turn-off branch, and a second end of a gate turn-off resistor included in the turn-off branch is connected with a grid electrode of the power device to be driven.
5. The gate drive circuit of claim 1, wherein the plurality of parallel turn-on legs comprises a first turn-on leg and a second turn-on leg, and wherein the first turn-on leg and the second turn-on leg comprise gate turn-on resistors having different resistance values.
6. The gate drive circuit of claim 5, wherein the plurality of parallel turn-off legs comprises a first turn-off leg and a second turn-off leg, and wherein the first turn-off leg and the second turn-off leg comprise gate turn-off resistors having different resistances.
7. The gate drive circuit of claim 6, wherein the first turn-on branch comprises a gate turn-on resistor having a resistance less than a gate turn-on resistor of the second turn-on branch, and the first turn-off branch comprises a gate turn-off resistor having a resistance less than a gate turn-off resistor of the second turn-off branch.
8. The gate driving circuit of claim 7, wherein the gate driving chip is configured to control, when the controller is in a first working condition, on-switching of a gate turn-on switching tube included in the first turn-on branch and the second turn-on branch in a power device stage to be driven, and on-switching of a gate turn-off switching tube included in the first turn-off branch and the second turn-off branch in a power device stage to be driven;
The gate driving chip is further configured to control, when the controller is in a second working condition, the gate turn-on switching tube included in the second turn-on branch to be turned on in a stage of turning on the power device to be driven, and control the gate turn-off switching tube included in the second turn-off branch to be turned on in a stage of turning off the power device to be driven;
The gate driving chip is further configured to control, when the controller is in a third working condition, the gate turn-on switching tube included in the first turn-on branch to be turned on in a stage of turning on the power device to be driven, and control the gate turn-off switching tube included in the first turn-off branch to be turned on in a stage of turning off the power device to be driven.
9. An electronic device comprising a gate drive circuit as claimed in any one of claims 1 to 8 for driving a power device to be driven in a controller, and a controller.
10. The electronic device of claim 9, wherein the controller comprises at least one of a motor controller, a photovoltaic inverter, a wind power converter, and an energy storage converter.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202322926348.0U CN221127122U (en) | 2023-10-30 | 2023-10-30 | Gate driving circuit and electronic equipment |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202322926348.0U CN221127122U (en) | 2023-10-30 | 2023-10-30 | Gate driving circuit and electronic equipment |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN221127122U true CN221127122U (en) | 2024-06-11 |
Family
ID=91344563
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202322926348.0U Active CN221127122U (en) | 2023-10-30 | 2023-10-30 | Gate driving circuit and electronic equipment |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN221127122U (en) |
-
2023
- 2023-10-30 CN CN202322926348.0U patent/CN221127122U/en active Active
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN205725436U (en) | Gate driver circuit and include the bridge circuit of gate driver circuit | |
| US7710187B2 (en) | Gate drive circuit | |
| CN104866000B (en) | Gate driving circuit and method with voltage-stablizer | |
| CN113228484B (en) | Gate active control circuit and method and SiC MOSFET gate active control system | |
| CN110768649B (en) | Gate circuit and gate drive circuit of power semiconductor switch | |
| CN106059552A (en) | MOSFET (metal oxide semiconductor field effect transistor) switching dynamic characteristic-based driving circuit | |
| CN113507200A (en) | Power converter and driving circuit thereof | |
| CN110572011B (en) | IGBT drive circuit soft switching device with short-circuit protection | |
| CN107342759B (en) | Digital intelligent IGBT driving method and system | |
| CN108592343A (en) | IGBT pipe gate electrode resistances adjust circuit and air conditioner | |
| JP4971603B2 (en) | Driving method of voltage-driven semiconductor switching element | |
| CN221127122U (en) | Gate driving circuit and electronic equipment | |
| CN110299826A (en) | A kind of spacecraft highly reliable isolated drive circuit of suitable wide duty ratio | |
| JP2016034178A (en) | Power conversion apparatus and control method of the same | |
| CN114714981A (en) | Circuit, system and method for heating battery | |
| CN116215325A (en) | Gate drive circuit, vehicle and active heating control method of gate drive circuit | |
| CN216564500U (en) | Shutdown circuit and electronic device | |
| CN114244339B (en) | Gate drive circuit and electronic device | |
| CN102594099A (en) | Grid drive circuit of intelligent power module | |
| CN204615626U (en) | Intelligent power module circuit and air conditioner | |
| CN104821705A (en) | Intelligent power module circuit and air-conditioner | |
| US10084439B2 (en) | Driver circuit | |
| CN117081370B (en) | Intelligent power module IPM, control method and equipment | |
| CN218783795U (en) | Circuit packaging structure and power supply device | |
| CN220291870U (en) | Driving circuit with strong driving capability and quick switch |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| GR01 | Patent grant |