CN111210786A - Shifting register unit, grid driving circuit, display substrate and display device - Google Patents
Shifting register unit, grid driving circuit, display substrate and display device Download PDFInfo
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- CN111210786A CN111210786A CN202010075524.2A CN202010075524A CN111210786A CN 111210786 A CN111210786 A CN 111210786A CN 202010075524 A CN202010075524 A CN 202010075524A CN 111210786 A CN111210786 A CN 111210786A
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3674—Details of drivers for scan electrodes
- G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
- G09G3/3266—Details of drivers for scan electrodes
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
- G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0264—Details of driving circuits
- G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
Abstract
The disclosure provides a shift register unit, a gate driving circuit, a display substrate and a display device. In the shift register unit, an input module is connected with a first signal input end, a second signal input end and a pull-up node and is configured to output effective voltages successively provided by the first signal input end and the second signal input end to the pull-up node after the effective voltages are superposed. The potential of the pull-up node can be effectively improved, and therefore the driving capability of the shift register unit is improved.
Description
Technical Field
The present disclosure relates to the field of display technologies, and more particularly, to a shift register unit, a gate driving circuit, a display substrate, and a display device.
Background
For the display substrate, for example, a liquid crystal display substrate or an organic light emitting diode display substrate, gate driving circuits are commonly disposed on both sides of the display substrate. The gate driving circuit is composed of cascaded shift register units. Taking the liquid crystal display substrate as an example, the output voltage of the shift register unit is provided to the gate of the driving transistor in each pixel circuit, and the driving capability of the shift register unit determines the driving capability of the driving transistor in the corresponding display substrate. The improvement of the driving capability of the shift register unit is a technical problem that is always sought by those skilled in the art.
Disclosure of Invention
The present disclosure provides a shift register unit, a gate driving circuit, a display substrate and a display device to at least partially solve the technical problems in the prior art.
In a first aspect, a shift register unit is provided, which includes an input module, an output module, a reset module, a pull-down control module and a pull-down module; the input module is connected with a first signal input end, a second signal input end and a pull-up node, and is configured to output effective voltages successively provided by the first signal input end and the second signal input end to the pull-up node after overlapping; the output module is connected with the pull-up node, the clock signal end and the signal output end and is configured to respond to the control of the pull-up node to transmit a signal of the clock signal end to the signal output end; the pull-down control module is connected with the pull-up node, a first power end and a pull-down node and is configured to respond to the control of the pull-up node to transmit a signal of the first power end to the pull-down node respectively; the reset module is connected with a reset signal terminal, a second power terminal and the pull-up node and is configured to respond to the control of the reset signal terminal to transmit a voltage signal provided by the second power terminal to the pull-up node; the pull-down module is connected with the pull-down node, the second power end, the third power end, the signal output end and the pull-up node, and is configured to transmit the voltage provided by the third power end to the signal output end and transmit the voltage provided by the second power end to the pull-up node under the control of the pull-down node.
In some embodiments, the input module includes a first transistor, a second transistor, a third transistor, and a first capacitance; a control electrode and a first electrode of the first transistor are both connected with the first signal input end, and a second electrode of the first transistor is connected with a pre-charging node; a control electrode and a first electrode of the second transistor are both connected with the pre-charging node, and a second electrode of the second transistor is connected with the pull-up node; a control electrode of the third transistor is connected with the pre-charging node, a first electrode of the third transistor is connected with the second signal input end, and a second electrode of the third transistor is connected with a first electrode of the first capacitor; the second pole of the first capacitor is connected with the pre-charging node.
In some embodiments, the output module includes a sixth transistor and a second capacitor, a control electrode of the sixth transistor is connected to the pull-up node, a first electrode of the sixth transistor is connected to the clock signal terminal, and a second electrode of the sixth transistor is connected to the output terminal; and the first pole of the second capacitor is connected with the pull-up node, and the second pole of the second capacitor is connected with the signal output end.
In some embodiments, the reset module includes a fourth transistor and a fifth transistor, a control electrode of the fourth transistor is connected to the reset signal terminal, a first electrode of the fourth transistor is connected to the second power terminal, and a second electrode of the fourth transistor is connected to the pull-up node; a control electrode of the fifth transistor is connected to the reset signal terminal, a first electrode of the fifth transistor is connected to the second power terminal, and a second electrode of the fifth transistor is connected to the first electrode of the first capacitor.
In some embodiments, the output module further includes a seventh transistor, a control electrode of the seventh transistor is connected to the pull-up node, a first electrode of the seventh transistor is connected to the clock signal terminal, and a second electrode of the seventh transistor is connected to an auxiliary output terminal.
In some embodiments, the pull-down module includes an eighth transistor and a ninth transistor, a control electrode of the eighth transistor is connected to the pull-down node, a first electrode of the eighth transistor is connected to the third power source terminal, a second electrode of the eighth transistor is connected to the signal output terminal, a control electrode of the ninth transistor is connected to the pull-down node, a first electrode of the ninth transistor is connected to the second power source terminal, and a second electrode of the ninth transistor is connected to the pull-up node.
In some embodiments, the pull-down control module includes a tenth transistor, an eleventh transistor, a twelfth transistor, and a thirteenth transistor; a control electrode of the tenth transistor is connected to the pull-up node, a first electrode of the tenth transistor is connected to the second power supply terminal, and a second electrode of the tenth transistor is connected to the pull-down control node; a control electrode of the eleventh transistor is connected with the pull-up node, a first electrode of the eleventh transistor is connected with the second power supply end, and a second electrode of the eleventh transistor is connected with the pull-down node; a control electrode and a first electrode of the twelfth transistor are both connected with the first power supply end, and a second electrode of the twelfth transistor is connected with the pull-down control node; a control electrode of the thirteenth transistor is connected to the pull-down control node, a first electrode of the thirteenth transistor is connected to the pull-down node, and a second electrode of the thirteenth transistor is connected to the first power supply terminal.
In a second aspect, a gate driving circuit is provided, which includes cascaded shift register units, where the shift register unit is the shift register unit of the first aspect.
In a third aspect, a display substrate is provided, which includes the gate driving circuit of the second aspect.
In a fourth aspect, a display device is provided, comprising the display substrate of the third aspect.
Drawings
Fig. 1 is a block diagram of a shift register unit provided in an embodiment of the present disclosure.
Fig. 2 is a circuit diagram of a shift register unit according to an embodiment of the present disclosure.
Fig. 3 is a schematic diagram of a cascade relationship of a gate driving circuit according to an embodiment of the disclosure.
Fig. 4 is a timing diagram of the operation of the shift register unit according to the embodiment of the disclosure.
Detailed Description
For a better understanding of the technical aspects of the present disclosure, reference is made to the following detailed description taken in conjunction with the accompanying drawings.
In the following embodiments, each transistor is an N-type transistor, and the effective voltage applied to the control electrode is a high level voltage. Of course, the transistor in the embodiment of the present disclosure is not limited to the N-type transistor.
Referring to fig. 1, an embodiment of the present disclosure provides a shift register unit including an input module 1, an output module 2, a reset module 4, a pull-down control module 3, and a pull-down module 5.
The input module 1 is connected to the first signal input terminal P1, the second signal input terminal P2 and the pull-up node PU, and is configured to superimpose the effective voltages sequentially provided by the first signal input terminal P1 and the second signal input terminal P2 respectively and output the superimposed effective voltages to the pull-up node PU.
The output module 2 is connected with the pull-up node PU, the clock signal terminal CLK and the signal output terminal OUT, and is configured to transmit a signal of the clock signal terminal CLK to the signal output terminal OUT in response to control of the pull-up node PU;
the pull-down control module 3 is connected with the pull-down node PU, the first power supply terminal VDD and the pull-down node PD, and is configured to respond to the control of the pull-up node PU to transmit the signal of the first power supply terminal VDD to the pull-down node PD respectively;
the reset module 4 is connected to the reset signal terminal RST, the second power terminal LVGL and the pull-up node PU, and configured to transmit a voltage signal provided by the second power terminal LVGL to the pull-up node PU in response to control of the reset signal terminal RST;
the pull-down module 5 is connected to the pull-down node PD, the second power source terminal LVGL, the third power source terminal VGL, the signal output terminal OUT, and the pull-up node PU, and is configured to transmit the voltage provided by the third power source terminal VGL to the signal output terminal OUT and transmit the voltage provided by the second power source terminal LVGL to the pull-up node PU under the control of the pull-down node PD.
The input module 1 of a typical shift register unit has only one signal input terminal, and when a gate driving circuit is formed, a pull-up node PU of the shift register unit of the previous stage is boosted by the shift register unit of the previous stage. The embodiment of the present disclosure improves this, that is, the voltage is boosted for the pull-up node PU of the shift register unit of the current stage by the shift register units of the first two stages. So, the promotion of the voltage of pull-up node PU is more abundant to can make the voltage driving ability of output module 2 output stronger.
In some embodiments, the input module 1 includes a first transistor M1, a second transistor M2, a third transistor M3, and a first capacitor C1; a control electrode and a first electrode of the first transistor M1 are both connected to the first signal input end P1, and a second electrode of the first transistor M1 is connected to the pre-charging node Q; the control electrode and the first electrode of the second transistor M2 are both connected with the pre-charging node Q, and the second electrode of the second transistor M2 is connected with the upper pull-up node PU; a control electrode of the third transistor M3 is connected to the pre-charge node Q, a first electrode of the third transistor M3 is connected to the second signal input terminal P2, and a second electrode of the third transistor M3 is connected to the first electrode of the first capacitor C1; the second pole of the first capacitor C1 is connected to the pre-charge node Q.
Referring to fig. 3, in an actual gate driving circuit, the cascade output OC1 of the first stage shift register unit GOA1 is connected to the first signal input terminal P1 of the third stage shift register unit GOA 3; the cascade output OC2 of the second stage shift register unit GOA2 is connected to the second signal input P2 of the third stage shift register unit GOA 3.
The manner of implementing cascade connection among the shift register units is not limited to this, for example, in some embodiments, the output terminal OUTOUT1 of the first stage shift register unit GOA1 may be connected to the first signal input terminal P1 of the third stage shift register unit GOA 3; the output terminal OUTOUT2 of the second stage shift register unit GOA2 is connected to the second signal input terminal P2 of the third stage shift register unit GOA 3.
The disclosure is not limited as to how the shift register units are cascaded. The skilled person can arrange according to the prior art.
In some embodiments, referring to fig. 2, the output module 2 includes a sixth transistor M6, a second capacitor C2, a control electrode of the sixth transistor M6 is connected to the pull-up node PU, a first electrode of the sixth transistor M6 is connected to the clock signal terminal CLK, and a second electrode of the sixth transistor M6 is connected to the output terminal OUT; a first pole of the second capacitor C2 is connected to the pull-up node PU, and a second pole of the second capacitor C2 is connected to the signal output terminal OUT.
The output block 27 of the shift register cell shown in fig. 2 further comprises a seventh transistor M7 having a control electrode connected to the pull-up node PU, a first electrode connected to the clock signal terminal CLK, and a second electrode connected to the cascade output. For those cases where the cascade connection is implemented by the output terminal OUTOUT, only the sixth transistor M6 and the second capacitor C2 need to be provided.
The embodiment of the present disclosure is not limited to the specific connection manner of the output module 2, and those skilled in the art can set the connection manner according to the prior art.
In some embodiments, the reset module 4 includes a fourth transistor M4 and a fifth transistor M5, a control electrode of the fourth transistor M4 is connected to the reset signal terminal RST, a first electrode of the fourth transistor M4 is connected to the second power terminal LVGL, and a second electrode of the fourth transistor M4 is connected to the pull-up node PU; a control electrode of the fifth transistor M5 is connected to the reset signal terminal RST, a first electrode of the fifth transistor M5 is connected to the second power source terminal LVGL, and a second electrode of the fifth transistor M5 is connected to the first electrode of the first capacitor C1.
As such, the fourth transistor M4 may reset the pull-up node PU under the control of the reset signal terminal RST. The fifth transistor M5 may be a first electrode (a lower electrode of the first capacitor C1 in fig. 2) of the first capacitor C1 at the control line of the reset signal terminal RST. The fifth transistor M5 may be used to reset the first pole of the first capacitor C1, thus improving the uniformity of the circuit.
Of course, the circuit shown in fig. 2 can be normally operated even if the fifth transistor M5 is omitted.
In some embodiments, the pull-down module 5 includes an eighth transistor M8 and a ninth transistor M9, a control electrode of the eighth transistor M8 is connected to the pull-down node PD, a first electrode of the eighth transistor M8 is connected to the third power source terminal VGLVGL, a second electrode signal output terminal OUT of the eighth transistor M8, a control electrode of the ninth transistor M9 is connected to the pull-down node PD, a first electrode of the ninth transistor M9 is connected to the second power source terminal LVGL, and a second electrode of the ninth transistor M9 is connected to the pull-down node PU.
In this manner, at the control line of the pull-down node PD, the eighth transistor M8 may reset the voltage of the output terminal OUT, and the ninth transistor M9 may reset the voltage of the pull-up node PU.
Of course, if the cascade output OC is used for cascade connection between the shift register units, the pull-down module 5 should further include a fourteenth transistor M14, and the fourteenth transistor M14 is used for resetting the cascade output OC at the control line of the pull-down node PD.
In some embodiments, referring to fig. 2, the pull-down control module 3 includes a tenth transistor M10, an eleventh transistor M11, a twelfth transistor M12, and a thirteenth transistor M13; a control electrode of the tenth transistor M10 is connected to the pull-up node PU, a first electrode of the tenth transistor M10 is connected to the second power source terminal LVGL, and a second electrode of the tenth transistor M10 is connected to the pull-down control node; a control electrode of the eleventh transistor M11 is connected to the pull-up node PU, a first electrode of the eleventh transistor M11 is connected to the second power source terminal LVGL, and a second electrode of the eleventh transistor M11 is connected to the pull-down node PD; a control electrode and a first electrode of the twelfth transistor M12 are both connected to the first power terminal VDD, and a second electrode of the twelfth transistor M12 is connected to the pull-down control node; a control electrode of the thirteenth transistor M13 is connected to the pull-down control node, and a second electrode of the thirteenth transistor M13 is connected to the first power source terminal VDD.
In this manner, if the voltage of the pull-up node PU becomes a low level, the tenth transistor M10 and the eleventh transistor M11 are turned off, the pull-down control node PDCN becomes a high level, the thirteenth transistor M13 is turned on, and the pull-down node PD becomes a high level.
Referring to fig. 3, an embodiment of the present disclosure further provides a gate driving circuit, which includes cascaded shift register units, where the shift register unit is the shift register unit described above.
The cascade output of the first two stages of shift register units provides input signals for the shift register unit of the current stage, so that the pull-up node PU is charged twice, rather than the pull-up node PU of the shift register unit of the current stage which is charged once as in the prior art.
Of course, the cascade connection between the shift register units can also be realized by the output terminal OUT. The key point of the embodiment of the disclosure is to improve the charging capability of the pull-up node PU, and the design of each module in addition can refer to the prior art.
Specifically, as the shift register unit shown in fig. 2 is used, the initial two-stage shift register units GOA1 and GOA2 are reset by the auxiliary reset signal terminal P3. From the third stage GOA3, the auxiliary reset signal terminal P3 is set to inactive state.
With reference to fig. 2-4, the signals at the first and second inputs of the initial shift register units GOA1 and GOA2 are provided by initial signal inputs STV0 and STV1, and the signals at the first and second inputs of the second stage shift register unit are provided by inputs STV1 and the cascade output OC1 of the first stage shift register unit GOA 1. Starting from the shift register cell GOA3 of the third stage, the signal at its first input is provided by the cascade output of the shift register cells of the previous two stages, and the signal at its second input is provided by the cascade output of the shift register cell of the previous stage.
Focusing on the third stage shift register unit GOA3, in stage PA, under the control of the cascade output OC1, the first transistor M1 is turned on, and the pre-charged node Q of the third stage shift register unit GOA3 is charged for the first time and the potential is raised. And the third transistor M3 is turned on, at which time the cascade output OC2 provides a low level, so that the lower electrode (in terms of current view) of the first capacitor C1 is written with a low level voltage. The second transistor M2 is turned on and the pull-up node PU is charged for the first time.
In phase PB, the first transistor M1 is turned off, and the third transistor M3 and the second transistor M2 are kept on. Under the control of the cascade output OC2, the voltage at the lower electrode of the first capacitor C1 is raised, and the voltage at the pre-charge node Q is raised a second time since the pre-charge node Q is floating at this time, i.e., the upper electrode (according to the current view of fig. 1) of the first capacitor C1 is floating. At this time, the second transistor M2 is turned on, that is, the voltage of the pull-up node PU is raised for the second time.
Therefore, the input module 1 can charge the pull-up node PU twice, and the potential of the pull-up node PU is further increased.
At the stage PC, the signal at the clock signal terminal CLK changes from low to high, and since the pull-up node PU is floating, that is, one electrode of the second capacitor C2 is floating, the rising of the right electrode potential of the second capacitor C2 in fig. 2 may cause the further rising of the left electrode potential of the second capacitor C2, that is, the potential of the pull-up node PU is raised for the third time, so as to ensure that the sixth transistor M6 is fully turned on, and improve the driving capability of the gate driving circuit.
The above description focuses on how the potential of the pull-up node PU is effectively raised, so as to ensure that the sixth transistor M6 is fully turned on. For other operations of the gate driving circuit, reference may be made to the prior art, and embodiments of the present disclosure do not specifically limit this part.
The embodiment of the present disclosure further provides a display substrate including the gate driving circuit.
An embodiment of the present disclosure further provides a display device including the display substrate.
The display device is any product or device having a display function, such as a liquid crystal display panel, a mobile phone, a display, and a television.
It is to be understood that the above embodiments are merely exemplary embodiments that are employed to illustrate the principles of the present disclosure, and that the present disclosure is not limited thereto. It will be apparent to those skilled in the art that various changes and modifications can be made therein without departing from the spirit and scope of the disclosure, and these are to be considered as the scope of the disclosure.
Claims (10)
1. A shift register unit is characterized by comprising an input module, an output module, a reset module, a pull-down control module and a pull-down module;
the input module is connected with a first signal input end, a second signal input end and a pull-up node, and is configured to output effective voltages successively provided by the first signal input end and the second signal input end to the pull-up node after overlapping;
the output module is connected with the pull-up node, the clock signal end and the signal output end and is configured to respond to the control of the pull-up node to transmit a signal of the clock signal end to the signal output end;
the pull-down control module is connected with the pull-up node, a first power end and a pull-down node and is configured to respond to the control of the pull-up node to transmit a signal of the first power end to the pull-down node respectively;
the reset module is connected with a reset signal terminal, a second power terminal and the pull-up node and is configured to respond to the control of the reset signal terminal to transmit a voltage signal provided by the second power terminal to the pull-up node;
the pull-down module is connected with the pull-down node, the second power end, the third power end, the signal output end and the pull-up node, and is configured to transmit the voltage provided by the third power end to the signal output end and transmit the voltage provided by the second power end to the pull-up node under the control of the pull-down node.
2. The shift register cell of claim 1, wherein the input module comprises a first transistor, a second transistor, a third transistor, and a first capacitor; a control electrode and a first electrode of the first transistor are both connected with the first signal input end, and a second electrode of the first transistor is connected with a pre-charging node; a control electrode and a first electrode of the second transistor are both connected with the pre-charging node, and a second electrode of the second transistor is connected with the pull-up node; a control electrode of the third transistor is connected with the pre-charging node, a first electrode of the third transistor is connected with the second signal input end, and a second electrode of the third transistor is connected with a first electrode of the first capacitor; the second pole of the first capacitor is connected with the pre-charging node.
3. The shift register unit according to claim 2, wherein the output module comprises a sixth transistor and a second capacitor, a control electrode of the sixth transistor is connected to the pull-up node, a first electrode of the sixth transistor is connected to the clock signal terminal, and a second electrode of the sixth transistor is connected to the output terminal; and the first pole of the second capacitor is connected with the pull-up node, and the second pole of the second capacitor is connected with the signal output end.
4. The shift register unit according to claim 3, wherein the reset module comprises a fourth transistor and a fifth transistor, a control electrode of the fourth transistor is connected to the reset signal terminal, a first electrode of the fourth transistor is connected to the second power source terminal, and a second electrode of the fourth transistor is connected to the pull-up node; a control electrode of the fifth transistor is connected to the reset signal terminal, a first electrode of the fifth transistor is connected to the second power terminal, and a second electrode of the fifth transistor is connected to the first electrode of the first capacitor.
5. The shift register unit according to claim 3, wherein the output module further comprises a seventh transistor, a control electrode of the seventh transistor is connected to the pull-up node, a first electrode of the seventh transistor is connected to the clock signal terminal, and a second electrode of the seventh transistor is connected to an auxiliary output terminal.
6. The shift register unit according to any one of claims 1 to 5, wherein the pull-down module comprises an eighth transistor and a ninth transistor, a control electrode of the eighth transistor is connected to the pull-down node, a first electrode of the eighth transistor is connected to the third power source terminal, a second electrode of the eighth transistor is connected to the signal output terminal, a control electrode of the ninth transistor is connected to the pull-down node, a first electrode of the ninth transistor is connected to the second power source terminal, and a second electrode of the ninth transistor is connected to the pull-up node.
7. The shift register unit according to any one of claims 1 to 5, wherein the pull-down control module includes a tenth transistor, an eleventh transistor, a twelfth transistor, and a thirteenth transistor; a control electrode of the tenth transistor is connected to the pull-up node, a first electrode of the tenth transistor is connected to the second power supply terminal, and a second electrode of the tenth transistor is connected to the pull-down control node; a control electrode of the eleventh transistor is connected with the pull-up node, a first electrode of the eleventh transistor is connected with the second power supply end, and a second electrode of the eleventh transistor is connected with the pull-down node; a control electrode and a first electrode of the twelfth transistor are both connected with the first power supply end, and a second electrode of the twelfth transistor is connected with the pull-down control node; a control electrode of the thirteenth transistor is connected to the pull-down control node, a first electrode of the thirteenth transistor is connected to the pull-down node, and a second electrode of the thirteenth transistor is connected to the first power supply terminal.
8. A gate drive circuit comprising cascaded shift register cells, wherein the shift register cells are according to claim 1.
9. A display substrate comprising the gate driver circuit according to claim 8.
10. A display device comprising the display substrate according to claim 9.
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| CN112382239A (en) * | 2020-11-05 | 2021-02-19 | 深圳市华星光电半导体显示技术有限公司 | GOA circuit and display panel |
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| CN111210786B (en) | 2021-12-24 |
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