CN111613170A - Shift register unit and driving method thereof, gate drive circuit and display device - Google Patents
Shift register unit and driving method thereof, gate drive circuit and display device Download PDFInfo
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- CN111613170A CN111613170A CN202010576444.5A CN202010576444A CN111613170A CN 111613170 A CN111613170 A CN 111613170A CN 202010576444 A CN202010576444 A CN 202010576444A CN 111613170 A CN111613170 A CN 111613170A
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0264—Details of driving circuits
- G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
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Abstract
The invention provides a shift register unit, a driving method thereof, a grid driving circuit and a display device. A shift register unit comprising: the control circuit comprises an input sub-circuit, a pull-up sub-circuit, a pull-down sub-circuit, a first control sub-circuit, a second control sub-circuit and a third control sub-circuit; the first control sub-circuit is configured to respond to the control of the second clock signal terminal, and transmit a signal to the forward direction scanning control terminal to the pull-down control node; and responding to the control of the third clock signal terminal, and transmitting the signal of the reverse scanning control terminal to the pull-down control node; the second control sub-circuit is configured to turn on the first power supply terminal with the pull-down node in response to control of a potential of the pull-down control node, and to turn on the second power supply terminal with the pull-down node in response to control of a potential of the pull-up control node; the third control sub-circuit is configured to conduct the first power supply terminal with the pull-up control node and conduct the pull-down node with the second power supply terminal in response to control of a potential of the pull-up node.
Description
Technical Field
The invention relates to the technical field of display, in particular to a shift register unit, a driving method thereof, a grid driving circuit and a display device.
Background
The Gate Driver On Array (GOA) is a technology for integrating a Gate Driver circuit On an Array substrate, where the Gate Driver circuit includes a plurality of shift register units, and each shift register unit corresponds to a row of Gate lines. In the charging stage of the operation of the current shift register unit, a pull-up node and a pull-down node can be charged simultaneously, so that when the potential of the pull-up node is increased, the pull-down node is pulled down by a pull-down transistor controlled by the pull-down node, and the driving capability of the shift register unit is reduced.
Disclosure of Invention
The present invention is directed to at least one of the technical problems in the prior art, and provides a shift register unit, a driving method thereof, a gate driving circuit and a display device.
In order to achieve the above object, the present invention provides a shift register unit, including: the control circuit comprises an input sub-circuit, a pull-up sub-circuit, a pull-down sub-circuit, a first control sub-circuit, a second control sub-circuit and a third control sub-circuit; the input sub-circuit, the third control sub-circuit and the pull-up sub-circuit are connected to a pull-up node, and the second control sub-circuit, the third control sub-circuit and the pull-down sub-circuit are connected to a pull-down node; the second control sub-circuit, the third control sub-circuit, and the pull-down sub-circuit are connected to a pull-up control node; the first control sub-circuit and the second control sub-circuit are connected to a pull-down control node;
the input sub-circuit is configured to transmit a signal of a forward scan control terminal to the pull-up node in response to control of a signal of a first input terminal, and to transmit a signal of a reverse scan control terminal to the pull-up node in response to control of a signal of a second input terminal;
the pull-up sub-circuit is configured to respond to the control of the electric potential of the pull-up node and conduct a first clock signal end and the output end of the shift register unit;
the first control sub-circuit is configured to respond to the control of a second clock signal terminal, and transmit a signal to the forward direction scanning control terminal to the pull-down control node; and responding to the control of a third clock signal terminal, and transmitting the signal of the reverse scanning control terminal to the pull-down control node;
the second control sub-circuit is configured to turn on a first power supply terminal with the pull-down node in response to control of the pull-down control node potential, and turn on a second power supply terminal with the pull-down node in response to control of the pull-up control node potential;
the third control sub-circuit is configured to turn on the first power supply terminal with the pull-up control node and turn on the pull-down node with the second power supply terminal in response to control of the pull-up node potential;
the pull-down sub-circuit is configured to respond to control of the pull-down node potential, pull-down the potential of the pull-up control node and the potential of the output end of the shift register unit, and conduct the pull-up node and the pull-up control node.
In some embodiments, the input sub-circuit comprises: a first input transistor and a second input transistor,
the grid electrode of the first input transistor is connected with the first input end, the first pole of the first input transistor is connected with the forward scanning control end, and the second pole of the first input transistor is connected with the pull-up node;
the grid electrode of the second input transistor is connected with the second input end, the first pole of the second input transistor is connected with the pull-up node, and the second pole of the second input transistor is connected with the reverse scanning control end.
In some embodiments, the pull-up sub-circuit comprises: a pull-up transistor and a first capacitor,
the grid electrode of the pull-up transistor is connected with the pull-up node, the first pole of the pull-up transistor is connected with the first clock signal end, and the second pole of the pull-up transistor is connected with the output end of the shift register unit;
and two ends of the first capacitor are respectively connected with the pull-up node and the output end of the shift register unit.
In some embodiments, the first control sub-circuit comprises: a first control transistor and a second control transistor,
the grid electrode of the first control transistor is connected with the second clock signal end, the first pole of the first control transistor is connected with the forward scanning control end, and the second pole of the first control transistor is connected with the pull-down control node;
the grid electrode of the second control transistor is connected with the third clock signal end, the first pole of the second control transistor is connected with the pull-down control node, and the second pole of the second control transistor is connected with the reverse scanning control end.
In some embodiments, the second control sub-circuit comprises: a third control transistor and a fourth control transistor,
the grid electrode of the third control transistor is connected with the pull-up control node, the first pole of the third control transistor is connected with the pull-down node, and the second pole of the third control transistor is connected with the second power supply end;
the grid electrode of the fourth control transistor is connected with the pull-down control node, the first pole of the fourth control transistor is connected with the first power supply end, and the second pole of the fourth control transistor is connected with the pull-down node.
In some embodiments, the third control sub-circuit comprises: a fifth control transistor and a sixth control transistor,
a gate of the fifth control transistor is connected to the pull-up node, a first pole of the fifth control transistor is connected to the pull-down node, and a second pole of the fifth control transistor is connected to the second power supply terminal;
the grid electrode of the sixth control transistor is connected with the pull-up node, the first pole of the sixth control transistor is connected with the first power supply end, and the second pole of the sixth control transistor is connected with the pull-up control node.
In some embodiments, the pull-down subcircuit includes: a first pull-down transistor, a second pull-down transistor, and a third pull-down transistor,
the grid electrode of the first pull-down transistor is connected with the pull-down node, the first pole of the first pull-down transistor is connected with the output end of the shift register unit, and the second pole of the first pull-down transistor is connected with the second power supply end;
the grid electrode of the second pull-down transistor is connected with the pull-down node, the first pole of the second pull-down transistor is connected with the pull-up control node, and the second pole of the second pull-down transistor is connected with the second power supply end;
the grid electrode of the third pull-down transistor is connected with the pull-down node, the first pole of the third pull-down transistor is connected with the pull-up node, and the second pole of the third pull-down transistor is connected with the pull-up control node.
In some embodiments, the shift register unit further includes:
a fourth control sub-circuit configured to pull down the potential of the pull-down node in response to control of a signal at an output terminal of the shift register unit.
In some embodiments, the fourth control sub-circuit comprises: a seventh control transistor, a gate of which is connected to the output terminal of the shift register unit, a first pole of which is connected to the pull-up node, and a second pole of which is connected to the second power source terminal.
In some embodiments, the shift register unit further includes: and two ends of the second capacitor are respectively connected with the pull-down node and the second power supply end.
The embodiment of the invention also provides a driving method of the shift register unit, which comprises the following steps:
in a charging phase of a forward scanning mode, providing effective level signals to the first input end and the second clock signal end, so that the input sub-circuit transmits a signal of a forward scanning control end to the pull-up node, the first control sub-circuit transmits the effective level signal of the forward scanning control end to the pull-down control node, the second control sub-circuit conducts the first power end and the pull-down node, the third control sub-circuit conducts the pull-down node and the second power end, and the pull-up node and the pull-up control node, and the pull-up control node and the second power end are disconnected;
in a pull-down control stage of a forward scanning mode, providing an invalid level signal to the second clock signal terminal, and providing an effective level signal to the third clock signal terminal, so that the invalid level signal of the reverse scanning control terminal is transmitted to the pull-down control node, and the second control sub-circuit conducts the pull-down node and the second power supply terminal;
in the output stage of the forward scanning mode, providing an effective level signal to the first clock signal end so that the pull-up sub-circuit transmits the signal of the first clock signal end to the output end;
in a reset phase of a forward scanning mode, providing an active level signal to the second input terminal and the second clock signal terminal, so that the input sub-circuit transmits an inactive level signal of the reverse scanning control terminal to the pull-up node, the first control sub-circuit transmits an active level signal of the second clock signal terminal to the pull-down control node, the second control sub-circuit transmits a voltage of the first power terminal to the pull-down node, and the pull-down sub-circuit pulls down a potential of the output terminal;
in a charging phase of a reverse scan mode, providing an effective level signal to the second input terminal and the third clock signal terminal, so that the input sub-circuit transmits a signal of a reverse scan control terminal to the pull-up node, the first control sub-circuit transmits an effective level signal of the reverse scan control terminal to the pull-down control node, the second control sub-circuit switches on the first power terminal and the pull-down node, the third control sub-circuit switches on the pull-down node and the second power terminal, and the pull-up node and the pull-up control node, and the pull-up control node and the second power terminal are both disconnected;
in a pull-down control stage of the reverse scan mode, providing an invalid level signal to the third clock signal terminal, and providing an effective level signal to the second clock signal terminal, so that the invalid level signal of the forward scan control terminal is transmitted to the pull-down control node, and the second control sub-circuit conducts the pull-down node and the second power supply terminal;
in an output stage of the reverse scanning mode, providing an effective level signal to the first clock signal end so that the pull-up sub-circuit transmits a signal of the first clock signal end to an output end;
in a reset stage of the reverse scan mode, an active level signal is provided to the first input terminal and the third clock signal terminal, so that the input sub-circuit transmits an inactive level signal of the forward scan control terminal to the pull-up node, the first control sub-circuit transmits an active level signal of the third clock signal terminal to the pull-down control node, the second control sub-circuit transmits the voltage of the first power terminal to the pull-down node, and the pull-down sub-circuit pulls down the potential of the output terminal.
The embodiment of the invention also provides a gate driving circuit, which comprises the shift register unit.
The embodiment of the invention also provides a display device which comprises the grid drive circuit.
Drawings
The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the principles of the invention and not to limit the invention. In the drawings:
fig. 1 is a schematic diagram of a shift register unit in the related art.
FIG. 2 is a timing diagram illustrating the operation of the shift register unit shown in FIG. 1.
Fig. 3 is a block diagram of a shift register unit according to an embodiment of the present invention.
Fig. 4 is a specific circuit diagram of a shift register unit according to an embodiment of the present invention.
FIG. 5 is a timing diagram illustrating the operation of the shift register unit in the forward scan mode according to an embodiment of the present invention.
FIG. 6 is a timing diagram illustrating the operation of the shift register unit in the reverse scan mode according to an embodiment of the present invention.
Fig. 7 is a flowchart of a driving method of a shift register unit in a forward scan mode according to an embodiment of the present invention.
Fig. 8 is a flowchart of a driving method of a shift register unit in a reverse scan mode according to an embodiment of the present invention.
Fig. 9 is a schematic diagram of a gate driving circuit according to an embodiment of the invention.
Detailed Description
The following detailed description of embodiments of the invention refers to the accompanying drawings. It should be understood that the detailed description and specific examples, while indicating the present invention, are given by way of illustration and explanation only, not limitation.
Fig. 1 is a schematic structural diagram of a shift register unit in the related art, and fig. 2 is a timing diagram of operations of the shift register unit shown in fig. 1, as shown in fig. 1 and fig. 2, the shift register unit includes: two capacitors C1 and C2, and transistors T1 to T8. Taking the forward scanning mode as an example, IN the charging stage, the first input terminal IN _1 and the second clock signal terminal CKB provide a high level signal, the first clock signal terminal CK provides a low level signal, and at this time, the high level signal of the forward scanning control terminal CN is transmitted to the pull-up node PU, so as to charge the pull-up node PU; meanwhile, the transistor T7 is turned on, so that the second clock signal terminal CKB charges the pull-down node PD, and the transistors T5 and T6 are turned on simultaneously, and the turn-on of the transistor T5 pulls down the potential of the pull-up node PU. In some technologies, the potential of the pull-up node PU can be raised by adjusting the channel sizes of the transistors T5 and T6, but the potential of the pull-down node PD cannot be completely pulled down, so that the potential of the pull-up node PU cannot be raised well, and thus, in the output stage, the potential of the pull-up node PU can only rise to 19.64V under the bootstrap action of the capacitor C1, and the output voltage of the output terminal OUT is smaller than the ideal output voltage, so that the driving capability of the shift register unit is reduced.
In order to solve the above problems, embodiments of the present invention provide a shift register unit and a driving method thereof, a gate driving circuit and a display device, and the shift register unit and the driving method thereof, the gate driving circuit and the display device in the embodiments of the present invention are described below with reference to the accompanying drawings.
Note that, the transistors according to the embodiments of the present invention may be independently selected from one of a polycrystalline silicon thin film transistor, an amorphous silicon thin film transistor, an oxide thin film transistor, and an organic thin film transistor. The "control electrode" referred to in the present invention specifically refers to a gate electrode of a transistor, the "first electrode" specifically refers to a source electrode of the transistor, and the corresponding "second electrode" specifically refers to a drain electrode of the transistor. Of course, those skilled in the art will appreciate that the "first pole" and "second pole" are interchangeable.
In addition, the transistors can be divided into N-type transistors and P-type transistors, and each transistor in the invention can be respectively and independently selected from the N-type transistors or the P-type transistors; in the following embodiments, each transistor in the display driving circuit is an N-type transistor, and the transistors in the display driving circuit can be simultaneously manufactured by the same manufacturing process. Accordingly, the active level signal is a high level signal and the inactive level signal is a low level signal.
Fig. 3 is a schematic block diagram of a shift register unit according to an embodiment of the present invention, and as shown in fig. 3, the shift register unit includes: an input sub-circuit 10, a pull-up sub-circuit 20, a pull-down sub-circuit 30, a first control sub-circuit 40, a second control sub-circuit 50 and a third control sub-circuit 60. The input sub-circuit 10, the third control sub-circuit 60 and the pull-up sub-circuit 20 are connected to the pull-up node PU, and the second control sub-circuit 50, the third control sub-circuit 60 and the pull-down sub-circuit 30 are connected to the pull-down node PD; the second control sub-circuit 50, the third control sub-circuit 60 and the pull-down sub-circuit 30 are connected to the pull-up control node PU _ CN; the first control sub-circuit 40 and the second control sub-circuit 50 are connected to the pull-down control node PD _ CN.
The input sub-circuit 10 is connected to the pull-up node PU, the first input terminal IN _1, the second input terminal IN _2, the forward scan control terminal CN, and the reverse scan control terminal CNB, and the input sub-circuit 10 is configured to transmit a signal of the forward scan control terminal CN to the pull-up node PU IN response to control of a signal of the first input terminal IN _1 and to transmit a signal of the reverse scan control terminal CNB to the pull-up node PU IN response to control of a signal of the second input terminal IN _ 2.
The pull-up sub-circuit 20 connects the pull-up node PU, the first clock signal terminal CLK1 and the output terminal OUT of the shift register unit, and the pull-up sub-circuit 20 is configured to turn on the first clock signal terminal CLK1 and the output terminal OUT of the shift register unit in response to the control of the potential of the pull-up node PU;
the first control sub-circuit 40 is connected to the forward direction scan control terminal CN, the reverse direction scan control terminal CNB, the second clock signal terminal CLK2, and the third clock signal terminal CLK3, and the first control sub-circuit 40 is configured to transmit a signal to the forward direction scan control terminal CN to the pull-down control node PD _ CN in response to the control of the second clock signal terminal CLK 2; and transmits a signal of the reverse scan control terminal CNB to the pull-down control node PD _ CN in response to the control of the third clock signal terminal CLK 3.
The second control sub-circuit 50 is connected to the pull-down control node PD _ CN, the pull-down node PU, the pull-up control node PU _ CN, the first power terminal and the second power terminal, and the second control sub-circuit 50 is configured to turn on the first power terminal VGH with the pull-down node PD in response to control of a potential of the pull-down control node PD _ CN and turn on the second power terminal VGL with the pull-down node PD in response to control of a potential of the pull-up control node PU _ CN.
The third control sub-circuit 60 is connected to the pull-up node PU, the pull-up control node PU _ CN, the pull-down node PD, the first power supply terminal VGH, and the second power supply terminal VGL, and is configured to switch on the first power supply terminal and the pull-up control node, and switch on the pull-down node and the second power supply terminal VGL in response to the control of the potential of the pull-up node.
The pull-down sub-circuit 30 is connected to the pull-down node PD, the pull-up node PU, the pull-up control node PU _ CN, the second power supply terminal VGL, and the output terminal OUT of the shift registering unit, and the pull-down sub-circuit 30 is configured to pull down the potential of the pull-up control node PU _ CN and the potential of the output terminal OUT of the shift registering unit in response to the control of the potential of the pull-down node PD, and to connect the pull-up node PU with the pull-up control node PU _ CN.
The first power terminal VGH may be a high-level voltage terminal, and the second power terminal VGL may be a low-level voltage terminal.
IN the embodiment of the present invention, IN the input stage of the forward scan mode, the first input terminal IN _1 and the second clock signal terminal CLK2 load an active level signal, the input sub-circuit 10 transmits the active level signal of the forward scan control terminal CN to the pull-up node PU, the first control sub-circuit 50 transmits the active level signal of the forward scan control terminal CN to the pull-down control node PD _ CN, under the control of the pull-down control node PD _ CN, the second control sub-circuit 50 turns on the first power terminal VGH and the pull-down node PD, and the third control sub-circuit 60 turns on the pull-down node PD and the second power terminal VGL, so that the pull-down node PD is at the middle potential, and the transistor controlled by the pull-down node PD is IN the off state, which does not affect the potential of the pull-up node PU. Similarly, IN the input stage of the reverse scan mode, the second input terminal IN _1 and the third clock signal terminal CLK3 load the active level signal, which can also prevent the pull-down node PD from interfering with the potential of the pull-up node PU, so as to facilitate the pull-up node PU to be pulled up to a sufficiently high potential IN the output stage, and further facilitate improving the driving capability of the shift register unit.
In addition, the working process of the shift register unit can further comprise the following steps: in the pull-down control phase of the forward scan mode, the second clock signal terminal CLK2 loads an inactive level signal, the third clock signal terminal CLK3 loads an active level signal, at this time, the inactive level signal of the reverse scan control terminal CNB is transmitted to the pull-down control node PD _ CN, and the second control sub-circuit 50 turns on the pull-down node PD and the second power terminal VGL, so that the pull-down node PD is maintained at a low level potential, and the pull-up node PU is maintained at a high level potential. During the output phase of the forward direction scan mode, the first clock terminal CLK1 is loaded with an active level signal, and at this time, the pull-up sub-circuit 20 transmits the signal of the first clock terminal CLK1 to the output terminal OUT. IN the reset phase of the forward direction scan mode, the second input terminal IN _2 and the second clock signal terminal CLK2 are loaded with active level signals, at this time, the input sub-circuit 10 transmits an inactive level signal of the reverse direction scan control terminal CNB to the pull-up node PU, the first control sub-circuit 40 transmits an active level signal of the second clock signal terminal CLK2 to the pull-down control node PD _ CN, and the second control sub-circuit 50 transmits the voltage of the first power terminal VGH to the pull-down node PD, so that the pull-down sub-circuit 30 pulls down the potential of the output terminal OUT. In the pull-down control phase of the reverse scan mode, the third clock signal terminal CLK3 loads an inactive level signal, and the second clock signal terminal CLK2 loads an active level signal, at this time, the inactive level signal of the forward scan control terminal CN is transmitted to the pull-down control node PD _ CN, and the second control sub-circuit 50 connects the pull-down node PD and the second power terminal VGL, so that the pull-down node PD is maintained at a low level potential, and the pull-up node PU is maintained at a high level potential. During the output phase of the reverse scan mode, the first clock terminal CLK1 is loaded with an active level signal, and at this time, the pull-up sub-circuit 20 transmits the signal of the first clock terminal CLK1 to the output terminal OUT. IN the reset phase of the reverse scan mode, the second input terminal IN _2 and the third clock signal terminal CLK3 are loaded with active level signals, at this time, the input sub-circuit 10 transmits an inactive level signal of the forward scan control terminal CN to the pull-up node PU, the first control sub-circuit 40 transmits an active level signal of the third clock signal terminal CLK3 to the pull-down control node PD _ CN, and the second control sub-circuit 50 transmits the voltage of the first power terminal VGH to the pull-down node PD, so that the pull-down sub-circuit 30 pulls down the potential of the output terminal OUT.
In some embodiments, the shift register unit further includes: and the fourth control sub-circuit 70, the fourth control sub-circuit 70 being connected to the output terminal OUT of the shift register unit, the pull-down node PD and the second power supply terminal VGL, the fourth control sub-circuit 70 being configured to pull down the potential of the pull-down node PD in response to the control of the signal of the output terminal OUT of the shift register unit, so as to ensure that the pull-down node PD is in an invalid level state when the output terminal outputs a valid level signal, and prevent the potential of the output terminal OUT from being pulled down.
Fig. 4 is a schematic circuit diagram of a shift register unit according to an embodiment of the present invention, and the shift register unit shown in fig. 4 is an embodiment of the shift register unit shown in fig. 3.
As shown in fig. 4, the input sub-circuit 10 includes: a first input transistor T1 and a second input transistor T2. The gate of the first input transistor T1 is connected to the first input terminal IN _1, the first pole of the first input transistor T1 is connected to the forward scan control terminal CN, and the second pole of the first input transistor T1 is connected to the pull-up node PU. The gate of the second input transistor T2 is connected to the second input terminal IN _2, the first pole of the second input transistor T2 is connected to the pull-up node PU, and the second pole of the second input transistor T2 is connected to the reverse scan control terminal CNB.
The pull-up sub-circuit 20 includes: a pull-up transistor T3 and a first capacitor C1, wherein the gate of the pull-up transistor T3 is connected to the pull-up node, the first pole of the pull-up transistor T3 is connected to the first clock signal terminal CLK1, and the second pole of the pull-up transistor T3 is connected to the output terminal OUT of the shift register unit. Two ends of the first capacitor C1 are connected to the pull-up node PU and the output terminal OUT of the shift register unit, respectively.
The first control sub-circuit 40 includes: a first control transistor T10 and a second control transistor T9, wherein a gate of the first control transistor T10 is connected to the second clock signal terminal CLK2, a first pole of the first control transistor T10 is connected to the forward scan control terminal CN, and a second pole of the first control transistor T10 is connected to the pull-down control node PD _ CN. The gate of the second control transistor T9 is connected to the third clock signal terminal CLK3, the first pole of the second control transistor T9 is connected to the pull-down control node PD _ CN, and the second pole of the second control transistor T10 is connected to the reverse scan control terminal CNB.
The second control sub-circuit 50 comprises: a third control transistor T6 and a fourth control transistor T7, a gate of the third control transistor T6 is connected to the pull-up control node PU _ CN, a first pole of the third control transistor T6 is connected to the pull-down node PD, and a second pole of the third control transistor T6 is connected to the second power source terminal VGL; the gate of the fourth control transistor T7 is connected to the pull-down control node PD _ CN, the first pole of the fourth control transistor T7 is connected to the first power source terminal VGH, and the second pole of the fourth control transistor T7 is connected to the pull-down node PD.
The third control sub-circuit 60 comprises: a fifth control transistor T11 and a sixth control transistor T12, a gate of the fifth control transistor T11 is connected to the pull-up node PU, a first pole of the fifth control transistor T11 is connected to the pull-down node PD, and a second pole of the fifth control transistor T11 is connected to the second power source terminal VGL; a gate of the sixth control transistor T12 is connected to the pull-up node PU, a first electrode of the sixth control transistor T12 is connected to the first power source terminal VGH, and a second electrode of the sixth control transistor T12 is connected to the pull-up control node PU _ CN.
The pull-down sub-circuit 30 includes: a first pull-down transistor T4, a second pull-down transistor T5, and a third pull-down transistor T13. The gate of the first pull-down transistor T4 is connected to the pull-down node PD, the first pole of the first pull-down transistor T4 is connected to the output terminal OUT of the shift register unit, and the second pole of the first pull-down transistor T4 is connected to the second power source terminal VGL. The gate of the second pull-down transistor T5 is connected to the pull-down node, the first pole of the second pull-down transistor T5 is connected to the pull-up control node PU _ CN, and the second pole of the second pull-down transistor T5 is connected to the second power source terminal VGL. The gate of the third pull-down transistor T13 is connected to the pull-down node PD, the first pole of the third pull-down transistor T13 is connected to the pull-up node PU, and the second pole of the third pull-down transistor T13 is connected to the pull-up control node PU _ CN.
The fourth control sub-circuit 70 includes: a gate of the seventh control transistor T8, the seventh control transistor T8 is connected to the output terminal OUT of the shift register unit, a first pole of the seventh control transistor T8 is connected to the pull-up node PU, and a second pole of the seventh control transistor T8 is connected to the second power source terminal VGL.
In some embodiments, the shift register unit further includes a second capacitor C2, two ends of which are respectively connected to the pull-down node PD and the second power supply terminal VGL.
Fig. 5 is a timing diagram illustrating an operation of the shift register unit in the forward scan mode according to an embodiment of the present invention, and the operation of the shift register unit in the forward scan mode is described with reference to fig. 4 and 5. In the forward direction scanning mode, the working process of the shift register unit comprises the following steps: a charging phase t1, a pull-down control phase t2, an output phase t3 and a reset phase t 4. In the forward scanning mode, an active level signal is provided to the forward scanning control terminal CN, and an inactive level signal is provided to the reverse scanning control terminal CNB.
During the charging period t1, an active level signal is provided to the first input terminal IN _1 and the second clock signal terminal CLK2, and an inactive level signal is provided to the second input terminal IN _2, the first clock signal terminal CLK1 and the third clock signal terminal CLK 3.
At this time, the first input transistor T1 is turned on, the active level signal of the forward scan control terminal CN is transmitted to the pull-up node PU, and the potential of the pull-up node PU is pulled high; meanwhile, since the second clock signal terminal CLK2 is at the active level potential, the first control transistor T10 is turned on, and the potential of the pull-down control node PD _ CN is pulled high, so that the fourth control transistor T7 is turned on; in addition, since the potential of the pull-up node PU is pulled high, the fifth control transistor T11 and the sixth control transistor T12 are turned on, and the pull-down node PD is at an intermediate level by the fourth control transistor T7, the fifth control transistor T11, and the sixth control transistor T12. Since the second pole of the first pull-down transistor T4 and the second pole of the second pull-down transistor T5 are connected to the second power source terminal VGL, which has a low voltage, the voltage between the gate and the second pole of the first pull-down transistor T4 may be higher than the threshold voltage, the voltage between the gate and the second pole of the second pull-down transistor T5 is also higher than the threshold voltage thereof, and the first pull-down transistor T4 and the second pull-down transistor T5 are turned on, thereby bringing the pull-up control node PU _ CN to an intermediate level. For example, the voltage of the first power source terminal VGH is 8V, the voltage of the second power source terminal VGL is-8V, and the potential of the pull-down node PD reaches-4V, at which time the gate-source voltage Vgs of the second pull-down transistor T5 is Vg-Vs-4- (-8) 4V, thereby turning on the second pull-down transistor T5. Since the voltage difference between the gate and the second pole of the third pull-down transistor T13 is small (the gate potential of the third pull-down transistor T13 is-4V, the second pole potential Vs is 4V, and the gate-source voltage Vgs is-8V), the third pull-down transistor T13 is turned off. Since the third pull-down transistor T13 is turned off, the pull-up node PU can be guaranteed to rise well. Under the control of the high level potential of the pull-up node PU, the pull-up transistor T3 is turned on, and the inactive level signal of the first clock signal terminal CLK1 is output to the output terminal OUT.
During the pull-down control period t2, an active level signal is supplied to the third clock signal terminal CLK3, and inactive level signals are supplied to the first input terminal IN _1, the second input terminal IN _2, the first clock signal terminal CLK1, and the second clock signal terminal CLK 2.
At this time, since the second clock signal terminal CLK2 provides the inactive level signal, the first control transistor T10 is turned off; since the third clock signal terminal CLK3 provides an active level signal, the second control transistor T9 is turned on, and the pull-down control node PD _ CN receives an inactive level signal of the reverse scan control terminal CNB, thereby turning off the fourth control transistor T7. The pull-up node PU maintains the high level potential during the charging phase, and therefore, the fifth control transistor T11 and the sixth control transistor T12 are turned on, so that the pull-down node PD is pulled down to a low level by the fifth control transistor T11, and the pull-up node PU _ CN is pulled up to a high level by the sixth control transistor T12. Since the pull-down node PD is at the inactive-level potential, the second pull-down transistor T5 is turned off.
IN the output stage t3, an active level signal is supplied to the first clock signal terminal CLK1, and an inactive level signal is supplied to each of the first input terminal IN _1, the second input terminal IN _2, the second clock signal terminal CLK2, and the third clock signal terminal CLK 3.
At this time, the potential of the pull-up node PU is further raised by the bootstrap action of the first capacitor C1, the pull-up transistor T3 is turned on, and the active level signal of the first clock signal terminal CLK1 is transmitted to the output terminal OUT. Since the second and third clock signal terminals CLK2 and CLK3 both provide the inactive level signal, the second and first control transistors T9 and T10 are both turned off, and the pull-down control node PD _ CN maintains the inactive level potential of the previous stage, thereby turning off the fourth control transistor T7. Since the output terminal OUT outputs the active level signal, the seventh control transistor T8 is turned on, and the pull-down node PD is turned on with the second power source terminal VGL, thereby reaching the inactive level potential. Since the pull-down node PD reaches the inactive level potential, the second pull-down transistor T5 is turned off, and the sixth control transistor T12 is turned on under the control of the active level potential of the pull-up node PU, so that the pull-up control node PU _ CN receives the high level signal of the first power source terminal VGH, and further the third control transistor T6 is turned on, thereby ensuring that the potential of the pull-down node PD is pulled down.
During the reset period t4, an active level signal is provided to the second input terminal IN _2 and the second clock signal terminal CLK2, and an inactive level signal is provided to the first input terminal IN _1, the first clock signal terminal CLK1 and the third clock signal terminal CLK 3.
At this time, the second input transistor T2 is turned on, so that the pull-up node PU is turned on with the reverse scan control terminal CNB, the first capacitor C1 is discharged, and the potential of the pull-up node PU is pulled low. The first control transistor T10 is turned on under the control of the active level signal of the second clock signal terminal CLK2, and the pull-down control node PD _ CN receives the active level signal of the forward scan control terminal CN. The fourth control transistor T7 is turned on under the control of the active-level potential of the pull-down control node PD _ CN, thereby causing the pull-down node PD to be pulled up to the active-level potential. Under the control of the active level potential of the pull-down node PD, the second pull-down transistor T5 and the first pull-down transistor T4 are turned on, so that the potentials of the pull-up control node PU _ CN and the output terminal OUT are pulled down. Meanwhile, the third pull-down transistor T13 is turned on under the control of the active level potential of the pull-down node PD, thereby ensuring that the potential of the pull-up node PU is pulled low.
Fig. 6 is a timing diagram illustrating an operation of the shift register unit in the reverse scan mode according to an embodiment of the present invention, and the operation of the shift register unit in the reverse scan mode is described with reference to fig. 4 and 6. In the reverse scanning mode, the working process of the shift register unit comprises the following steps: a charging phase t1 ', a pull-down control phase t 2', an output phase t3 'and a reset phase t 4'. In the reverse scan mode, an active level signal is provided to the reverse scan control terminal CNB, and an inactive level signal is provided to the forward scan control terminal CN.
During the charging period t 1', an active level signal is provided to the second input terminal IN _2 and the third clock signal terminal CLK3, and an inactive level signal is provided to the first input terminal IN _1, the first clock signal terminal CLK1 and the second clock signal terminal CLK 2.
At this time, the second input transistor T2 is turned on, the active level signal of the reverse scan control terminal CNB is transmitted to the pull-up node PU, and the potential of the pull-up node PU is pulled up; meanwhile, since the third clock signal terminal CLK2 is at the active level potential, the second control transistor T9 is turned on, and the potential of the pull-down control node PD _ CN is pulled high, so that the fourth control transistor T7 is turned on; in addition, since the potential of the pull-up node PU is pulled high, the fifth control transistor T11 and the sixth control transistor T12 are turned on, and the pull-down node PD is at an intermediate level by the fourth control transistor T7, the fifth control transistor T11, and the sixth control transistor T12. At this time, referring to the above description, the pull-up control node PU _ CN is at the intermediate level, the first pull-down transistor T4, the second pull-down transistor T5 are turned on, and the third pull-down transistor T13 is turned off. Since the third pull-down transistor T13 is turned off, the pull-up node PU can be guaranteed to rise well. Under the control of the high level potential of the pull-up node PU, the pull-up transistor T3 is turned on, and the inactive level signal of the first clock signal terminal CLK1 is output to the output terminal OUT.
During the pull-down control period t 2', an active level signal is supplied to the second clock signal terminal CLK2, and an inactive level signal is supplied to the first input terminal IN _1, the second input terminal IN _2, the first clock signal terminal CLK1, and the third clock signal terminal CLK 3.
At this time, since the third clock signal terminal CLK3 provides the inactive level signal, the second control transistor T9 is turned off; since the second clock signal terminal CLK2 provides an active level signal, the first control transistor T10 is turned on, and the pull-down control node PD _ CN receives an inactive level signal from the forward scan control terminal CN, thereby turning off the fourth control transistor T7. The pull-up node PU maintains the high level potential during the charging phase, and therefore, the fifth control transistor T11 and the sixth control transistor T12 are turned on, so that the pull-down node PD is pulled down to a low level by the fifth control transistor T11, and the pull-up node PU _ CN is pulled up to a high level by the sixth control transistor T12. Since the pull-down node PD is at the inactive-level potential, the second pull-down transistor T5 is turned off.
At the output stage t 3', an active level signal is supplied to the first clock signal terminal CLK1, and an inactive level signal is supplied to each of the first input terminal IN _1, the second input terminal IN _2, the second clock signal terminal CLK2, and the third clock signal terminal CLK 3.
At this time, the potential of the pull-up node PU is further raised by the bootstrap action of the first capacitor C1, the pull-up transistor T3 is turned on, and the active level signal of the first clock signal terminal CLK1 is transmitted to the output terminal OUT. Since the second and third clock signal terminals CLK2 and CLK3 both provide the inactive level signal, the second and first control transistors T9 and T10 are both turned off, and the pull-down control node PD _ CN maintains the inactive level potential of the previous stage, thereby turning off the fourth control transistor T7. Since the output terminal OUT outputs the active level signal, the seventh control transistor T8 is turned on, and the pull-down node PD is turned on with the second power source terminal VGL, thereby reaching the inactive level potential. Since the pull-down node PD reaches the inactive level potential, the second pull-down transistor T5 is turned off, and the sixth control transistor T12 is turned on under the control of the active level potential of the pull-up node PU, so that the pull-up control node PU _ CN receives the high level signal of the first power source terminal VGH, and further the third control transistor T6 is turned on, thereby ensuring that the potential of the pull-down node PD is pulled down.
During the reset period t 4', an active level signal is supplied to the first input terminal IN _2 and the third clock signal terminal CLK3, and an inactive level signal is supplied to the second input terminal IN _1, the first clock signal terminal CLK1 and the second clock signal terminal CLK 2.
At this time, the first input transistor T1 is turned on, so that the pull-up node PU is turned on with the forward scan control terminal CN, the first capacitor C1 discharges, and the potential of the pull-up node PU is pulled low. The second control transistor T9 is turned on under the control of the active level signal of the third clock signal terminal CLK3, and the pull-down control node PD _ CN receives the active level signal of the reverse scan control terminal CNB. The fourth control transistor T7 is turned on under the control of the active-level potential of the pull-down control node PD _ CN, thereby causing the pull-down node PD to be pulled up to the active-level potential. Under the control of the active level potential of the pull-down node PD, the second pull-down transistor T5 and the first pull-down transistor T4 are turned on, so that the potentials of the pull-up control node PU _ CN and the output terminal OUT are pulled down. Meanwhile, the third pull-down transistor T13 is turned on under the control of the active level potential of the pull-down node PD, thereby ensuring that the potential of the pull-up node PU is pulled low.
Fig. 7 is a flowchart of a driving method of a shift register unit in a forward scan mode according to an embodiment of the present invention, and fig. 8 is a flowchart of a driving method of a shift register unit in a reverse scan mode according to an embodiment of the present invention, where the shift register unit is the shift register unit according to any of the embodiments. As shown in fig. 7, the driving method includes the following steps in the forward direction scan mode:
s11, during a charging phase of the forward scan mode, providing an effective level signal to the first input terminal and the second clock signal terminal, so that the input sub-circuit transmits a signal of a forward scan control terminal to the pull-up node, the first control sub-circuit transmits an effective level signal of the forward scan control terminal to the pull-down control node, the second control sub-circuit switches on the first power terminal and the pull-down node, the third control sub-circuit switches on the pull-down node and the second power terminal, and the pull-up node and the pull-up control node are both disconnected.
S12, in the pull-down control phase of the forward scan mode, providing an invalid level signal to the second clock signal terminal, and providing an valid level signal to the third clock signal terminal, so that the invalid level signal of the reverse scan control terminal is transmitted to the pull-down control node, and the second control sub-circuit connects the pull-down node and the second power terminal.
S13, during the output stage of the forward scan mode, providing an active level signal to the first clock signal terminal, so that the pull-up sub-circuit transmits the signal of the first clock signal terminal to the output terminal.
S14, in a reset phase of the forward scan mode, providing an active level signal to the second input terminal and the second clock signal terminal, so that the input sub-circuit transmits an inactive level signal of the reverse scan control terminal to the pull-up node, the first control sub-circuit transmits an active level signal of the second clock signal terminal to the pull-down control node, the second control sub-circuit transmits the voltage of the first power terminal to the pull-down node, and the pull-down sub-circuit pulls down the potential of the output terminal.
As shown in fig. 8, the driving method of the shift register unit further includes the following steps in the reverse scan mode:
s21, in a charging phase of the reverse scan mode, providing an effective level signal to the second input terminal and the third clock signal terminal, so that the input sub-circuit transmits a signal of the reverse scan control terminal to the pull-up node, the first control sub-circuit transmits an effective level signal of the reverse scan control terminal to the pull-down control node, the second control sub-circuit turns on the first power terminal and the pull-down node, the third control sub-circuit turns on the pull-down node and the second power terminal, and the pull-up node and the pull-up control node are both turned off.
S22, in a pull-down control stage of the reverse scan mode, providing an invalid level signal to the third clock signal terminal, and providing an valid level signal to the second clock signal terminal, so that the invalid level signal of the forward scan control terminal is transmitted to the pull-down control node, and the second control sub-circuit connects the pull-down node with the second power terminal.
S23, during the output stage of the reverse scan mode, providing an active level signal to the first clock signal terminal, so that the pull-up sub-circuit transmits the signal of the first clock signal terminal to the output terminal.
S24, in a reset phase of the reverse scan mode, providing an active level signal to the first input terminal and the third clock signal terminal, so that the input sub-circuit transmits an inactive level signal of the forward scan control terminal to the pull-up node, the first control sub-circuit transmits an active level signal of the third clock signal terminal to the pull-down control node, the second control sub-circuit transmits the voltage of the first power terminal to the pull-down node, and the pull-down sub-circuit pulls down the potential of the output terminal.
For the specific description of the steps S11 to S14 and S21 to S24, reference may be made to the corresponding contents in the above embodiments, which are not described herein again.
As can be seen from the above description of the shift register unit and the driving method thereof provided by the present invention, in the present invention, the pull-up node and the pull-down node of the shift register unit are not directly adjusted to each other any more, so that when the pull-up node is pulled up, the potential of the pull-down node is pulled down, thereby eliminating the competition between the pull-up node and the pull-down node, making the pull-up node rise well, and improving the driving capability of the shift register unit.
Fig. 9 is a schematic diagram of a gate driving circuit according to an embodiment of the present invention, and as shown in fig. 9, the gate driving circuit includes a plurality of cascaded shift register units, where the shift register units are shift register units in any of the embodiments.
As shown in FIG. 9, in the consecutive three stages of shift register units GOA (N-1), GOA (N), GOA (N +1), the output terminal of the middle stage GOA (N) is connected to the first input terminal of the next stage GOA (N +1), and is connected to the second input terminal of the previous stage GOAGOA (N-1).
The embodiment of the invention also provides a display device which comprises the grid drive circuit. The display device in the embodiment of the invention can be any product or component with a display function, such as electronic paper, an OLED panel, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator and the like.
It will be understood that the above embodiments are merely exemplary embodiments taken to illustrate the principles of the present invention, which is not limited thereto. It will be apparent to those skilled in the art that various modifications and improvements can be made without departing from the spirit and substance of the invention, and these modifications and improvements are also considered to be within the scope of the invention.
Claims (13)
1. A shift register unit, comprising: the control circuit comprises an input sub-circuit, a pull-up sub-circuit, a pull-down sub-circuit, a first control sub-circuit, a second control sub-circuit and a third control sub-circuit; the input sub-circuit, the third control sub-circuit and the pull-up sub-circuit are connected to a pull-up node, and the second control sub-circuit, the third control sub-circuit and the pull-down sub-circuit are connected to a pull-down node; the second control sub-circuit, the third control sub-circuit, and the pull-down sub-circuit are connected to a pull-up control node; the first control sub-circuit and the second control sub-circuit are connected to a pull-down control node;
the input sub-circuit is configured to transmit a signal of a forward scan control terminal to the pull-up node in response to control of a signal of a first input terminal, and to transmit a signal of a reverse scan control terminal to the pull-up node in response to control of a signal of a second input terminal;
the pull-up sub-circuit is configured to respond to the control of the electric potential of the pull-up node and conduct a first clock signal end and the output end of the shift register unit;
the first control sub-circuit is configured to respond to the control of a second clock signal terminal, and transmit a signal to the forward direction scanning control terminal to the pull-down control node; and responding to the control of a third clock signal terminal, and transmitting the signal of the reverse scanning control terminal to the pull-down control node;
the second control sub-circuit is configured to turn on a first power supply terminal with the pull-down node in response to control of the pull-down control node potential, and turn on a second power supply terminal with the pull-down node in response to control of the pull-up control node potential;
the third control sub-circuit is configured to turn on the first power supply terminal with the pull-up control node and turn on the pull-down node with the second power supply terminal in response to control of the pull-up node potential;
the pull-down sub-circuit is configured to respond to control of the pull-down node potential, pull-down the potential of the pull-up control node and the potential of the output end of the shift register unit, and conduct the pull-up node and the pull-up control node.
2. The shift register cell of claim 1, wherein the input sub-circuit comprises: a first input transistor and a second input transistor,
the grid electrode of the first input transistor is connected with the first input end, the first pole of the first input transistor is connected with the forward scanning control end, and the second pole of the first input transistor is connected with the pull-up node;
the grid electrode of the second input transistor is connected with the second input end, the first pole of the second input transistor is connected with the pull-up node, and the second pole of the second input transistor is connected with the reverse scanning control end.
3. The shift register cell of claim 1, wherein the pull-up sub-circuit comprises: a pull-up transistor and a first capacitor,
the grid electrode of the pull-up transistor is connected with the pull-up node, the first pole of the pull-up transistor is connected with the first clock signal end, and the second pole of the pull-up transistor is connected with the output end of the shift register unit;
and two ends of the first capacitor are respectively connected with the pull-up node and the output end of the shift register unit.
4. The shift register cell of claim 1, wherein the first control sub-circuit comprises: a first control transistor and a second control transistor,
the grid electrode of the first control transistor is connected with the second clock signal end, the first pole of the first control transistor is connected with the forward scanning control end, and the second pole of the first control transistor is connected with the pull-down control node;
the grid electrode of the second control transistor is connected with the third clock signal end, the first pole of the second control transistor is connected with the pull-down control node, and the second pole of the second control transistor is connected with the reverse scanning control end.
5. The shift register cell of claim 1, wherein the second control sub-circuit comprises: a third control transistor and a fourth control transistor,
the grid electrode of the third control transistor is connected with the pull-up control node, the first pole of the third control transistor is connected with the pull-down node, and the second pole of the third control transistor is connected with the second power supply end;
the grid electrode of the fourth control transistor is connected with the pull-down control node, the first pole of the fourth control transistor is connected with the first power supply end, and the second pole of the fourth control transistor is connected with the pull-down node.
6. The shift register cell of claim 1, wherein the third control sub-circuit comprises: a fifth control transistor and a sixth control transistor,
a gate of the fifth control transistor is connected to the pull-up node, a first pole of the fifth control transistor is connected to the pull-down node, and a second pole of the fifth control transistor is connected to the second power supply terminal;
the grid electrode of the sixth control transistor is connected with the pull-up node, the first pole of the sixth control transistor is connected with the first power supply end, and the second pole of the sixth control transistor is connected with the pull-up control node.
7. The shift register cell of claim 1, wherein the pull-down sub-circuit comprises: a first pull-down transistor, a second pull-down transistor, and a third pull-down transistor,
the grid electrode of the first pull-down transistor is connected with the pull-down node, the first pole of the first pull-down transistor is connected with the output end of the shift register unit, and the second pole of the first pull-down transistor is connected with the second power supply end;
the grid electrode of the second pull-down transistor is connected with the pull-down node, the first pole of the second pull-down transistor is connected with the pull-up control node, and the second pole of the second pull-down transistor is connected with the second power supply end;
the grid electrode of the third pull-down transistor is connected with the pull-down node, the first pole of the third pull-down transistor is connected with the pull-up node, and the second pole of the third pull-down transistor is connected with the pull-up control node.
8. The shift register unit according to any one of claims 1 to 7, further comprising:
a fourth control sub-circuit configured to pull down the potential of the pull-down node in response to control of a signal at an output terminal of the shift register unit.
9. The shift register cell of claim 8, wherein the fourth control sub-circuit comprises: a seventh control transistor, a gate of which is connected to the output terminal of the shift register unit, a first pole of which is connected to the pull-up node, and a second pole of which is connected to the second power source terminal.
10. The shift register unit according to any one of claims 1 to 7, further comprising: and two ends of the second capacitor are respectively connected with the pull-down node and the second power supply end.
11. A driving method of a shift register unit is characterized by comprising the following steps:
in a charging phase of a forward scanning mode, providing effective level signals to the first input end and the second clock signal end, so that the input sub-circuit transmits a signal of a forward scanning control end to the pull-up node, the first control sub-circuit transmits the effective level signal of the forward scanning control end to the pull-down control node, the second control sub-circuit conducts the first power end and the pull-down node, the third control sub-circuit conducts the pull-down node and the second power end, and the pull-up node and the pull-up control node, and the pull-up control node and the second power end are disconnected;
in a pull-down control stage of a forward scanning mode, providing an invalid level signal to the second clock signal terminal, and providing an effective level signal to the third clock signal terminal, so that the invalid level signal of the reverse scanning control terminal is transmitted to the pull-down control node, and the second control sub-circuit conducts the pull-down node and the second power supply terminal;
in the output stage of the forward scanning mode, providing an effective level signal to the first clock signal end so that the pull-up sub-circuit transmits the signal of the first clock signal end to the output end;
in a reset phase of a forward scanning mode, providing an active level signal to the second input terminal and the second clock signal terminal, so that the input sub-circuit transmits an inactive level signal of the reverse scanning control terminal to the pull-up node, the first control sub-circuit transmits an active level signal of the second clock signal terminal to the pull-down control node, the second control sub-circuit transmits a voltage of the first power terminal to the pull-down node, and the pull-down sub-circuit pulls down a potential of the output terminal;
in a charging phase of a reverse scan mode, providing an effective level signal to the second input terminal and the third clock signal terminal, so that the input sub-circuit transmits a signal of a reverse scan control terminal to the pull-up node, the first control sub-circuit transmits an effective level signal of the reverse scan control terminal to the pull-down control node, the second control sub-circuit switches on the first power terminal and the pull-down node, the third control sub-circuit switches on the pull-down node and the second power terminal, and the pull-up node and the pull-up control node, and the pull-up control node and the second power terminal are both disconnected;
in a pull-down control stage of the reverse scan mode, providing an invalid level signal to the third clock signal terminal, and providing an effective level signal to the second clock signal terminal, so that the invalid level signal of the forward scan control terminal is transmitted to the pull-down control node, and the second control sub-circuit conducts the pull-down node and the second power supply terminal;
in an output stage of the reverse scanning mode, providing an effective level signal to the first clock signal end so that the pull-up sub-circuit transmits a signal of the first clock signal end to an output end;
in a reset stage of the reverse scan mode, an active level signal is provided to the first input terminal and the third clock signal terminal, so that the input sub-circuit transmits an inactive level signal of the forward scan control terminal to the pull-up node, the first control sub-circuit transmits an active level signal of the third clock signal terminal to the pull-down control node, the second control sub-circuit transmits the voltage of the first power terminal to the pull-down node, and the pull-down sub-circuit pulls down the potential of the output terminal.
12. A gate driver circuit comprising the shift register unit according to any one of claims 1 to 10.
13. A display device comprising the gate driver circuit according to claim 12.
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| CN113724637A (en) * | 2021-08-31 | 2021-11-30 | 京东方科技集团股份有限公司 | Grid driving circuit, shift register unit and driving method thereof |
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| CN103021318A (en) * | 2012-12-14 | 2013-04-03 | 京东方科技集团股份有限公司 | Shifting register, working method of shifting register, grid electrode driving device and display device |
| KR20140127378A (en) * | 2013-03-14 | 2014-11-04 | 엘지디스플레이 주식회사 | Shift register and display device using the same |
| CN104810003A (en) * | 2015-05-21 | 2015-07-29 | 合肥京东方光电科技有限公司 | Shifting register, driving method of shifting register, grid driving circuit and display device |
| CN105096904A (en) * | 2015-09-30 | 2015-11-25 | 京东方科技集团股份有限公司 | Gate driving circuit, display device and driving method for gate driving circuit |
| CN105609136A (en) * | 2016-01-04 | 2016-05-25 | 京东方科技集团股份有限公司 | Shifting register unit, drive method, grid drive circuit and display device |
| CN106896957A (en) * | 2017-02-06 | 2017-06-27 | 京东方科技集团股份有限公司 | Touch control e equipment, touch control display apparatus and array base palte gate driving circuit |
| CN107068088A (en) * | 2017-04-14 | 2017-08-18 | 京东方科技集团股份有限公司 | Shift register cell and its driving method, gate driving circuit, display device |
| CN110060645A (en) * | 2019-05-07 | 2019-07-26 | 京东方科技集团股份有限公司 | A kind of shift register and its driving method, gate driving circuit, display device |
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| CN112599069A (en) * | 2020-12-22 | 2021-04-02 | 京东方科技集团股份有限公司 | Gate driving unit, gate driving circuit and display device |
| CN112599069B (en) * | 2020-12-22 | 2023-09-01 | 京东方科技集团股份有限公司 | Gate driving unit, gate driving circuit and display device |
| CN113724637A (en) * | 2021-08-31 | 2021-11-30 | 京东方科技集团股份有限公司 | Grid driving circuit, shift register unit and driving method thereof |
| CN113724637B (en) * | 2021-08-31 | 2023-12-26 | 京东方科技集团股份有限公司 | Gate driving circuit, shift register unit and driving method thereof |
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