CN107909960A - Shift register cell, shift-register circuit and display panel - Google Patents
Shift register cell, shift-register circuit and display panel Download PDFInfo
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- CN107909960A CN107909960A CN201810003043.3A CN201810003043A CN107909960A CN 107909960 A CN107909960 A CN 107909960A CN 201810003043 A CN201810003043 A CN 201810003043A CN 107909960 A CN107909960 A CN 107909960A
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- signal
- pull
- node
- switch element
- shift register
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Classifications
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
- G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0264—Details of driving circuits
- G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
Abstract
This disclosure relates to a kind of shift register cell, shift-register circuit and its display panel, are related to display technology field.The shift register cell includes：Input module, including more than two switch elements, under the control of input signal, the first power supply signal to be transmitted to pull-up node；Output module, under the control of the voltage signal of the pull-up node, by clock signal transmission to signal output part；Module is pulled down, under the control of the voltage signal of pull-down node, by second source signal transmission to the pull-up node and the signal output part；Storage capacitance, is connected between the pull-up node and the signal output part.The disclosure can avoid showing caused by output waveform distortion bad.
Description
Technical field
This disclosure relates to display technology field, more particularly to a kind of shift register cell, shift-register circuit and its
Display panel.
Background technology
With the development of optical technology and semiconductor technology, with liquid crystal display (Liquid Crystal Display,
LCD) and organic light emitting diode display (Organic Light Emitting Diode, OLED) be representative FPD
Utensil has the features such as frivolous, energy consumption is low, reaction speed is fast, excitation purity is good and contrast is high, is occupied in display field leading
Status.
Display device presented the development trend of high integration and low cost in recent years.Driven with array base palte row
(Gate Driver on Array, GOA) technology is representative, and gate driving circuit is integrated in array base palte using GOA technologies
Neighboring area so that while narrow frame design is realized, effectively improve the integrated level of display device, and reduce it and be manufactured into
This.
The output terminal grid line corresponding with one of every level-one shift register cell in GOA circuits is connected, for the grid
Line exports gated sweep signal, to realize progressive scan function.Since resolution ratio is higher and higher, cause the grid gate numbers of GOA
Amount is continuously increased, therefore more and more harsher to the rate request of storage capacitance charging.
It should be noted that information is only used for strengthening the reason to the background of the disclosure disclosed in above-mentioned background section
Solution, therefore can include not forming the information to the prior art known to persons of ordinary skill in the art.
The content of the invention
The purpose of the disclosure is to provide a kind of shift register cell, shift-register circuit and its display panel, into
And overcome at least to a certain extent due to the circuit output wave distortion caused by the limitation of correlation technique and defect the problem of.
Other characteristics and advantage of the disclosure will be apparent from by following detailed description, or partially by the disclosure
Practice and acquistion.
According to one aspect of the disclosure, there is provided a kind of shift register cell, including：
Input module, including more than two switch elements, under the control of input signal, by the first power supply signal
It is transmitted to pull-up node；
Output module, it is under the control of the voltage signal of the pull-up node, clock signal transmission is defeated to signal
Outlet；
Module is pulled down, under the control of the voltage signal of pull-down node, by second source signal transmission on described
Draw node and the signal output part；
Storage capacitance, is connected between the pull-up node and the signal output part.
In a kind of exemplary embodiment of the disclosure, the input module includes：
First switching element, its control terminal reception input signal, first end reception first power supply signal, second
End connects the pull-up node；
Second switch element, its control terminal reception input signal, first end reception first power supply signal, second
End connects the pull-up node.
In a kind of exemplary embodiment of the disclosure, the input module includes：
First switching element, its control terminal reception input signal, first end reception first power supply signal, second
End connects the pull-up node；
Second switch element, its control terminal reception input signal, first end reception first power supply signal, second
The first end of the 3rd switch element of end connection；
3rd switch element, its first end connect the second end of the second switch element, described in second end connection
Pull-up node.
In a kind of exemplary embodiment of the disclosure, the first switching element and the second switch element in parallel.
In a kind of exemplary embodiment of the disclosure, the output module includes：
4th switch element, its control terminal connect the pull-up node, and first end receives the clock signal, and second end connects
Connect the signal output part.
In a kind of exemplary embodiment of the disclosure, the drop-down module includes：
5th switch element, its control terminal connection pull-down node, the first end reception second source signal, second
End connects the signal output part；
6th switch element, its control terminal connection pull-down node, the first end reception second source signal, second
End connects the pull-up node.
In a kind of exemplary embodiment of the disclosure, further include：
Reseting module, under the control of reset signal, by the second source signal transmission to the pull-up node；
The reseting module includes：
7th switch element, its control terminal connection reset signal, the first end reception second source signal, second
End connects the pull-up node.
In a kind of exemplary embodiment of the disclosure, further include：
Module is pulled up, under the control of the voltage signal of the pull-up node, by the second source signal transmission
To the pull-down node；
Control module is pulled down, under the control of first voltage signal, by the first voltage signal transmission to described
Pull-down node；
Output control module, under the control of second voltage signal, by the second source signal transmission to described
Signal output part.
According to one aspect of the disclosure, there is provided a kind of shift-register circuit, including multiple cascades are above-mentioned any one
Shift register cell described in；
Wherein, the output signal of the signal output part of M grades of shift register cells is M+1 grades of shift register cells
Input signal.
According to one aspect of the disclosure, there is provided a kind of display panel, including display area and neighboring area；Wherein, institute
State neighboring area and be provided with shift-register circuit described in above-mentioned any one.
Shift register cell, shift-register circuit and its display surface that disclosure illustrative embodiments are provided
Plate, on the basis of the input module of conventional shift register cell structure, adds the quantity of switch element in input module,
It can ensure when input signal is high level, the charging rate of storage capacitance can be lifted by input module, and will not increase
Add the size for the leakage current for flowing through first switching element, improve the situation of GOA circuit output distortions, improve the steady of GOA circuits
It is qualitative, avoid resulting display bad.
It should be appreciated that the general description and following detailed description of the above are only exemplary and explanatory, not
The disclosure can be limited.
Brief description of the drawings
Attached drawing herein is merged in specification and forms the part of this specification, shows the implementation for meeting the disclosure
Example, and be used to together with specification to explain the principle of the disclosure.It should be evident that drawings in the following description are only the disclosure
Some embodiments, for those of ordinary skill in the art, without creative efforts, can also basis
These attached drawings obtain other attached drawings.
Fig. 1 schematically shows the structure diagram of shift register cell in the prior art；
Fig. 2 schematically shows the working timing figure of shift register cell in the prior art；
Fig. 3 schematically shows the structure diagram of shift register cell in disclosure exemplary embodiment；
Fig. 4 schematically shows the comparison of wave shape figure of shift register cell in disclosure exemplary embodiment；
Fig. 5 schematically shows the level link composition of shift-register circuit in disclosure exemplary embodiment.
Reference numeral：
The first to the tenth two-transistors of M1-M12
C1 storage capacitances
The first input signals of Input
Output signal output parts
PU pull-up nodes
PD pull-down nodes
CLK clock signals
RST reset signals
The first power supply signals of VDD
VSS/VGL second source signals
GCH first voltage signals
GCL second voltage signals
Embodiment
Example embodiment is described more fully with referring now to attached drawing.However, example embodiment can be with a variety of shapes
Formula is implemented, and is not understood as limited to example set forth herein；On the contrary, these embodiments are provided so that the disclosure will more
Fully and completely, and by the design of example embodiment comprehensively it is communicated to those skilled in the art.Described feature, knot
Structure or characteristic can be incorporated in one or more embodiments in any suitable manner.
In addition, attached drawing is only the schematic illustrations of the disclosure, it is not necessarily drawn to scale.Identical attached drawing mark in figure
Note represents same or similar part, thus will omit repetition thereof.Some block diagrams shown in attached drawing are work(
Can entity, not necessarily must be corresponding with physically or logically independent entity.These work(can be realized using software form
Energy entity, or these functional entitys are realized in one or more hardware modules or integrated circuit, or at heterogeneous networks and/or place
These functional entitys are realized in reason device device and/or microcontroller device.
Exemplary, with reference to shift register cell as shown in Figure 1, if increasing the size of first switching element M1,
Although the speed of capacitance charging can be increased, the leakage current for flowing through first switching element M1 can be increased at the same time, so as to
Cause GOA circuits by mistake output or export distortion situation, therefore shift-register circuit often occur it is various bad so that
Cause display abnormal.
The sequence diagram shown in the shift register cell and its Fig. 2 in correlation technique with reference to shown in Fig. 1, the shift LD
The course of work of device unit is as follows：
T1 in the first stage, when input signal Input is high level signal, input signal Input is the letter of upper level
The voltage signal of number output terminal Output, so that first switching element M1 conductings under the high level effect of input signal；At that time
When clock signal CLK is low level signal, the level of pull-up node PU is drawn high by the high level signal of signal input part, and then is given
Storage capacitance C1 charges, while the M8 and M6 conductings under the high level effect of pull-up node PU, by designing M5's and M9
Ratio, it is low level to make pull-down node PD, so that M10 and M4 shut-offs, ensure signal stablizes output.
In second stage t2, when input signal Input is low level, first switching element M1 is turned off, pull-up node PU
Continue to keep high level under the action of storage capacitance C1, the 3rd switch element M3 is tended to remain on.Clock signal clk is height
Level signal, pull-up node PU finally transmit drive signal due to the voltage of bootstrap effect amplification pull-up node PU to output terminal；
Pull-up node PU is high level signal at this time, and M6 conductings, so that M10 and M4 continue to close, ensure the stability output of signal.
In phase III t3, voltage signal, that is, reset signal of next stage signal output part Output, therefore reset signal
RST is high level, and M2 is turned under the control of reset signal high level, by it to pull-up node PU and signal output part
Output transmits low level signal, and M3 is closed, and moves output signal to VGL current potentials, to ensure that the stability of signal exports.
In fourth stage t4, since GCH is high potential always.At this time second stage by M2 to pull-up node PU and
Signal output part Output is discharged, and M6 is closed at this time, so will not discharge pull-down node PD；By
It is high potential, M9 and M5 conductings in GCH, pull-down node PD current potentials are driven high at this time, so that discharge tube M10 and M4 are opened, with right
Pull-up node PU and signal output part Output put making an uproar so that it is eliminated by the CLK Coupling noise voltages produced,
So as to ensure that low pressure exports, ensure the stability of signal output.
In subsequent time, GCH is high level always, the Coupling noises that CLK is produced be constantly in put the state of making an uproar until
The next frame row is opened.
It follows that this shift register cell can only ensure general Gate waveforms output, but for Gate ripples
The distortion of shape is really without improvement function.
In order to avoid the above problem, this example embodiment proposes a kind of shift register cell, for providing grid
Scanning signal；As shown in figure 3, the shift register cell can specifically include：
Input module 10, including more than two switch elements, under the control of input signal Input, by first
Power supply signal VDD is transmitted to pull-up node PU；
Output module 20, under the control of the voltage signal of the pull-up node PU, clock signal clk to be transmitted to
Signal output part Output；
Module 30 is pulled down, under the control of the voltage signal of pull-down node PD, second source signal VGL to be transmitted to
The pull-up node PU and signal output part Output；
Storage capacitance C1, is connected between the pull-up node PU and the signal output part Output.
In addition, the shift register cell can also include：
Reseting module 40, is saved for second source signal VSS to be transmitted to the pull-up under the control of reset signal RST
Point PU.
The shift register cell that disclosure illustrative embodiments are provided, in conventional shift register cell structure
On the basis of input module, the quantity of switch element in input module is added, it is ensured that when input signal is high level, lead to
The charging rate of input module lifting storage capacitance is crossed, and the size for the leakage current for flowing through first switching element will not be increased,
The situation of GOA circuit output distortions is improved, avoids resulting display bad.
In this example embodiment, the input module 10 can specifically include more than two switch elements, all
Switch element is used under the control of input signal Input the first power supply signal VDD being transmitted to pull-up node PU.
It should be noted that：The purpose that this example embodiment adjusts the input module 10 is to improve storage capacitance C1
Charging rate and avoid increase from flowing through the leakage current of switch element M1, avoid the circuit caused by leakage current is larger defeated
Go out the situation of distortion, as long as therefore can reach the effect above, two switch elements or more are set in the input module 10
A switch element, is not specifically limited here.
The shift register cell in this example embodiment is described in detail with reference to Fig. 3.Such as institute in Fig. 4
Show, by taking first switching element is N-type transistor to the 12nd switch element as an example, control terminal can be the grid of transistor,
First end can be the source electrode of transistor, and second end can be the drain electrode of transistor；But it should be recognized that the source electrode of transistor
Distinguished with drain electrode and without stringent, therefore be also likely to be the drain electrode that first end is transistor, second end is the source electrode of transistor.
Wherein：
In this example embodiment, all switch elements can use metal-oxide-semiconductor (Metal Oxide
Semiconductor, Metal-oxide-semicondutor field effect transistor) or transistor, specifically, first switching element
N-type metal-oxide-semiconductor can be used to the 12nd switch element.In addition, first switching element is to the 12nd switch element
P-type metal-oxide-semiconductor can be used.It should be noted that：For different transistor types, the level signal of each signal end needs phase
The adjustment change answered.
Specifically, input module 10 can include：First switching element M1, its control terminal receive input signal Input,
First end receives the first power supply signal VDD, second end connection pull-up node PU；Second switch element M2, its control terminal receive defeated
Enter signal Input, first end receives the first power supply signal VDD, second end connection pull-up node PU.It should be noted that first
Switch element can be with second switch element in parallel, and to reduce the resistance in input module 10, increase flows through input module 10
Total current, so as to improve the charging rate of storage capacitance C1.
Further, input module 10 can also be another structure, specifically include：First switching element M1, it is controlled
End receives input signal Input, and first end receives the first power supply signal VDD, second end connection pull-up node PU；Second switch member
Part M2, its control terminal receive input signal Input, and first end receives the first power supply signal VDD, the 3rd switch member of second end connection
The first end of part M3；3rd switch element M3, the second end of its first end connection second switch element M2, second end connection pull-up
Node PU.
It should be noted that second switch element can be with the 3rd switch elements in series, such as the leakage of second switch element
Pole connects the drain electrode of the 3rd switch element, and the source electrode of second switch element receives the first power supply signal VDD, the 3rd switch element
Source electrode connect pull-up node PU, first switching element M1 can with connect after second switch element and the 3rd switch element simultaneously
Connection, to reduce the resistance in input module 10, increase flows through the total current of input module 10, improves the charging speed of storage capacitance C1
Degree；In addition, the leakage current for flowing through first switching element M1 is reduced by second switch element and the 3rd switch elements in series,
So as to avoid GOA circuit outputs abnormal.Wherein, the quantity of serialized switch elements is not limited to two, specifically can be according to reality
Demand is configured.
Output module 20 can include：4th switch element M4, its control terminal connection pull-up node PU, when first end receives
Clock signal CLK, second end connection signal output part Output.
Drop-down module 30 can include：5th switch element M5, its control terminal connection pull-down node PD, first end receive the
Two power supply signal VGL, second end connection signal output part Output；Drop-down module 30 can also include：6th switch element M6,
Its control terminal connects pull-down node PD, and first end receives second source signal VGL, second end connection pull-up node PU.
Reseting module 40 can include：7th switch element M7, its control terminal connection reset signal RST, first end receive
First power supply signal VSS, second end connection pull-up node PU.
The shift register provided in this example can also include：Module 50 is pulled up, for the voltage in pull-up node PU
Under the control of signal, second source signal VGL is transmitted to pull-down node PD；Control module 60 is pulled down, in first voltage
Under the control of signal GCH, first voltage signal GCH is transmitted to pull-down node PD；Output control module 70, in the second electricity
Under the control for pressing signal GCL, second source signal VGL is transmitted to signal output part Output.M12
Wherein, pull-up module 50 can specifically include：8th switch element M8, its control terminal connection pull-up node PU, the
One end receives second source signal VGL, and second end connects the second end of the tenth switch element M10, to pass through the tenth switch element
Pull-down node PD is connected with the 11st switch element；9th switch element M9, its control terminal connection pull-up node PU, the first termination
Receive second source signal VGL, second end connection pull-down node PD.
Drop-down control module 60 can specifically include：Tenth switch element M10, its control terminal and first end receive first
The second end of the 8th switch element of voltage signal GCH, second end connection pull-down node PD connection, while connect the 11st switch member
The control terminal of part M11, to connect pull-down node PD by the 11st switch element；11st switch element M11, its control terminal connect
The second end of the tenth switch element is connect, first end receives first voltage signal GCH, second end connection pull-down node PD.
Output control module 70 can specifically include：12nd switch element M12, its control terminal receive second voltage signal
GCL, first end receive second source signal VGL, second end connection signal output part Output.
In the following, the working timing figure with reference to shown in Fig. 2 runs to control sequential the shift register cell in each stage
Operation principle be specifically described.Wherein, the first power supply signal VDD is high level signal, second source signal VGL/VSS
For low level signal, first voltage signal GCH is high level signal, and second voltage signal GCL is low level signal.
The course of work of the shift-register circuit can specifically include with the next stage：
Firstly the need of explanation, first voltage signal GCH is high level signal always, therefore the tenth switch element and
11 switch elements tend to remain on, and pull-down node PD keeps high level, so that the 5th switch element and the 6th switch
Element tends to remain on.
First stage t1：When input signal Input is high level signal, input signal Input is the signal of upper level
The voltage signal of output terminal Output, so that first switching element M1 conductings under the high level effect of input signal；Work as clock
When signal CLK is low level signal, the level of pull-up node PU is drawn high by the high level signal of signal input part, and then deposited
Storing up electricity holds C1 and charges, and at the same time, second switch element M2 and the 3rd switch element M3 are also in the height of input signal Input
The lower conducting of level effect, the size of charging current is 2 times of charging current in conventional shift register cell at this time, can make to deposit
Storing up electricity holds C1 quick charges to high level.
In second stage t2, when input signal Input is low level, switch element M1, M2, M3 are turned off, pull-up section
Point PU continues to keep high level under the action of storage capacitance C1, and the 4th switch element M4 is tended to remain on.Clock signal clk
For high level signal, pull-up node PU is finally transmitted to output terminal and driven due to the voltage of bootstrap effect amplification pull-up node PU
Signal；Due to bootstrap effects of the storage capacitance C1 full of after than storage capacitance in the conventional shift register cell shown in Fig. 1
More preferably, the voltage after bootstrapping is close to 2 times of VGH voltages, therefore can ensure the stability output of signal.
In phase III t3, the voltage signal of next stage signal output part Output is reset signal, therefore resets letter
Number RST is high level, and M7 is turned under the control of reset signal high level, is transmitted to second source signal VSS by it
Node PU, M4 closing is drawn, since first voltage signal GCH is always high level, is opened by the tenth switch element M10 and the 11st
Close element M11 and first voltage signal GCH is transmitted to pull-down node PD, so that the switch members of the 5th switch element M5 and the 6th
Part M6 is turned on, and second source signal VGL is transmitted to signal output part Output, to ensure that stablizing for signal exports.
In fourth stage t4, since GCH is high potential always, and in second stage by M7 to pull-up node PU and letter
Number output terminal Output is discharged, and M9 is closed at this time, so will not discharge pull-down node PD；Due to
GCH is high potential, M10 and M11 conductings, and pull-down node PD current potentials are driven high at this time, so that discharge tube M5 and M6 are opened, with to upper
Node PU and signal output part Output is drawn put making an uproar so that it is eliminated by the CLK Coupling noise voltages produced, from
And ensure that low pressure exports, ensure the stability of signal output.M1, M2 are turned off at this time, and potential difference is not present in M3 both ends, therefore
It is very small by the leakage current of M2, it can be ignored.
The workflow of subsequent time is then identical with the workflow of conventional shift register cell, and details are not described herein again.
It should be noted that：After above-mentioned fourth stage t4, shift register cells at different levels are repeated according to actual conditions
Above-mentioned first stage t1 and fourth stage t4.
In order to which the distortion situation of the output signal to shift register cell is verified, the output wave with reference to shown in Fig. 4
Shape figure illustrates.It can be seen that by the figure A in Fig. 4：There are one for the output waveform of pull-up node PU and pull-down node PD
There are certain rising edge in the output waveform of fixed rising edge or trailing edge, output signal G (n) and G (n-1), from
And cause the phenomenon for output waveform distortion occur；And in Fig. 4 scheme B in output waveform for A is schemed, pull-up node PU with
And the amplitude of rising edge or trailing edge reduces in the output waveform of pull-down node PD, signal G (n) and G (n-1) output wave is exported
Rising edge present in shape disappears, it can be said that the shift register cell provided in bright example can improve output signal
Distortion situation, put forward the stability of high output signal.
Understood based on the above process, this example embodiment in input module 10 by increasing second switch element and the
Three switch elements, not only increase the charging rate of storage capacitance C1, and avoid increase and flow through first switching element M1's
Leakage current, avoids the situation of the circuit output distortion caused by leakage current is larger, improves the stability of GOA circuits, keeps away
It is bad to exempt from resulting display.
This example embodiment also proposed a kind of shift-register circuit, gate driving circuit can be used as to be applied to bag
In the GOA circuits for including one or more clock signal clks；As shown in figure 5, the shift-register circuit can include multiple levels
The above-mentioned shift register cell of connection；Wherein, the output signal of the signal output part Output of M grades of shift register cells is
The input signal Input of M+1 grades of shift register cells.Such as the first reset signal in shift register cell SR1 can
Think the output signal of the second shift register cell SR2, the input signal in the first shift register cell SR1 can be one
Initial signal STV.
On this basis, the scan mode of the shift-register circuit can include forward scan or reverse scan.
When using forward scan, the input signal Input of first order shift register cell is initial signal.When using reverse scan
When, the input signal Input of afterbody shift register cell is initial signal.
It should be noted that：The detail of each modular unit in the shift-register circuit is in corresponding shifting
It is described in detail in bit register unit, which is not described herein again.
This example embodiment also proposed a kind of display panel, including display area and neighboring area, and in peripheral region
Domain is provided with above-mentioned shift-register circuit.
Understand that shift-register circuit is integrated in the periphery of display panel using GOA technologies by the present embodiment based on this, from
And realize the design of narrow side frame panel, while can also reduce the manufacture cost of display panel.
Wherein, the display panel is specifically as follows LCD display panel, OLED display panel, PLED (Polymer
Light-Emitting Diode, polymer LED) display panel, PDP (Plasma Display Panel, wait from
Sub- display panel) etc., specific limitation is not done for the applicable of display panel here.
This example embodiment also provides a kind of display device, including above-mentioned display panel.Wherein, the display device
Such as it can include that mobile phone, tablet computer, television set, laptop, Digital Frame, navigator etc. are any to have display function
Product or component.
Those skilled in the art will readily occur to the disclosure its after considering specification and putting into practice invention disclosed herein
Its embodiment.This application is intended to cover any variations, uses, or adaptations of the disclosure, these modifications, purposes or
Person's adaptive change follows the general principle of the disclosure and including the undocumented common knowledge in the art of the disclosure
Or conventional techniques.Description and embodiments are considered only as exemplary, and the true scope and spirit of the disclosure are by appended
Claim is pointed out.
Claims (10)
- A kind of 1. shift register cell, it is characterised in that including：Input module, including more than two switch elements, under the control of input signal, the first power supply signal to be transmitted To pull-up node；Output module, under the control of the voltage signal of the pull-up node, by clock signal transmission to signal output part；Module is pulled down, under the control of the voltage signal of pull-down node, second source signal transmission to the pull-up to be saved Point and the signal output part；Storage capacitance, is connected between the pull-up node and the signal output part.
- 2. shift register cell according to claim 1, it is characterised in that the input module includes：First switching element, its control terminal receive the input signal, and first end receives first power supply signal, and second end connects Connect the pull-up node；Second switch element, its control terminal receive the input signal, and first end receives first power supply signal, and second end connects Connect the pull-up node.
- 3. shift register cell according to claim 1, it is characterised in that the input module includes：First switching element, its control terminal receive the input signal, and first end receives first power supply signal, and second end connects Connect the pull-up node；Second switch element, its control terminal receive the input signal, and first end receives first power supply signal, and second end connects Connect the first end of the 3rd switch element；3rd switch element, its first end connect the second end of the second switch element, and second end connects the pull-up Node.
- 4. the shift register cell according to Claims 2 or 3, it is characterised in that the first switching element with it is described Second switch element in parallel.
- 5. shift register cell according to claim 1, it is characterised in that the output module includes：4th switch element, its control terminal connect the pull-up node, and first end receives the clock signal, second end connection institute State signal output part.
- 6. shift register cell according to claim 1, it is characterised in that the drop-down module includes：5th switch element, its control terminal connect the pull-down node, and first end receives the second source signal, and second end connects Connect the signal output part；6th switch element, its control terminal connect the pull-down node, and first end receives the second source signal, and second end connects Connect the pull-up node.
- 7. shift register cell according to claim 1, it is characterised in that further include：Reseting module, under the control of reset signal, by the second source signal transmission to the pull-up node；The reseting module includes：7th switch element, its control terminal connect the reset signal, and first end receives the second source signal, and second end connects Connect the pull-up node.
- 8. shift register cell according to claim 1, it is characterised in that further include：Module is pulled up, under the control of the voltage signal of the pull-up node, by the second source signal transmission to institute State pull-down node；Control module is pulled down, under the control of first voltage signal, by the first voltage signal transmission to the drop-down Node；Output control module, under the control of second voltage signal, by the second source signal transmission to the signal Output terminal.
- A kind of 9. shift-register circuit, it is characterised in that claim 1-8 any one of them displacement including multiple cascades Register cell；Wherein, the output signal of the signal output part of M grades of shift register cells is the defeated of M+1 grades of shift register cells Enter signal.
- 10. a kind of display panel, it is characterised in that including display area and neighboring area；Wherein, the neighboring area is provided with Shift-register circuit described in claim 9.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
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| WO2019237889A1 (en) * | 2018-06-12 | 2019-12-19 | 京东方科技集团股份有限公司 | Shift register and shift register circuit, display device |
| CN111210786A (en) * | 2020-01-22 | 2020-05-29 | 合肥鑫晟光电科技有限公司 | Shifting register unit, grid driving circuit, display substrate and display device |
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