CN111201609B - 具有可调阈值电压的高电子迁移率晶体管 - Google Patents

具有可调阈值电压的高电子迁移率晶体管 Download PDF

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CN111201609B
CN111201609B CN201880053671.0A CN201880053671A CN111201609B CN 111201609 B CN111201609 B CN 111201609B CN 201880053671 A CN201880053671 A CN 201880053671A CN 111201609 B CN111201609 B CN 111201609B
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transistor
gate
threshold voltage
source
fin
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CN111201609A (zh
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张坤好
N·乔杜里
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Mitsubishi Electric Corp
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Mitsubishi Electric Corp
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Abstract

一种高电子迁移率晶体管包括：一组电极，诸如源极(110)、漏极(120)、顶栅极(130)和侧栅极(140，150)；并且包括具有在源极和漏极之间延伸的鳍的半导体结构。顶栅极布置在鳍的顶部上，并且侧栅极距顶栅极一定距离而布置在鳍的侧壁上。半导体结构包括位于顶栅极下方的覆盖层(101)和布置在覆盖层下方以用于提供导电性的沟道层(102)。覆盖层包括氮化物基半导体材料，以使异质结能够在源极和漏极之间形成载流子沟道。

Description

具有可调阈值电压的高电子迁移率晶体管
技术领域
本发明总体上涉及诸如高电子迁移率晶体管之类的半导体器件。
背景技术
随着无线通信市场的近期兴起以及功率应用的稳定但持续的发展，微波晶体管在人类活动的许多方面正发挥着至关重要的作用。对微波晶体管性能的要求正在变得越来越高。在个人移动通信应用中，下一代手机需要更宽的带宽和提高的效率。卫星通信和TV广播的发展要求放大器以更高频率(从C波段到Ku波段，再到Ka波段)和更大功率操作，以减小终端用户的天线尺寸。由于速度或数据传输速率的不断增加，对宽带无线互联网连接也有相同的要求。
由于这些需求，对基于Si/SiGe、GaAs、SiC和GaN的高性能微波晶体管和放大器的开发进行了大量投资。约翰逊品质因数(JM)仅基于材料特性给出了功率-频率极限，并且可以用于比较用于高频率和大功率应用的不同材料。对大功率和高频率的要求需要基于具有高击穿电压和高电子速度二者的半导体材料的晶体管。从这一点出发，具有较高JM的宽带隙材料(诸如GaN和SiC)是优选的。因为最终的击穿电场是带间碰撞电离所需的电场，所以宽带隙产生更高的击穿电压，从而允许高频操作。
尽管具有类似的击穿电场和饱和电子速度，但GaN形成异质结的能力比SiC优越。GaN可以用于制造高电子迁移率晶体管(HEMT)，而SiC仅可以用于制造金属半导体场效应晶体管(MESFET)。HEMT的优点包括高载流子浓度以及归因于减少的电离杂质散射的更高电子迁移率。高载流子浓度和高电子迁移率的结合导致高电流密度和低沟道电阻，这对于高频操作和功率开关应用尤其重要。
从放大器的角度来看，GaN基HEMT与现有生产技术相比具有许多优势。高输出功率密度允许制造具有相同输出功率的尺寸小得多的器件。由于尺寸越小阻抗越高，使得放大器中能够进行更容易且损耗更低的匹配。由于其击穿电场高而使其在高压下操作，不仅减少了对电压转换的需求，而且还提供了获得高效率(放大器的关键参数)的潜力。宽带隙还使GaN基HEMT能够在高温下操作。同时，HEMT比MESFET提供了更好的噪声性能。
放大器应用中的由出色的半导体性能带来的这些吸引人的特性使得GaN基HEMT成为微波功率应用中非常有前景的候选。
在耗尽模式高电子迁移率晶体管(HEMT)中，从栅极产生的电场用于耗尽在宽和窄能量带隙半导体(诸如AlN/GaN或AlGaN/GaN)的界面处的二维电子气沟道。控制电压可以被施加到栅极以直接影响和控制流过沟道的电流的量。耗尽模式晶体管用作开关时，充当“常开”器件。对于增强模式晶体管，不存在沟道，并且没有电流流动，直到晶体管被偏置以进行操作。具体地，晶体管被偏置并且电压被施加到栅极，以便将二维电子气沟道移动到费米能级以下。一旦在源极和漏极之间施加了另一电压，二维电子气沟道中的电子会从源极向漏极移动。增强模式晶体管通常用于数字和模拟集成电路(IC)，并且可以用作“常关”器件。
增强模式(E模式)HEMT对于诸如RF/微波功率放大器或开关之类的模拟电路应用是有作用的。
目前正在研究将E模式和耗尽模式(D模式)HEMT集成的直接结合FET逻辑(DCFL)(称为E/D DCFL)，以用于高速和高密度数字电路应用。
宽带隙AlGaN/GaN HEMT由于其大功率和高速处理能力而成为RF/微波功率放大器感兴趣的器件。针对大功率、高频应用，继续推动尺寸缩小和性能提高。尤其是，与传统AlGaN势垒相比，AlN的大带隙(6.2eV)提供了改善的载流子限制并降低了栅极漏电流，并实现低电场载流子传输和高电场载流子传输二者的改善。高载流子密度和高载流子迁移率二者希望获得高输出电流。
为了减少合金散射并提高沟道导电率，在可以将HEMT的栅极区域下方的薄层密度降低到足以进行E-模式操作的情况下，具有非常薄的AlN阻挡层的结构对于高速、高压、大功率器件是具有吸引力的选项。
AlGaN/GaN HEMT的当前研究表明了在大功率、高温应用中的前景。另外，对于使用晶体管作为开关或具有高温能力的集成电路的应用，还希望具有常关或增强模式的操作器件。因此，在本领域中仍然需要能够在大功率、高压、高速和/或高温应用中能够执行的器件的改进的方法和结构。
发明内容
技术问题
一些实施方式基于以下认识：存在可能难以预先预测和控制的、影响晶体管的阈值电压值的许多因素。例如，阈值电压可能受到在各个晶体管之间变化的晶体管的制造细节影响。而且，阈值电压可能受到在各个晶体管之间也变化的晶体管的操作细节影响。为此，一些实施方式是以下认识：在晶体管操作期间改变(例如，调整)晶体管的阈值电压可以是有益的。
附加地或另选地，载流子沟道的密度取决于相对于晶体管的源极端子施加到沟道的电压。有时，施加到源极的电压的增加必然需要改变阈值电压，例如，使阈值电压相对于源极朝向正域移动。
一些实施方式基于以下理解：可以通过使晶体管的载流子沟道耗尽来调制阈值电压的值，这是因为晶体管的阈值电压是沟道中的载流子密度的函数。例如，在一个实施方式中，晶体管是具有异质结构以在源极和漏极之间形成载流子沟道的高电子迁移率晶体管(HEMT)。高载流子密度产生负电压，而低载流子密度产生正阈值电压。
一些实施方式基于另一种认识：通过在与漏极-源极电压方向垂直的方向上施加电压，可以使载流子沟道耗尽。
一些实施方式基于以下认识：除了晶体管的在本文中称为顶栅极并且用于调制源极和漏极之间的载流子沟道的电导率的栅极之外，可以布置另一栅极(在本文中称为侧栅极)以使沟道耗尽并调制阈值电压。一些实施方式基于以下理解：为了执行这种调制，需要将侧栅极布置为与顶栅极间隔开一定距离，使得可以向不同栅极独立地施加两个不同的电压，从而在晶体管的侧壁处使这两个栅极能够足够靠近载流子沟道。
为此，一个实施方式公开了一种晶体管，其包括源极、漏极、顶栅极、侧栅极以及具有在源极和漏极之间延伸的鳍(fin)的半导体结构。顶栅极布置在鳍的顶部上，并且相对于源极施加到顶栅极的电压调制源极和漏极之间的载流子沟道的导电率。侧栅极以距顶栅极一定距离的方式布置在鳍的侧壁上，并且相对于源极施加到侧栅极的电压调制晶体管的阈值电压，从而使晶体管的阈值电压可调。
在一些实现中，晶体管包括布置在鳍的相对侧壁上的两个侧栅极。两个侧栅极能够更好地控制沟道的载流子。
半导体结构的鳍使得侧栅极布置为足够靠近载流子沟道。例如，在一个实施方式中，鳍的宽度小于400nm。该宽度能够实现用于耗尽载流子沟道所需的最大电容。然而，一些实施方式使用负电容的原理来增加鳍的宽度。例如，在一个实施方式中，晶体管包括布置在侧栅极和鳍的侧壁之间的铁电氧化物(FE)层。FE层形成负电容器，从而允许鳍的宽度大于400nm。
附加地或另选地，在一些实现中，介电层布置在侧栅极和鳍的侧壁之间。介电层减少了栅极电流，因此降低了功耗。
在一些实现中，侧栅极由半导体材料制成。如果选择适当的话，侧栅极的半导体材料使得制造工艺更容易，并且产生更高性能。例如，在一个实施方式中，侧栅极的半导体材料是p掺杂半导体，通过将空穴注入到沟道中使得阈值电压甚至更靠正。
在一些实施方式中，侧栅极具有L形，其中，L形的第一腿部布置在鳍的侧壁上，并且L形的第二腿部基本垂直于第一腿部。该实施方式简化了侧栅极在鳍化的半导体结构上的生长。
附加地或另选地，L形简化了向侧栅极施加电压以调制晶体管的阈值电压。例如，在一些情况下，施加到侧栅极的电压为负，以使阈值电压相对于源极朝向正域移动。例如，施加到侧栅极的电压为正，以使阈值电压相对于源极朝向负域移动。对于功率电子和数字应用，希望具有常关操作，这能够通过向侧栅极施加负电压来实现。但是，如果我们不关心阈值电压(针对RF器件的情况)，则我们能够向栅极施加正电压，增加沟道中的载流子密度，由此具有更多的电流。
一些实施方式确认了，仿真结果表明采用一些实施方式的原理的晶体管的跨导的线性度增加。为此，一些实施方式选择施加到侧栅极的、与晶体管的线性度成比例的负电压的绝对值。任何RF器件中的线性度劣化是由许多因素引起的，这些因素之一是源扼流效应(source choking effect)。当源极具有比沟道区低的载流能力时会发生这种效应。所提出的晶体管通过使沟道耗尽来消除这种效应，这反过来降低了沟道的载流能力。
技术方案
因此，一个实施方式公开了一种高电子迁移率晶体管(HEMT)。HEMT包括：一组电极，其包括源极、漏极、顶栅极和侧栅极；以及半导体结构，其具有在源极和漏极之间延伸的鳍，其中，顶栅极布置在鳍的顶部上，其中，侧栅极距顶栅极一定距离布置在鳍的侧壁上，其中，半导体结构包括位于顶栅极下方的覆盖层和布置在覆盖层下方用于提供导电性的沟道层，其中，覆盖层包括氮化物基半导体材料，以使异质结构能够在源极和漏极之间形成载流子沟道。
另一实施方式公开了一种用于控制晶体管的方法，该晶体管包括具有在晶体管的源极和漏极之间延伸的鳍的半导体结构，其中，晶体管的顶栅极布置在鳍的顶部上，并且晶体管的侧栅极距顶栅极一定距离布置在鳍的侧壁上。该方法包括：相对于源极向顶栅极施加电压，以调制源极和漏极之间的载流子沟道的导电率；以及相对于源极向侧栅极施加电压，以调制晶体管的阈值电压。
另一实施方式公开了一种用于制造晶体管的方法。该方法包括：提供基板和半导体结构，该半导体结构包括覆盖层和具有至少一个载流子沟道的沟道层；蚀刻半导体结构以限定晶体管的有源区；通过金属沉积和退火形成源极和漏极；通过干蚀刻和湿蚀刻的组合在半导体结构中形成鳍；沉积侧栅极；以及沉积顶金属栅极。
附图说明
[图1]
图1示出了根据一些实施方式的高电子迁移率晶体管(HEMT)的3-D示意图。
[图2]
图2示出了根据一个实施方式的晶体管的沟道的中间的截面。
[图3]
图3示出了沿着图2的晶体管的截面A-A'的能带图310。
[图4A]
图4A示出了不同实施方式的晶体管的电子密度截面轮廓。
[图4B]
图4B示出了不同实施方式的晶体管的电子密度截面轮廓。
[图5]
图5示出了针对不同侧栅极电压的仿真的IDS-VGS特性。
[图6]
图6示出了由一些实施方式使用的针对不同鳍厚度的阈值电压随侧栅极电压的变化。
[图7]
图7示出了根据一个实施方式的针对100nm鳍宽晶体管的不同侧栅极电压(VSG)的IDS-VDS特性。
[图8]
图8示出了根据一个实施方式的晶体管的沟道的中间的2-D截面。
[图9]
图9示出了根据一个实施方式的晶体管的沟道的中间的2-D截面。
[图10]
图10示出了根据一个实施方式的晶体管的沟道的中间的2-D截面。
[图11]
图11示出了根据各种实施方式的用于控制晶体管的阈值电压的方法的流程图。
[图12]
图12示出了根据一些实施方式的用于制造半导体器件的方法的框图。
具体实施方式
图1示出了根据一些实施方式的高电子迁移率晶体管(HEMT)的3-D示意图。该晶体管包括这样的半导体结构，该半导体结构具有形成于覆盖层101和沟道层102之间的化合物半导体异质结构，以使得在覆盖层和沟道层的界面处形成二维电子气(2-DEG)103。源极110和漏极120被置为与所述2-DEG电连接。半导体结构具有在源极和漏极之间延伸的鳍199，以有助于将标记为140和/或150的侧壁栅极置于鳍的一侧或相对两侧上，以便调节沟道中的载流子密度，从而调节阈值电压。标记为130的顶栅极置于覆盖层的顶部，以控制沟道的导电率。在实施方式中通过仅一个侧壁栅极来控制阈值电压，然而，另选实施方式包括两个侧栅极以提供更好的可控制性。
图2示出了根据一个实施方式的晶体管的沟道的中间的截面。在该实施方式中，侧壁栅极是L形的，其中，L形侧面的垂直腿部放置在鳍侧壁的附近，而水平腿部仅仅是便于向该栅极施加电压。
图3示出了沿着图2的晶体管的截面A-A'的能带图310。根据该能带图，一些实施方式得到了HEMT的标记为333的阈值电压的等式。从该等式应注意的是，阈值电压与2-DEG浓度具有线性关系。因此，可以推断出能够通过调制2-DEG密度来调制HEMT的阈值电压。通常，由于2-DEG密度高，HEMT的阈值电压为负，使其成为常开器件。然而，通过使2-DEG耗尽，可以使阈值电压为正，从而使器件常关。为了调制2-DEG密度，设置了侧壁栅极。
图4A示出了由一些实施方式使用的0V的侧栅极电压的电子密度截面轮廓。在此，刻度410为log(电子浓度)。我们可以观察到，在101和102层的界面处，电子浓度非常高，并且随着沿两个方向远离界面，电子浓度单调降低。
图4B示出了对于-4V的侧栅极电压的电子密度截面轮廓。与图4A相比，电子密度已经显著降低了至少三个数量级。这是因为，当我们向侧栅极施加负偏压时，在沟道的费米能级将移动得更高，并且电子密度对费米能级具有指数依从关系(exp(-费米能级/(kBT)))。由于阈值电压取决于电子密度，因此通过侧栅极调制电子密度，能够调制阈值电压。
图5示出了针对不同侧栅极电压的仿真的IDS-VGS特性。可以根据IDS-VGS特性来测量晶体管的阈值电压。漏极电流开始快速增加时的栅极电压被称为阈值电压，该阈值电压可以通过外推IDS曲线的线性区域并找到其与栅极电压轴交叉的点来找到。如此处所示范的，随着向侧栅极施加越来越多的负偏压，晶体管的阈值电压不断增加。这是因为在侧栅极施加负偏压会耗尽沟道。这里，510是侧栅极电压的IDS-VGS曲线，VSG＝0V，520是针对VSG＝-2V的，530是针对VSG＝-4V的。
图6示出了由一些实施方式使用的针对不同鳍厚度的阈值电压随侧栅极电压的变化。此处，分别针对标记为610、620、630和640的鳍宽度100nm、200nm、300nm和400nm呈现了仿真曲线。如果我们可以定义可控制性参数α，则该参数被定义为其由曲线的斜率给出。理想情况下，我们希望α的大小尽可能大，但是由于物理原因，它不能大于1。如该图所示，随着鳍厚度增加，α值减小，这是因为随着鳍厚度增加，侧壁由于电容减小而失去对沟道的可控制性。如果鳍厚度大于400nm，则可控制性参数α非常接近于零，这为我们提供了鳍厚度的上限。
图7示出了根据一个实施方式的针对100nm鳍宽度晶体管的不同侧栅极电压(VSG)的IDS-VDS特性。曲线710示出了其中VSG＝0V的示例，并且曲线720示出了当VSG＝-3V时的示例。当施加负调整电压时，由于阈值电压的增加，漏电流会急剧下降，这进而降低了过驱动电压(VDS-VTH)。
图8示出了根据一个实施方式的晶体管的沟道的中间的2-D横截面。在该实施方式中，晶体管包括夹置在顶栅极和覆盖层之间的介电层103。这种结构使栅极漏电流减小并通过减少功率损耗来提高效率。
图9示出了根据一个实施方式的晶体管的沟道的中间的2-D截面。在该实施方式中，晶体管包括夹置在侧栅极和鳍侧壁之间的介电层104和105。该介电层有助于减少来自侧壁的栅极泄漏。
图10示出了根据一个实施方式的晶体管的沟道的中间的2-D截面。在该实施方式中，半导体结构包括后阻挡层107。后阻挡层的目的是对形成于沟道和覆盖层的界面处的2-DEG提供量子限制。根据一个实施方式，后阻挡掺杂有p型掺杂剂。
图11示出了根据各种实施方式的用于控制晶体管的阈值电压的方法的流程图。该方法在1110中在不施加任何侧栅极电压的情况下测量阈值电压。该方法在1130中检查期望的阈值电压，以检测相对于源极改变阈值电压的符号的请求。例如，如果需要更高的阈值电压，则该方法在1120中向侧栅极施加负偏压。例如，当阈值电压为负并且需要正阈值电压时，该方法向侧栅极施加负电压。另一方面，如果需要更低的阈值电压，则该方法在1140中向侧栅极施加正偏压。例如，当阈值电压为正且需要负阈值电压时，该方法向侧栅极施加正电压。
附加地或另选地，如果需要增强模式操作，则该方法保持增加侧栅极处的负偏压，直到阈值电压变得大于零。通常，对于驱动器电路和大多数电力电子应用，增强模式操作是优选的。
图12示出了根据一些实施方式的用于制造半导体器件的方法的框图。该方法包括在1210提供基板，在1220使半导体结构至少包括在半导体结构中形成载流子沟道的III-N沟道层。覆盖层的材料具有比III-N沟道层中的材料的带隙更高的带隙。根据一些实施方式，可以采用各种方法来生长和形成覆盖层或沟道层，所述方法包括但不限于化学气相沉积(CVD)、金属有机化学气相沉积(MOCVD)、分子束外延(MBE)、金属有机气相外延(MOVPE)和等离子体增强化学气相沉积(PECVD)以及微波等离子体沉积系统。
该方法在1230中通过湿蚀刻或干蚀刻限定晶体管的有源区，并在1240中使用电子束沉积、焦耳蒸发、化学气相沉积和溅射工艺中的一种或组合来形成电连接到载流子沟道的源极和漏极。然后将样品在真空或N2环境中以>800℃的温度进行退火来形成欧姆接触。该方法在1250中例如通过沉积硬掩模和干蚀刻来形成鳍结构，并且在1260中例如通过沉积金属然后空白蚀刻来形成侧壁栅极。
该方法还包括在1270中例如使用原子层沉积(ALD)、化学气相沉积(CVD)、金属有机化学气相沉积(MOCVD)、分子束外延(MBE)、金属有机气相外延(MOVPE)、等离子体增强化学气相沉积(PECVD)和微波等离子体沉积中的一种或组合来沉积间隔介电层。然后，该方法通过空白蚀刻使间隔层平坦化。
进一步，该方法还包括在1280中形成用于栅极的金属层。可以使用光刻→金属沉积→剥离以及金属沉积→光刻→蚀刻中的一种或组合进行该金属层的形成。这里，可以使用包括但不限于照相光刻、电子束光刻来执行光刻。可以使用电子束沉积、焦耳蒸发、化学气相沉积和溅射工艺中的一种或组合来进行金属沉积。

Claims (11)

1.一种高电子迁移率晶体管，该高电子迁移率晶体管包括：
一组电极，所述一组电极包括源极、漏极、顶栅极和两个侧栅极；以及
半导体结构，该半导体结构具有在所述源极和所述漏极之间延伸的鳍，其中，所述顶栅极布置在所述鳍的顶部上，其中，所述侧栅极距所述顶栅极一定距离布置在所述鳍的相对侧壁上，其中，所述半导体结构包括由位于所述顶栅极下方的覆盖层和布置在所述覆盖层下方以用于提供导电性的沟道层形成的异质结构，其中，所述覆盖层包括氮化物基半导体材料，以使所述异质结构能够在所述源极和所述漏极之间形成载流子沟道，从而在所述覆盖层和所述沟道层的界面处形成二维电子气2-DEG，其中，所述高电子迁移率晶体管被配置为使得相对于所述源极施加到所述顶栅极的电压调制所述源极与所述漏极之间的所述载流子沟道的导电率，并且使得相对于所述源极施加到所述侧栅极的电压调制所述晶体管的所述顶栅极的阈值电压，其中，所述高电子迁移率晶体管被配置为响应于施加到所述侧栅极的负偏压的增加而增加所述顶栅极的阈值电压；
所述鳍的宽度小于400nm，
所述高电子迁移率晶体管被配置为当所述顶栅极的阈值电压为正并且需要负阈值电压时，所述侧栅极被施加正电压；否则
当所述顶栅极的阈值电压为负并且需要正阈值电压时，所述侧栅极被施加负电压。
2.根据权利要求1所述的晶体管，其中，所述侧栅极由半导体材料制成。
3.根据权利要求2所述的晶体管，其中，所述侧栅极的所述半导体材料是p掺杂半导体。
4.根据权利要求1所述的晶体管，其中，所述侧栅极具有L形，其中，所述L形的第一腿部布置在所述鳍的所述侧壁上，并且其中，所述L形的第二腿部基本垂直于所述第一腿部。
5.根据权利要求1所述的晶体管，该晶体管还包括：
介电层，该介电层被布置在所述顶栅极与所述鳍的顶表面之间、或者在所述侧栅极与所述鳍的所述侧壁之间、或者这两个位置的组合。
6.根据权利要求1所述的晶体管，其中，所述半导体结构包括AlxInyGa1-x-yN。
7.一种用于控制高电子迁移率晶体管的方法，该高电子迁移率晶体管包括具有在所述晶体管的源极和漏极之间延伸的鳍的半导体结构，其中，所述晶体管的顶栅极布置在所述鳍的顶部上，并且所述晶体管的两个侧栅极距所述顶栅极一定距离布置在所述鳍的相对侧壁上，其中，所述半导体结构包括由位于所述顶栅极下方的覆盖层和布置在所述覆盖层下方以用于提供导电性的沟道层形成的异质结构，其中，所述覆盖层包括氮化物基半导体材料，以使所述异质结构能够在所述源极和所述漏极之间形成载流子沟道，从而在所述覆盖层和所述沟道层的界面处形成二维电子气2-DEG，该方法包括以下步骤：
相对于所述源极向所述顶栅极施加电压，以调制所述源极和所述漏极之间的所述载流子沟道的导电率；以及
相对于所述源极向所述侧栅极施加电压，以调制所述晶体管的所述顶栅极的阈值电压，其中，所述方法包括增加施加到所述侧栅极的负偏压，以增加所述顶栅极的阈值电压；
该方法还包括以下步骤：
测量所述顶栅极的阈值电压；
检测相对于所述源极改变所述阈值电压的符号的请求；以及
当所述阈值电压为正并且需要负阈值电压时，向所述侧栅极施加正电压；否则当测量到的所述阈值电压为负并且需要正阈值电压时，向所述侧栅极施加负电压。
8.一种用于制造权利要求1所述的高电子迁移率晶体管的方法，该方法包括以下步骤：
提供基板和半导体结构，该半导体结构包括由覆盖层和具有至少一个载流子沟道的沟道层形成的异质结构，其中，所述覆盖层布置在所述沟道层上方，其中，所述覆盖层包括氮化物基半导体材料，以使得能够在所述覆盖层和所述沟道层的界面处形成二维电子气2-DEG；
蚀刻所述半导体结构以限定所述晶体管的有源区；
通过金属沉积和退火形成源极和漏极；
通过干蚀刻和湿蚀刻的组合在所述半导体结构中形成在所述源极和所述漏极之间延伸的宽度小于400nm的鳍；
距顶栅极一定距离，在所述鳍的相对侧壁上沉积两个侧栅极；以及
距所述侧栅极一定距离，在所述覆盖层上方的鳍的顶部上沉积顶金属栅极，其中，所述方法包括将所述高电子迁移率晶体管制造为使得相对于所述源极施加到所述顶栅极的电压调制所述源极与所述漏极之间的所述载流子沟道的导电率，使得相对于所述源极施加到所述侧栅极的电压调制所述晶体管的阈值电压，并且使得所述阈值电压随着施加到所述侧栅极的负偏压的增加而增加。
9.根据权利要求8所述的方法，其中，使用电子束物理气相沉积EBPVD、焦耳蒸发、化学气相沉积和溅射工艺中的一种或组合形成电极。
10.根据权利要求8所述的方法，其中，使用化学气相沉积CVD、金属有机化学气相沉积MOCVD、分子束外延MBE、金属有机气相外延MOVPE、等离子体增强化学气相沉积PECVD和微波等离子体沉积中的一种或组合来形成所述半导体结构。
11.根据权利要求8所述的方法，该方法还包括以下步骤：在所述沟道层下方形成后阻挡层。
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