CN111180436A - Double-layer packaging structure of hybrid integrated circuit and manufacturing method thereof - Google Patents

Double-layer packaging structure of hybrid integrated circuit and manufacturing method thereof Download PDF

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Publication number
CN111180436A
CN111180436A CN202010074415.9A CN202010074415A CN111180436A CN 111180436 A CN111180436 A CN 111180436A CN 202010074415 A CN202010074415 A CN 202010074415A CN 111180436 A CN111180436 A CN 111180436A
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substrate
layer
shell
double
dual
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CN111180436B (en
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许艳军
李秀灵
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BEIJING SUPLET POWER CO LTD
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BEIJING SUPLET POWER CO LTD
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H01L25/162—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits the devices being mounted on two or more different substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • H01L23/043—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having a conductive base as a mounting as well as a lead for the semiconductor body
    • H01L23/045—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having a conductive base as a mounting as well as a lead for the semiconductor body the other leads having an insulating passage through the base
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H01L25/165—Containers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
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  • Manufacturing & Machinery (AREA)
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Abstract

The application provides a double-layer packaging structure of a hybrid integrated circuit and a manufacturing method thereof, the packaging structure comprises a substrate, a double-layer integrated shell and a shell cover plate, wherein the substrate comprises a bottom substrate and an upper substrate, and an electronic component is assembled on the upper surface of the substrate; the double-layer integrated shell comprises a shell base and a double-cavity shell; the bottom substrate is welded on the shell base, and the upper substrate is welded in the upper cavity of the double-cavity shell; the bottom substrate and the upper substrate are connected through pins and connecting wires in a welding mode. This application technical scheme adopts double-deck assembly structure and double-deck integration shell, both can promote the packing density of product by a wide margin, and the miniaturized design of electronic components of being convenient for can ensure the structural strength of product again, satisfies the reliability demand of high-grade product.

Description

Double-layer packaging structure of hybrid integrated circuit and manufacturing method thereof
Technical Field
The present disclosure relates to the field of hybrid integrated circuit packaging technologies, and in particular, to a dual-layer package structure of a hybrid integrated circuit and a method for manufacturing the same.
Background
The hybrid integrated circuit belongs to an air-tight packaging device, high-purity nitrogen is sealed inside the hybrid integrated circuit, the hybrid integrated circuit is used for ensuring that fragile components such as a bare chip and a bonding wire in the product are completely isolated from an external unfavorable environment, and the hybrid integrated circuit has the characteristics of wide working temperature range, good environmental adaptability, high reliability and the like, and is widely applied to the field with high reliability requirements.
The packaging structure of the thick film hybrid integrated circuit in the prior art, as shown in fig. 1, adopts an all-metal airtight packaging shell 11; a thick film forming substrate 12 mounted on the base of the package case 11; the thick film substrate 12 has a wiring layer 13 on the surface thereof, and a chip 14, a chip element 15, a magnetic inductor, a transformer 16, and the like are mounted thereon and connected by a bonding wire 17 and a bonding wire 18 to constitute a circuit package structure having a specific function.
As shown in fig. 1, the hybrid integrated circuit of the prior art is a typical single-layer package structure, the packaging density of the components in the package structure is low, and the thick-film substrate with a large area is required, which is not favorable for the miniaturization design of the electronic components.
Disclosure of Invention
In order to solve the above problems, the present application provides a dual-layer package structure of a hybrid integrated circuit and a manufacturing method thereof, which can greatly increase the packaging density of the hybrid integrated circuit product, facilitate the miniaturization design of electronic components, ensure the structural strength of the electronic components, and meet the reliability requirements of high-grade electronic components.
In order to achieve the above purpose, the present application provides the following technical solutions:
a dual layer package structure for a hybrid integrated circuit, the dual layer package structure comprising: the base plate, the double-layer integrated shell and the shell cover plate;
the substrate comprises a bottom substrate and an upper substrate, and electronic components are assembled on the upper surfaces of the bottom substrate and the upper substrate;
the double-layer integrated shell comprises a shell base and a double-cavity shell;
the double-cavity shell comprises an upper cavity and a lower cavity, and the upper cavity and the lower cavity are separated by a partition plate;
the bottom substrate is welded on the outer shell base, and the upper substrate is welded on the partition plate on one side of the upper cavity of the double-cavity shell;
the bottom substrate and the upper substrate are connected through pins and connecting wires in a welding mode.
Preferably, the outer shell base and the double-cavity shell are welded through energy storage welding to form an integrated structure.
Preferably, the bottom substrate, the dual-cavity housing and the upper substrate respectively comprise a partition through hole or a substrate through hole for the pin or the connecting wire to pass through;
the pins penetrate through the substrate through holes of the lower substrate, the partition plate through holes of the double-cavity shell and the substrate through holes of the upper substrate from bottom to top and are welded and connected with surface pads between the upper substrate and the lower substrate;
the bottom of the connecting wire is welded on the surface of the lower-layer substrate, and the connecting wire penetrates through the through hole of the partition plate and the through hole of the upper-layer substrate from bottom to top and is then welded and connected with the surface welding disc of the upper-layer substrate and the surface welding disc of the lower-layer substrate.
Preferably, the double-layer integrated shell is made of metal, the inner plating layer of the double-layer integrated shell is made of nickel, and the outer plating layer of the double-layer integrated shell is made of gold.
Preferably, the base material of the substrate is ceramic.
Preferably, the thickness of the base of the shell is set between 0.5mm and 2 mm.
Preferably, the wall of the double-cavity shell and the thickness of the partition plate are set between 0.5mm and 1.5 mm.
Preferably, a first energy storage welding area is distributed on the edge of the base of the outer shell, and a second energy storage welding area is distributed on the edge of the bottom of the double-cavity shell.
Preferably, the width of the energy storage welding area 1 is between 1.5mm and 2.5mm, and the width of the energy storage welding area 2 is between 1mm and 2 mm.
A manufacturing method for manufacturing the two-layer package structure as described above, the manufacturing method comprising:
providing a substrate, a double-layer integrated shell and a shell cover plate;
assembling the bottom substrate and the upper substrate;
welding the shell base and the double-cavity shell through an energy storage welding process to form an integrated shell structure;
completing the welding connection of the upper layer substrate, the pins and the connecting wires, and locally cleaning welding spots;
and (5) performing parallel seam welding to finish the sealing of the product.
According to the packaging structure, the double-layer integrated shell is adopted, the structural strength of the shell is high, and compared with a traditional single-layer packaged hybrid integrated circuit, the packaging structure can greatly improve the packaging density of products, can ensure the structural strength of electronic components, and meets the reliability requirement of high-grade electronic components.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly introduced below, it is obvious that the drawings in the following description are only embodiments of the present application, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.
FIG. 1 is a schematic diagram of a hybrid integrated circuit package structure in the prior art;
fig. 2 is a schematic structural diagram of a hybrid integrated circuit dual-layer package structure according to an embodiment of the present disclosure;
fig. 3 is a schematic cross-sectional view of a double-layer integrated housing according to an embodiment of the present disclosure;
fig. 4 is a schematic cross-sectional view of a base of a double-layer integrated housing according to an embodiment of the present application;
FIG. 5 is a schematic cross-sectional view of a dual-integrated-shell dual-chamber housing according to an embodiment of the present application;
fig. 6 is a flowchart illustrating a method for manufacturing a hybrid integrated circuit dual-layer package structure according to an embodiment of the present disclosure.
The names of the components are described as follows:
11-package housing base, 12-thick film forming substrate, 13-wiring layer, 14-chip, 15-chip component, 16-large size component, 17-bonding wire, 18-welding lead, 21-double layer integrated housing, 22-insulator, 23-pin, 24-housing cover plate, 25-partition plate, 26-partition plate through hole, 27-upper substrate, 28-substrate through hole, 29-bottom substrate, 30-connecting lead; 31-soldering tin; 32-energy storage welding zone 1; 33-energy storage welding zone 2; 41-housing base; 51-Dual chamber housing.
Detailed Description
As shown in fig. 1, the prior art thick film hybrid integrated circuit is a typical single layer assembly structure with relatively low internal assembly density. Meanwhile, in the prior art, the wiring line width, the wiring line pitch, the component assembly pitch value and the like on the surface of the thick film forming substrate 12 are all close to the lower limit values of the thick film forming process and the component assembly process, so that the component assembly density in the packaging structure is not likely to be further and greatly improved under the condition that the structure of the prior art is not changed. Therefore, under the current trend of miniaturization and light-weight development of electronic components, how to greatly increase the packaging density of components in the hybrid integrated circuit package structure is beneficial to the miniaturization design of the electronic components, and the problem to be solved in the field of hybrid integrated circuits is already urgent.
It should be noted that the applicant has proposed a three-dimensional package structure of a hybrid integrated circuit in the prior art. The three-dimensional packaging structure is different from the three-dimensional packaging structure provided by the prior art in packaging structure and manufacturing method, and the generated beneficial effects are obviously different. Specifically, the packaging structure and the manufacturing method are different: the three-dimensional packaging structure proposed in the prior art adopts a support assembly structure, and the three-dimensional packaging of a product is realized mainly in a layer-by-layer assembly mode on a support; the double-layer integrated shell assembly structure is characterized in that the double-layer integrated shell assembly structure is formed by firstly respectively assembling two parts (a base and a double-cavity shell) of the double-layer integrated shell, then welding the two parts to form the double-layer integrated shell through energy storage welding, and meanwhile, a double-layer packaging structure is formed. The beneficial effects are obviously different: the three-dimensional packaging structure provided by the application can be used for packaging three-dimensional products with 2 layers or more than 2 layers, and the double-layer packaging structure provided by the application can only be used for packaging products with 2 layers; the double-layer packaging structure provided by the application adopts the integrated metal shell, the structural strength of the shell is high, the upper layer of the shell can also be used for assembling large-size and heavy components, the welding strength of the support and the bearing plate is limited, the weight of the components assembled on the heavy plate is also limited, usually large-size and heavy components are assembled on the bottom layer of the shell, and only small-size and light components are assembled on the bearing plate; the support step of the interior of the product of the three-dimensional packaging structure is provided to occupy a certain height, so that the height of the product packaged by the three-dimensional packaging structure is lower and the space utilization rate in the vertical direction is higher compared with the three-dimensional packaging structure provided by the prior art under the condition of the same packaging layer number (2 layers).
In order to make the aforementioned objects, features and advantages of the present application more comprehensible, the present application is described in further detail with reference to the accompanying drawings and the detailed description.
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
Referring to fig. 2, an embodiment of the present application provides a structural schematic diagram of a hybrid integrated circuit dual-layer package structure, where the dual-layer package structure includes: a base plate, a double-layer integrated housing 21, and a housing cover plate 24.
The substrate comprises a bottom substrate 29 and an upper substrate 27, and electronic components are assembled on the upper surfaces of the bottom substrate 29 and the upper substrate 27.
A typical electronic component mounted on the upper surface of a substrate includes: chip components 15, such as resistors or capacitors mounted on a chip, chips 14, such as bare integrated circuit chips or power semiconductor chips, and large-sized components 16, such as inductors or transformers.
Referring to fig. 3, the double-integrated housing 21 includes a housing base 41 and a double-chamber housing 51.
Referring to fig. 5, the dual chamber housing 51 includes an upper chamber and a lower chamber separated by a partition 25.
The bottom substrate 29 is welded to the housing base 41, and the upper substrate 27 is welded to the upper chamber of the double chamber housing 51.
It should be noted that, for the dual-layer package structure of the present application, the soldering of the bottom substrate 29 and the housing base 41, the soldering of the top substrate 27 and the dual-cavity housing 51, and the soldering of the electronic components and the substrate surface can use the mature soldering process and process materials of the existing hybrid integrated circuit, i.e. the reflow soldering process and the solders such as 62Sn/36Pb/2Ag, 63Sn/37Pb, etc. of the prior art can be used.
Referring to fig. 3 and fig. 4, fig. 3 is a schematic cross-sectional structure view of a double-layer integrated housing provided in an embodiment of the present application, and fig. 4 is a schematic cross-sectional view of a package housing base 41 provided in the embodiment of the present application. The package housing comprises a housing base 41, a double-chamber housing 51 and a housing cover 24.
In fig. 3, the housing base 41 and the dual-chamber housing 51 are welded by stored energy welding to form an integrated structure.
In summary, in the dual-layer package structure shown in fig. 2, the bottom substrate 29 is directly welded to the bottom of the package housing 21, the upper substrate 27 is welded to the partition 25 of the dual-cavity housing 51, the partition 25 and the housing cavity are integrated, so that the structure strength is high, the reliability requirements on mechanical strength such as vibration and impact of the product can be met, and the long-term reliability working requirements related to aging and temperature impact can be met.
The bottom substrate 29 and the upper substrate 27 are soldered and connected by means of pins 23, connecting wires 30, and the like.
Referring to the dual-layer package structure of fig. 2, the bottom substrate 29, the dual-cavity housing 51, and the top substrate 27 include a partition through hole 26 or a substrate through hole 28 for the pin 23 or the connecting wire 30 to pass through. The pins 23 pass through the substrate through holes 28 of the lower substrate 29, the partition plate through holes 26 of the double-cavity housing and the substrate through holes 28 of the upper substrate 27 from bottom to top, and then are soldered to surface pads between the upper and lower substrates. The bottom of the connecting wire 30 is soldered to the surface of the lower substrate 29, and after passing through the spacer through-hole 26 and the substrate through-hole 28 of the upper substrate 27 from the bottom up, the surface pads of the upper and lower substrates are soldered.
The double-layer integrated shell 21 is made of metal, preferably, the inner plating layer is made of nickel, and the outer plating layer is made of gold.
Referring to fig. 4 and 5, the dual chamber housing of fig. 5 includes a sidewall and a partition 25, both made of metal. As shown in fig. 5, through holes 26 of different sizes are designed in the partition 25, and the electrical interconnection lines 30 and pins 23 between the upper and lower substrates pass through the through holes 26 to electrically interconnect the upper and lower substrates.
In fig. 4, the housing base 41 includes a metal base 11, an insulator 22, pins 23, and energy storage lands 32. The metal base 11 is used for welding the lower substrate 29, the pins 23 are used for welding the upper substrate 27 and the lower substrate 29 to form electrical interconnection, the insulators 22 enable the insulating property to be formed between the shell base and the pins, and the energy storage welding areas 32 are used for welding the double-cavity shell 41 to form the integrated shell 21.
The base material of the substrate is ceramic, and preferably, the substrate can be manufactured by a thick film forming process, a thin film forming process, a high-temperature co-fired ceramic process and a low-temperature co-fired ceramic process.
It is to be noted that the thick film forming process, the thin film forming process, the high temperature co-fired ceramic process and the low temperature co-fired ceramic process are all mature processes in the industry. The bottom substrate 29 and the upper substrate 27 have large-area metal pads at the bottom for soldering the substrates to the bottom of the package housing 11 and the surface of the partition 25, respectively. The bottom substrate 29 and the upper substrate 27 are provided with wiring layers and surface pads on their upper surfaces for mounting electronic components. The edge of the base of the shell is distributed with a first energy storage welding area, and the edge of the bottom of the double-cavity shell is distributed with a second energy storage welding area. And the width of the energy storage welding area 1 is set between 1.5mm and 2.5mm, and the width of the energy storage welding area 2 is set between 1mm and 2 mm.
In the embodiment of the application, the thickness of the shell base is set between 0.5mm and 2 mm; the shell wall and the partition plate of the double-cavity shell are 0.5 mm-1.5 mm in thickness.
This application packaging structure has adopted double-deck integration shell, and shell structural strength is high, compares in the hybrid integrated circuit of traditional individual layer encapsulation, and the packaging structure of this application not only can promote product packaging density by a wide margin, and can ensure electronic components's structural strength, satisfies high-grade electronic components's reliability demand. Meanwhile, the packaging technology used in the product assembly is mature technology, the operation is simple, the reliability is high, and the mass production of the product is high.
The present application further provides a manufacturing method for manufacturing the package structure described in any one of the above embodiments, and fig. 6 is a schematic flow chart of a process method provided in the present application, where the manufacturing method includes:
step S01: providing a bottom substrate 29, an upper substrate 27, a package housing base 41, a dual-chamber housing 51, and a housing cover 24;
step S02: completing the assembly of the lower substrate 29 and completing the assembly of the upper substrate 27;
the assembly of the lower substrate 29 specifically includes: completing the welding of the lower substrate 29 with the package housing base 41 and the surface components of the lower substrate 29; completing the welding connection between the surface bonding pad of the lower substrate 29 and the pin 23; completing welding cleaning; and completing other assembly of the surface components of the lower substrate 29, such as bonding, magnetic element bonding assembly, manual welding of enameled wires and the like.
The assembly of the upper substrate 27 specifically includes: welding the upper substrate 27 and the packaging double-cavity shell partition plate 25 is completed; completing the welding of the surface component of the upper substrate 27; completing welding cleaning; and completing other assembly of the surface components of the upper substrate 27, such as chip bonding, bonding and the like.
Step S03: the packaging shell base 41 and the packaging double-cavity shell 51 are welded together through an energy storage welding process to form an integrated shell and double-layer packaging structure.
Step S04: the upper substrate 27 is connected with the pins 23 and the connecting wires 30 by welding;
the assembly of this step specifically includes: soldering tin 31 is adopted to solder the surface bonding pad of the upper substrate 27, the pin 23 and the connecting lead 30; and locally cleaning the welding spot.
Step S05: and (5) performing parallel seam welding to finish the sealing of the product.
This application packaging structure has adopted double-deck integration shell, and shell structural strength is high, compares in the hybrid integrated circuit of traditional individual layer encapsulation, and the packaging structure of this application not only can promote product packaging density by a wide margin, and can ensure electronic components's structural strength, satisfies high-grade electronic components's reliability demand. Meanwhile, the packaging technology used in the product assembly is mature technology, the operation is simple, the reliability is high, and the mass production of the product is high.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the application. Thus, the present application is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims (10)

1. A dual layer package structure of a hybrid integrated circuit, the dual layer package structure comprising: the base plate, the double-layer integrated shell and the shell cover plate;
the substrate comprises a bottom substrate and an upper substrate, and electronic components are assembled on the upper surfaces of the bottom substrate and the upper substrate;
the double-layer integrated shell comprises a shell base and a double-cavity shell;
the double-cavity shell comprises an upper cavity and a lower cavity, and the upper cavity and the lower cavity are separated by a partition plate;
the bottom substrate is welded on the outer shell base, and the upper substrate is welded on the partition plate on one side of the upper cavity of the double-cavity shell;
the bottom substrate and the upper substrate are connected through pins and connecting wires in a welding mode.
2. The dual layer package structure of claim 1, wherein the housing base and the dual chamber housing are welded by energy storage welding to form an integral structure.
3. The dual-layer package structure of claim 1, wherein the bottom substrate, the dual-cavity housing and the upper substrate respectively comprise a partition through hole or a substrate through hole for the pin or the connection wire to pass through;
the pins penetrate through the substrate through holes of the lower substrate, the partition plate through holes of the double-cavity shell and the substrate through holes of the upper substrate from bottom to top and are welded and connected with surface pads between the upper substrate and the lower substrate;
the bottom of the connecting wire is welded on the surface of the lower-layer substrate, and the connecting wire penetrates through the through hole of the partition plate and the through hole of the upper-layer substrate from bottom to top and is then welded and connected with the surface welding disc of the upper-layer substrate and the surface welding disc of the lower-layer substrate.
4. The dual-layer package structure of claim 1, wherein the dual-layer integrated housing is made of metal, the inner plating layer of the dual-layer integrated housing is made of nickel, and the outer plating layer of the dual-layer integrated housing is made of gold.
5. The dual-layer package structure of claim 1, wherein the substrate material of the substrate is ceramic.
6. The dual layer encapsulation structure of claim 1, wherein the thickness of the housing base is set between 0.5mm and 2 mm.
7. The dual-layer encapsulation structure according to claim 1, wherein the wall of the dual-cavity housing and the thickness of the partition are set between 0.5mm and 1.5 mm.
8. The dual layer package structure of claim 1, wherein a first energy storage welding area is distributed on an edge of the base of the housing, and a second energy storage welding area is distributed on an edge of the bottom of the dual chamber housing.
9. The dual-layer package structure as claimed in claim 8, wherein the width of the energy storage pad 1 is between 1.5mm and 2.5mm, and the width of the energy storage pad 2 is between 1mm and 2 mm.
10. A method for manufacturing a two-layer package structure according to any one of claims 1 to 9, wherein the method comprises:
providing a substrate, a double-layer integrated shell and a shell cover plate;
assembling the bottom substrate and the upper substrate;
welding the shell base and the double-cavity shell through an energy storage welding process to form an integrated shell structure;
completing the welding connection of the upper layer substrate, the pins and the connecting wires, and locally cleaning welding spots;
and (5) performing parallel seam welding to finish the sealing of the product.
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