CN109637980A - A kind of ceramic flat surface pad array package casing and processing method - Google Patents
A kind of ceramic flat surface pad array package casing and processing method Download PDFInfo
- Publication number
- CN109637980A CN109637980A CN201811271088.5A CN201811271088A CN109637980A CN 109637980 A CN109637980 A CN 109637980A CN 201811271088 A CN201811271088 A CN 201811271088A CN 109637980 A CN109637980 A CN 109637980A
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- ceramic
- flat surface
- package casing
- array package
- pad array
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/02—Containers; Seals
- H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
- H01L23/053—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4803—Insulating or insulated parts, e.g. mountings, containers, diamond heatsinks
- H01L21/4807—Ceramic parts
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/02—Containers; Seals
- H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
- H01L23/053—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body
- H01L23/055—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body the leads having a passage through the base
Abstract
The invention discloses a kind of ceramic flat surface pad array package casing and processing methods, using the design structure mutually compatible with BGA/PGA installation mainboard；Hollow out and mating with pad array in the middle part of positioning module, can provide positioning in shell and mainboard installation process for the solder ball of thawing；Transmission line by surface connecting line, it is interior bury connecting line and inter-level vias is constituted, provide electric power and signal input/output for enclosed inside chip and circuit；Ceramic peripheral frame and metal sealing frame constitute subsequent chip and circuit installation space, and metal sealing frame upper surface can be in the subsequent structure for carrying out Leakless sealing with metal cover board.Shell is processed using high-temperature co-fired ceramics technology and electric plating method, is had processing method simple and is reduced the low usage amount of Board level packaging process lead, mounting height, light-weight, high mechanical strength, stable chemical performance, excellent electrical properties and high reliability.
Description
Technical field
The present invention relates to a kind of ceramic flat surface pad array package casing and processing methods, belong to microelectronics Packaging field.
Background technique
PBGA (plastic ball grid array encapsulation), CBGA (ceramic ball grid array package), CPGA (ceramic pin grid array package)
It is melted when passing through reflow welding using the soldered ball or welding column that are located at its package bottom with TBGA (carrier band shape BGA Package), with
Pad on substrate forms connection, eliminates same flatness and warpage due to caused by pin problem in fine distant element and asks
Topic, ensure that the same flatness of pin, while soldered ball has the function of self alignment function and self-compensating after dissolving, and have envelope
Fill that area is small, the feature more than number of pins, micro process/controller needed for the smart electronics such as movement, communication, calculating equipment,
The fields such as ASIC, CPU, SMPS, memory are widely applied.As electronic component increasingly tends to high capacity and high speed, compel
It highly necessary asks and provides signal to its electronic circuit, the circuit of power supply miniaturises, multi-functional and high reliability.Ceramics weldering
Disk array package casing (CLGA) replaces PBGA (plastic ball grid array encapsulation), CBGA (ceramic ball grid array envelope with bottom Pad
Dress), the soldered ball and capillary of CPGA (ceramic pin grid array package) and TBGA (carrying shape BGA Package) outer casing bottom, not only
Reduce the usage amount of Board level packaging process lead, and mounting height reduces, weight saving；Avoiding ball bar/needle grid solder joint can
By property problem.
Summary of the invention
Goal of the invention: the present invention proposes a kind of ceramic flat surface pad array package casing and processing method, by using position
The ball impact mainboard welding effect in the integrated positioning module of its package bottom avoids solder.
Technical solution: the present invention discloses a kind of ceramic flat surface pad array package casing, and the pottery of pad is had including bottom
Porcelain pedestal, the bottom of the ceramic base are equipped with positioning module, which is adapted with installation mainboard.
The ceramic base is the hollow body of one side opening, and bottom outer surface is provided with pad and positioning module, and its
Bottom interior surface is then equipped with the metallization welding section for fixing all kinds of packed elements and provides the biography of power supply and signal for it
Defeated line.
The transmission line include positioned at metallization 2 surface of welding section inner surface connecting line and its extend to metallization
Connecting line is buried in below welding section, further includes the inter-level vias for being connected to pad.
The transmission line connects each metallization welding section according to certain circuit pattern.
The metallization welding section is made of multiple layer metal material, and skin-material is gold, and the second layer material is metallic nickel, nickel
Cobalt or nickel phosphorus, third layer material are tungsten or molybdenum manganese.
The skin-material thickness is in 1.3~5.7um, and for second layer material thickness in 1.3~8.9um, the second layer material is thick
Degree is in 5~30um.
A kind of ceramic flat surface pad array package casing processing method, comprising the following steps:
Array-like is processed on multi-disc aluminium oxide or aluminium nitride ceramic chips using the method for laser boring or mechanical punching
Multiple through-holes；
Metal slurry is injected in the through-hole by mask plate and forms inter-level vias, then using with metallization welding
Area's figure and inner surface connecting line and the interior silk screen for burying connection line graph, Metal slurry is coated in per a piece of through-hole after filling
Ceramic chips surface；
Added on the multi-disc ceramic chips for constituting ceramic base enclosure space using the method for mechanical punching or laser cutting
Work cavity；
It is stacked by multiple ceramic chips of above-mentioned processing, the through-hole of all ceramic chips is all corresponded to each other and is compacted, shape
At the green component of the layer containing interconnecting function；
Above-mentioned superimposed green component is cut into single ceramic raw body from its upper surface with scribing machine；
Metal sealing frame is made according to the size of ceramic base opening；
The Metal slurry airtight welding after metal sealing frame and deposition nickel is realized with solder；
On the metallization welding section of ceramic base, intracavitary welding section, transmission line and metal sealing frame deposited metal nickel layer and
Layer gold.
Ceramic chips have with a thickness of 0.2mm and stablize dielectric constant, excellent mechanical strength and high-temperature stable in the step 1)
Property, and have and match thermal expansion coefficient with GaAs and Si.
Metal nickel layer thickness is 0.4~5.9um in the step 8), layer gold above nickel layer with a thickness of 1.3~
5.7um。
The utility model has the advantages that mounting height reduces, weight saving The present invention reduces the usage amount of Board level packaging process lead；It keeps away
Ball bar/needle grid welding spot reliability problem is exempted from.The shell uses high-temperature co-fired ceramics technology, and electric plating method is processed,
Processing method is simple, and product has high mechanical strength, stable chemical performance, excellent electrical properties and easily meets subsequent chip gold tin
The packaging technologies requirement such as welding and gold wire bonding.
Detailed description of the invention
Fig. 1 is Ceramic shell internal structural schematic diagram of the present invention；
Fig. 2 is ceramic shell structure chart of the present invention；
Fig. 3 is the distribution schematic diagram of through-hole on a piece of ceramic chips of the present invention；
Fig. 4 is the structural schematic diagram of positioning module of the present invention；
Fig. 5 is the ceramic chips that the present invention has multiple cavities structural unit.
Specific embodiment
In the following with reference to the drawings and specific embodiments, the present invention is furture elucidated, it should be understood that these embodiments are merely to illustrate
It the present invention rather than limits the scope of the invention, after the present invention has been read, those skilled in the art are to of the invention each
The modification of kind equivalent form falls within the application range as defined in the appended claims.
As depicted in figs. 1 and 2, present embodiment discloses a kind of ceramic flat surface pad array package casing, outer dimension is
15.0mm × 12.0mm × 3.5mm, internal closed space are 9.0mm × 6.0mm × 2.5mm comprising ceramic base 5, metal
Sealing frame 6 and metal cover board 7.Ceramic base 5 is the hollow body of one side opening, and bottom outer surface is provided with pad 1 and positioning
Mould group 8, and its bottom interior surface is then equipped with the metallization welding section 2 for fixing all kinds of packed elements and provides power supply for it
With the transmission line 3 of signal.Peripheral frame 4 is good by high mechanical strength, chemical-resistance, and the Ceramic manufacturing of excellent insulating property forms.It closes
Gold solder welds together metal sealing frame 6 and metal cover board 7, forms appearance by peripheral frame 4, metal cover board 7 and metal sealing frame 6
Receive the enclosure spaces of all kinds of packed chip assemblies and passive device.Since the present embodiment discloses a kind of second level package, institute
With packed element, there are also other passive elements other than chip assembly.
5 bottom interior surface of ceramic base is equipped with multiple metallization welding sections 2, and the metallization welding section 2 is by multilayer gold
Belong to material to constitute, skin-material is gold, and the second layer material is metallic nickel, nickel cobalt or nickel phosphorus, third layer material be tungsten or
Molybdenum manganese, skin-material thickness is in 1.3~5.7um, and second layer material thickness is in 1.3~8.9um, and second layer material thickness is 5
~30um.Metallization welding section 2 is for welding the elements such as chip, capacitor, for internal packed chip assembly and passive member
Part provides mechanical support.It is also interior between each metallization welding section 2 to have buried corresponding transmission line 3 for each metallization welding section 2
It is connected according to certain circuit pattern.Transmission line 3 includes the inner surface connecting line positioned at metallization 2 surface of welding section, with
And extend to the interior of 2 lower section of metallization welding section and bury connecting line, it further include the inter-level vias for being connected to pad 1.
Quantity, size and the adjacent pad spacing of pad 1 all with mainboard pad to be mounted is completely compatible.Outside pad
Portion is equipped with positioning module 8 and passes through mechanical punching, laser cutting or silk-screen printing using nonmetallic materials such as glass or ceramics
And entirety is formed with ceramic base 5 through subsequent multi-layer ceramic technology and plating technic processing.8 height of positioning module 0.01~
0.25mm provides the effect of positioning when being welded to mainboard for subsequent package casing, because pad 1 is welded direct on mainboard,
The missing solder rolled, on adhesion even part pad occurs on mainboard for the easy pilling of its solder.And positioning module 8 avoids weldering
Stream is dynamic to lead to the problem of bridge joint, solder adhesion roll between missing solder or adjacent pad between shell pad and mainboard, just
In installing and using, reliability is improved.
A kind of ceramic flat surface pad array package casing and processing method, comprising the following steps:
1) using the method for laser boring or mechanical punching in multi-disc with a thickness of 0.2mm, have and stablize dielectric constant, excellent
Good mechanical strength and high-temperature stability, and there is the aluminium oxide or aluminium nitride ceramic chips of the thermal expansion coefficient that matches with GaAs and Si
Upper processing aperture is 0.2mm, at multiple through-holes of array-like, adjacent through-holes spacing 0.2-1.0mm, the arrangement of through-hole such as Fig. 3 institute
Show, every layer of through-hole arrangement is different according to the respectively interior design for burying connecting line.The thermal expansion coefficient of the ceramic chips is 6.7x10-6/
DEG C, and the thermal expansion coefficient of GaAs is 6.5x10-6/ DEG C, the thermal expansion coefficient of Si is 4.4x10-6/ DEG C, it is seen that the heat of three is swollen
Swollen coefficient is on the same order of magnitude.All green chip sizes are identical.
2) Metal slurry is injected in the through-hole by mask plate and forms inter-level vias, then using with metallization weldering
Area's figure and inner surface connecting line and the interior silk screen for burying connection line graph are connect, the Metal slurry of 5~30um thickness is coated in every
A piece of through-hole filled aluminium oxide ceramic chips surface.Since transmission line had both included inner surface connecting line, further include in bury connection
Line and inter-level vias, so the Metal slurry pattern and different, some ceramic chips tables that are coated per a piece of ceramic chips surface
Face coating be surface connecting line, have plenty of in bury connecting line, some haves both at the same time.The positioning module is underlying metalization weldering
Glass or the ceramics etc. in area are connect, the non-metallic material bed of material to be formed are deposited by silk-screen printing, as shown in Figure 4.
3) using the method for mechanical punching or laser cutting on the multi-disc ceramic chips for constituting ceramic base enclosure space
Process chamber.The ceramic base eventually formed is formed by stacking by multi-disc ceramic chips, all constitutes ceramic bottom per a piece of ceramic chips
One layer of seat.Undermost ceramic chips are not processed cavity.And according to design, those form ceramic base enclosure space
The middle section of ceramic chips is processed to cavity cavity.And all contain multiple units on every ceramic chips, so really in life
A plurality of cavities cavity is processed on tile, as shown in Figure 5.
4) multiple ceramic chips Jing Guo above-mentioned processing stack, and the through-hole of all ceramic chips is all corresponded to each other and is compacted,
Form the green component of the layer containing interconnecting function.Per all having formd inner surface connecting line on a piece of ceramic chips and interior buried connection
Line, and the interconnection of interlayer can be formed by inter-level vias.Depending on specific superposition ceramic chips quantity is needed according to concrete application.
5) above-mentioned superimposed green component is cut into single ceramic raw body from its upper surface with scribing machine, because of green group
Part face contains multiple ceramic raw bodies.Then multiple ceramic raw bodies after cutting are carried out height in nitrogen and hydrogen mixture atmosphere sintering furnace
Temperature sintering, formation high mechanical strength, electrical property and chemical property are excellent, have the ceramic base of regulation shape.Pottery at this time
Porcelain base bottom outer surface is the planar array pad with positioning module.
6) metal sealing frame is made according to the size of ceramic base opening.Protective atmosphere is used again, and annealing is eliminated
Metal sealing frame stress in process and hardening.In order to guarantee that the ceramic base in next step and metal sealing frame weld
Used solder has good infiltration and wandering effect to metalization layer in the process, to improve intermetallic connection state,
Deposition thickness is the metallic nickel of 1.0~3.0um at Metal slurry after the sintering for being located at metal sealing frame position.The deposition
Metallic nickel be to improve tungsten perhaps to improve combination of the sealing frame solder on tungsten or molybdenum manganese strong for molybdenum manganese surface state
Degree.
7) under the conditions of air or protective atmosphere, specific heating, heat preservation and temperature lowering curve, metal is realized with solder
Metal slurry airtight welding after sealing frame and deposition nickel.
8) the metallization welding section of ceramic base, on transmission line and metal sealing frame 0.4~5.9um of deposition thickness metal
The layer gold of 1.3~5.7um of nickel layer and thickness, wherein upper epidermis is gold, and bottom is metallic nickel, can meet subsequent gold wire bonding, gold
Tin welding and the needs of protection.The layer gold improves the electric conductivity and oxidation resistent susceptibility of package casing, prevents natural environment
Corrosion, while also improving the weld strength of chip and component and shell, gold wire bonding intensity.The nickel layer prevents nature
Corrosion of the environment to package casing.
Claims (9)
1. a kind of ceramic flat surface pad array package casing, which is characterized in that the ceramic base (5) of pad is had including bottom,
The bottom of the ceramic base (5) is equipped with positioning module (8), which is adapted with installation mainboard.
2. ceramic flat surface pad array package casing according to claim 1, which is characterized in that the ceramic base (5)
For the hollow body of one side opening, bottom outer surface is provided with pad (1) and positioning module (8), and its bottom interior surface is then set
There is the metallization welding section (2) for fixing all kinds of packed elements and provides the transmission line (3) of power supply and signal for it.
3. ceramic flat surface pad array package casing according to claim 2, which is characterized in that transmission line (3) packet
It includes the inner surface connecting line for being located at metallization 2 surface of welding section and it extends to the interior company of burying below metallization welding section (2)
Wiring further includes the inter-level vias for being connected to pad (1).
4. ceramic flat surface pad array package casing according to claim 2, which is characterized in that the transmission line (3) will
Each metallization welding section (2) connects according to certain circuit pattern.
5. ceramic flat surface pad array package casing according to claim 2, which is characterized in that the metallization welding section
(2) it is made of multiple layer metal material, skin-material is gold, and the second layer material is metallic nickel, nickel cobalt or nickel phosphorus, third layer material
It is tungsten or molybdenum manganese.
6. ceramic flat surface pad array package casing according to claim 5, which is characterized in that the skin-material thickness
In 1.3~5.7um, second layer material thickness is in 1.3~8.9um, and second layer material thickness is in 5~30um.
7. a kind of ceramic flat surface pad array package casing processing method, which comprises the following steps:
1) array-like is processed on multi-disc aluminium oxide or aluminium nitride ceramic chips using the method for laser boring or mechanical punching
Multiple through-holes；
2) Metal slurry is injected in the through-hole by mask plate and forms inter-level vias, then using with metallization welding section
Figure and inner surface connecting line and the interior silk screen for burying connection line graph, Metal slurry are coated in filled per a piece of through-hole
Ceramic chips surface；
3) it is processed on the multi-disc ceramic chips for constituting ceramic base enclosure space using the method for mechanical punching or laser cutting
Cavity；
4) multiple ceramic chips Jing Guo above-mentioned processing stack, and the through-hole of all ceramic chips is all corresponded to each other and is compacted, and are formed
The green component of the layer containing interconnecting function；
5) above-mentioned superimposed green component is cut into single ceramic raw body from its upper surface with scribing machine；
6) metal sealing frame is made according to the size of ceramic base opening；
7) the Metal slurry airtight welding after metal sealing frame and deposition nickel is realized with solder；
8) deposited metal nickel layer and gold on the metallization welding section, intracavitary welding section of ceramic base, transmission line and metal sealing frame
Layer.
8. ceramic flat surface pad array package casing processing method according to claim 7, which is characterized in that the step
1) ceramic chips have and stablize dielectric constant, excellent mechanical strength and high-temperature stability with a thickness of 0.2mm in, and have and GaAs
Match thermal expansion coefficient with Si.
9. ceramic flat surface pad array package casing processing method according to claim 7, which is characterized in that the step
8) metal nickel layer thickness is 0.4~5.9um in, and the layer gold above nickel layer is with a thickness of 1.3~5.7um.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811271088.5A CN109637980A (en) | 2018-10-29 | 2018-10-29 | A kind of ceramic flat surface pad array package casing and processing method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811271088.5A CN109637980A (en) | 2018-10-29 | 2018-10-29 | A kind of ceramic flat surface pad array package casing and processing method |
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| Publication Number | Publication Date |
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| CN109637980A true CN109637980A (en) | 2019-04-16 |
Family
ID=66066859
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
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| CN201811271088.5A Pending CN109637980A (en) | 2018-10-29 | 2018-10-29 | A kind of ceramic flat surface pad array package casing and processing method |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111785691A (en) * | 2020-05-13 | 2020-10-16 | 中国电子科技集团公司第五十五研究所 | Radio frequency micro-system three-dimensional packaging shell structure and manufacturing method |
| CN111945202A (en) * | 2020-07-21 | 2020-11-17 | 中国电子科技集团公司第十三研究所 | Blind hole electroplating method for ceramic leadless shell |
| CN114195523A (en) * | 2021-12-21 | 2022-03-18 | 河北中瓷电子科技股份有限公司 | Black aluminum nitride ceramic shell for 3D-sensor and preparation method thereof |
| CN117153789A (en) * | 2023-10-30 | 2023-12-01 | 苏州中航天成电子科技有限公司 | Semiconductor power tube shell of heat sink sealing structure and processing device thereof |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101714543A (en) * | 2009-11-12 | 2010-05-26 | 美新半导体（无锡）有限公司 | Ceramic substrate for three-dimensional packaging of multi-chip system and packaging method thereof |
-
2018
- 2018-10-29 CN CN201811271088.5A patent/CN109637980A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101714543A (en) * | 2009-11-12 | 2010-05-26 | 美新半导体（无锡）有限公司 | Ceramic substrate for three-dimensional packaging of multi-chip system and packaging method thereof |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111785691A (en) * | 2020-05-13 | 2020-10-16 | 中国电子科技集团公司第五十五研究所 | Radio frequency micro-system three-dimensional packaging shell structure and manufacturing method |
| WO2021227240A1 (en) * | 2020-05-13 | 2021-11-18 | 中国电子科技集团公司第五十五研究所 | Three-dimensional packaging housing structure of radio frequency microsystem and manufacturing method |
| CN111785691B (en) * | 2020-05-13 | 2022-03-11 | 中国电子科技集团公司第五十五研究所 | Radio frequency micro-system three-dimensional packaging shell structure and manufacturing method |
| CN111945202A (en) * | 2020-07-21 | 2020-11-17 | 中国电子科技集团公司第十三研究所 | Blind hole electroplating method for ceramic leadless shell |
| CN111945202B (en) * | 2020-07-21 | 2021-10-15 | 中国电子科技集团公司第十三研究所 | Blind hole electroplating method for ceramic leadless shell |
| CN114195523A (en) * | 2021-12-21 | 2022-03-18 | 河北中瓷电子科技股份有限公司 | Black aluminum nitride ceramic shell for 3D-sensor and preparation method thereof |
| CN117153789A (en) * | 2023-10-30 | 2023-12-01 | 苏州中航天成电子科技有限公司 | Semiconductor power tube shell of heat sink sealing structure and processing device thereof |
| CN117153789B (en) * | 2023-10-30 | 2024-01-23 | 苏州中航天成电子科技有限公司 | Semiconductor power tube shell of heat sink sealing structure and processing device thereof |
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