CN111180336A - Low residual voltage surge protection device and manufacturing method thereof - Google Patents
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- CN111180336A CN111180336A CN201911398034.XA CN201911398034A CN111180336A CN 111180336 A CN111180336 A CN 111180336A CN 201911398034 A CN201911398034 A CN 201911398034A CN 111180336 A CN111180336 A CN 111180336A
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
- H01L29/6609—Diodes
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
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- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
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- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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Abstract
The invention discloses a low residual voltage surge protection device and a manufacturing method thereof, belonging to the technical field of power devices and comprising the following steps: a first conductivity type substrate layer; the epitaxial layer of the first conduction type, the doping area of the second conduction type, the doping area of the first conduction type, the protective layer, grow on the upper surface of the epitaxial layer, there are contact holes on the protective layer, the contact hole is used for exposing the doping area of the first conduction type and doping area of the second conduction type; a first metal layer is formed on the upper surface of the protective layer and in the contact hole, and the first metal layer is used for short-circuiting a P-N junction formed by the first conductive type doped region and the second conductive type doped region; has the advantages that: the transient surge voltage is clamped in a lower range to a greater extent.
Description
Technical Field
The invention relates to the technical field of power devices, in particular to a low residual voltage surge protection device and a manufacturing method thereof.
Background
With the continuous progress of science and technology, the battery endurance of consumer electronic products is more and more concerned by consumers, and the longer the battery endurance, the longer the charging time, the larger the charging current must be to realize the quick charging, the higher the output voltage must be, the charging terminal voltage of most electronic products is increased from the original 5V to 9V or 12V, and the charging current is increased to 2A, 2.5A, etc. In the practical application process, the back-end circuit may be damaged by plugging and unplugging operations during charging, external static electricity, and transient burr voltage or surge voltage generated in the circuit system. Therefore, it is a challenging issue to clamp these transient high voltages within a safe voltage range acceptable to the system, and to ensure the stable operation of the back-end circuit.
A TVS (Transient Voltage Suppressor), which is a commonly used high-efficiency surge protection device, can absorb a Transient high surge within a very fast time (sub-nanosecond level), and clamp voltages at two ends to a predetermined value, thereby protecting components of a back-end circuit from being impacted by Transient spike pulses. Therefore, TVS plays a very important role in protecting devices or circuits from static electricity, transient voltages generated when inductive loads are switched, and overvoltage generated by induced lightning.
As shown in fig. 1, in the conventional unidirectional 12V TVS device, a p-type impurity is directly doped on an N-type epitaxial layer to form a p-N junction, and then metal is deposited on the front and back sides to form a unidirectional diode, such TVS devices have a simple structure, and an I-V characteristic curve thereof is shown in fig. 2. While the back-end circuit is usually required to be maintained at a constant voltage, the excessive clamping voltage makes the back-end circuit hard to withstand and burn out.
Disclosure of Invention
According to the problems in the prior art, an n-p-n structure is introduced on the basis of a traditional device, an anode p-n junction is short-circuited, when a high-voltage surge is applied to two ends of the low residual voltage surge protection device, carriers are led out from a p + region after avalanche breakdown of the p-n junction, and a part of carriers are led to an anode through an internal electric field which jumps over the anode p-n junction and are led to the anode through n +, so that the transient surge voltage can be clamped in a lower range in a larger range.
The technical scheme specifically comprises the following steps:
a method for manufacturing a low residual voltage surge protection device comprises the following steps:
step S1, providing a first conductive type substrate;
step S2, growing a first conductivity type epitaxial layer on the substrate;
step S3, forming an oxide layer on the epitaxial layer;
step S4, forming a second conductive type doped region in the epitaxial layer by ion implantation;
step S5, forming a first conductive type doped region in the second conductive type doped region by ion implantation;
step S6, coating a layer of photoresist on the oxide layer, and defining the position of the isolation groove through a photoetching process;
step S7, etching the oxide layer through a dry etching process to expose the epitaxial layer corresponding to the isolation trench;
step S8, removing the photoresist, and etching the epitaxial layer by using the oxide layer as a hard mask to form the isolation groove, wherein the isolation groove is arranged around the second conductive type doped region;
step S9, removing the oxide layer, depositing TEOS on the top layer of the epitaxial layer, and filling the isolation groove with TEOS;
step S10, defining the position of the contact hole through a photoetching process, and removing TEOS in the contact hole through a wet etching process to expose the first conductive type doped region and the second conductive type doped region;
and step S11, depositing a metal layer on the surface of the surge protection device, and thinning the metal layer on the back of the surge protection device.
Preferably, the isolation trench penetrates through the substrate layer and the epitaxial layer.
Preferably, wherein the epitaxial layer is lightly doped.
Preferably, wherein the substrate layer is lightly doped.
Preferably, wherein the first conductive type doped region is heavily doped.
Preferably, wherein the second conductive type doped region is heavily doped.
A low residual voltage surge protection device comprising:
a first conductivity type substrate layer;
the first conductive type epitaxial layer grows on the upper surface of the substrate layer, and a second conductive type doped region is formed on the upper surface of the epitaxial layer;
forming a first conductive type doped region on the upper surface of the second conductive type doped region;
the protective layer grows on the upper surface of the epitaxial layer, a contact hole is formed in the protective layer, and the contact hole is used for exposing the first conduction type doping area and the second conduction type doping area;
a first metal layer is formed on the upper surface of the protective layer and in the contact hole, and the first metal layer is used for short-circuiting a P-N junction formed by the first conductive type doped region and the second conductive type doped region;
and a second metal layer is formed on the lower surface of the first conductive substrate layer.
Preferably, the method further comprises the following steps:
the isolation groove penetrates through the substrate layer and the epitaxial layer, and the isolation groove is arranged around the second conduction type doping area.
Preferably, wherein, the isolation trench is filled with TEOS.
The beneficial effects of the above technical scheme are that:
the device introduces an n-p-n structure on the basis of a traditional device, and simultaneously short-circuits an anode p-n junction, when a high-voltage surge is applied to two ends of the low residual voltage surge protection device, carriers are led out from a p + region after avalanche breakdown of the p-n junction, and a part of carriers jump over a built-in electric field of the anode p-n junction and are led to an anode through n +, so that the transient surge voltage can be clamped in a lower range in the process.
Drawings
FIG. 1 is a schematic structural diagram of a conventional unidirectional 12V TVS device;
FIG. 2 is an I-V characteristic curve of a conventional unidirectional 12V TVS device;
FIG. 3 is a schematic diagram of a low residual voltage surge protection device according to a preferred embodiment of the present invention;
fig. 4-10 are schematic structural diagrams of a method for manufacturing a low residual voltage surge protection device in steps according to a preferred embodiment of the present invention;
fig. 11 is an I-V characteristic curve of a low residual voltage surge protection device in accordance with a preferred embodiment of the present invention;
fig. 12 is a surge diagram of a conventional unidirectional 12V TVS device;
fig. 13 is a surge diagram of a low residual voltage surge protection device in accordance with a preferred embodiment of the present invention;
the reference numerals in the specification denote descriptions:
the epitaxial structure comprises a substrate (10), an epitaxial layer (20), a second conductive type doped region (30), a first conductive type doped region (40), a protective layer (50), an isolation groove (60), a first metal layer (70), a second metal layer (80), an oxidation layer (90) and photoresist (100).
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
It should be noted that the embodiments and features of the embodiments may be combined with each other without conflict.
The invention is further described with reference to the following drawings and specific examples, which are not intended to be limiting.
A method of manufacturing a low residual voltage surge protection device, as shown in fig. 3-10, comprising:
step S1, providing a first conductive type substrate 10;
step S2, growing a first conductive type epitaxial layer 20 on the substrate 10;
step S3, forming an oxide layer 90 on the epitaxial layer 20;
specifically, in the present embodiment, a layer is grown on the first conductive type epitaxial layer 20 by thermal oxidation
Oxide layer 90.
Step S4, forming a second conductive type doped region 30 in the epitaxial layer 20 by ion implantation;
specifically, in this embodiment, a photoresist 100 is coated on the oxide layer 90, a photolithography mask is used to perform photolithography to realize pattern transfer of the second conductive type doped region 30, a window region doped with the second conductive type is defined by a photomask, and then the window region is implanted 1015cm-3Boron concentration, followed by photoresist 100 removal, is then annealed at 1050 c to form second conductivity type doped region 30.
Step S5, forming a first conductive type doped region 40 in the second conductive type doped region 30 by ion implantation;
specifically, in this embodiment, the photoresist 100 is coated again, the pattern transfer of the first conductive type doped region 40 is realized through a photolithography mask, the window of the first conductive type doped region 40 is defined after exposure and development, and then the window is implanted 1016cm-3Arsenic in a concentration, finally passingThe first conductive type doped region 40 is formed by annealing at 1000 c.
Step S6, coating a layer of photoresist 100 on the oxide layer 90, and defining the position of the isolation trench 60 by a photolithography process;
step S7, etching the oxide layer 90 by a dry etching process to expose the epitaxial layer 20 at a position corresponding to the isolation trench 60;
specifically, in the present embodiment, a layer is grown on the surface of the wafer
The oxide layer 90 is formed by defining a deep trench isolation region, i.e., a position corresponding to the isolation trench 60, through a photolithography process, and then dry etching the oxide layer 90 to expose the epitaxial layer 20 corresponding to the isolation trench 60.
Step S8, removing the photoresist 100, and etching the epitaxial layer 20 with the oxide layer 90 as a hard mask to form an isolation trench 60, where the isolation trench 60 is disposed around the second conductive type doped region 30;
specifically, in this embodiment, the oxide layer 90 left after the photoresist stripping is used as a hard mask for etching the isolation trench 60, and then the epitaxial layer 20 is dry etched to obtain the 15um deep trench isolation trench 60.
Step S9, removing the oxide layer 90, and depositing TEOS on the top layer of the epitaxial layer 20 to fill the isolation trench 60 with TEOS;
step S10, defining the position of the contact hole through a photolithography process, and removing TEOS in the contact hole through a wet etching process to expose the first conductive type doping region 40 and the second conductive type doping region 30;
and step S11, depositing a metal layer on the surface of the surge protection device, and thinning the metal layer on the back of the surge protection device.
Specifically, in this embodiment, a first metal layer 70 and a second metal layer 80 are formed on the front and back surfaces of the surge protection device by sputtering deposition, and finally, the second metal layer 80 on the back surface is subjected to thinning and evaporation processes, so as to finally form the low residual voltage surge protection device.
As a preferred implementation mode, the low residual voltage surge protection device disclosed by the invention adopts a deep groove isolation process, on one hand, an n-p-n structure is introduced on the basis of a traditional device, meanwhile, an anode p-n junction is short-circuited, when a high-voltage surge is applied to two ends of the surge protection device, a carrier is led out from a p + region after the p-n junction is subjected to avalanche breakdown, and a part of the carrier is led to an anode through an n + after jumping over a built-in electric field of the anode p-n junction, so that the transient surge voltage can be clamped in a lower range in a larger range in the process; on the other hand, the potential distribution at the edge of the p-n junction can be effectively improved by introducing deep trench isolation at the edge of the surge protection device, so that the IPP is further increased, as shown in fig. 3, which is a schematic structural diagram of the low residual voltage surge protection device, and fig. 11 is an I-V characteristic curve corresponding to the low residual voltage surge protection device.
In the preferred embodiment of the present invention, isolation trenches 60 extend through the substrate 10 layer and the epitaxial layer 20.
In the preferred embodiment of the present invention, the epitaxial layer 20 is lightly doped.
In the preferred embodiment of the present invention, the substrate 10 layer is lightly doped.
In the preferred embodiment of the present invention, the first conductive type doping region 40 is heavily doped.
In the preferred embodiment of the present invention, the second conductive type doping region 30 is heavily doped.
A low residual voltage surge protection device, as shown in fig. 3, comprising:
a first conductivity type substrate 10 layer;
a first conductive type epitaxial layer 20 grown on the upper surface of the substrate 10, wherein a second conductive type doped region 30 is formed on the upper surface of the epitaxial layer 20;
a first conductive type doped region 40 is formed on the upper surface of the second conductive type doped region 30;
a protective layer 50 grown on the upper surface of the epitaxial layer 20, the protective layer 50 having a contact hole for exposing the first conductive type doping region 40 and the second conductive type doping region 30;
a first metal layer 70 is formed on the upper surface of the protective layer 50 and in the contact hole, and the first metal layer 70 short-circuits a P-N junction formed by the first conductive type doped region 40 and the second conductive type doped region 30;
a second metal layer 80 is formed on the lower surface of the first conductive substrate 10 layer.
In a preferred embodiment of the present invention, the method further comprises:
and an isolation trench 60, wherein the isolation trench 60 penetrates through the substrate 10 layer and the epitaxial layer 20, and the isolation trench 60 is disposed around the second conductive type doped region 30.
In the preferred embodiment of the present invention, the isolation trench 60 is filled with TEOS.
Specifically, in the above embodiment, for the same chip area, comparing the performance parameters of the conventional unidirectional 12V TVS device with the performance parameters of the low residual voltage surge protection device of the present invention, an 8/20us surge curve is shown in fig. 12, fig. 12 is a surge diagram of the conventional unidirectional 12V tvvs device, fig. 13 is a surge diagram of the low residual voltage surge protection device, and the comparison data is detailed in the following table:
from the data, it can be seen that the 12V TVS of the low residual voltage surge protection device of the present invention has a residual voltage V under the condition of a high transient surge current IPPCReduced by 4V (IPP 190A), residual pressure VCThe reduction of 14% and the corresponding increase of IPP capability from 190A to 204A by 7%.
The beneficial effects of the above technical scheme are that:
the device introduces an n-p-n structure on the basis of a traditional device, and simultaneously short-circuits an anode p-n junction, when a high-voltage surge is applied to two ends of the low residual voltage surge protection device, carriers are led out from a p + region after avalanche breakdown of the p-n junction, and a part of carriers jump over a built-in electric field of the anode p-n junction and are led to an anode through n +, so that the transient surge voltage can be clamped in a lower range in the process.
While the invention has been described with reference to a preferred embodiment, it will be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit and scope of the invention.
Claims (9)
1. A method for manufacturing a low residual voltage surge protection device is characterized by comprising the following steps:
step S1, providing a first conductive type substrate;
step S2, growing a first conductivity type epitaxial layer on the substrate;
step S3, forming an oxide layer on the epitaxial layer;
step S4, forming a second conductive type doped region in the epitaxial layer by ion implantation;
step S5, forming a first conductive type doped region in the second conductive type doped region by ion implantation;
step S6, coating a layer of photoresist on the oxide layer, and defining the position of the isolation groove through a photoetching process;
step S7, etching the oxide layer through a dry etching process to expose the epitaxial layer corresponding to the isolation trench;
step S8, removing the photoresist, and etching the epitaxial layer by using the oxide layer as a hard mask to form the isolation groove, wherein the isolation groove is arranged around the second conductive type doped region;
step S9, removing the oxide layer, depositing TEOS on the top layer of the epitaxial layer, and filling the isolation groove with TEOS;
step S10, defining the position of the contact hole through a photoetching process, and removing TEOS in the contact hole through a wet etching process to expose the first conductive type doped region and the second conductive type doped region;
and step S11, depositing a metal layer on the surface of the surge protection device, and thinning the metal layer on the back of the surge protection device.
2. The method of manufacturing a low residual voltage surge protection device according to claim 1, wherein said isolation trench penetrates said substrate layer and said epitaxial layer.
3. The method of claim 1, wherein the epitaxial layer is lightly doped.
4. The method of manufacturing a low residual voltage surge protection device according to claim 1, wherein said substrate layer is lightly doped.
5. The method of claim 1, wherein the first conductivity type doped region is heavily doped.
6. The method of claim 1, wherein the second conductivity type doped region is heavily doped.
7. A low residual voltage surge protection device, comprising:
a first conductivity type substrate layer;
the first conductive type epitaxial layer grows on the upper surface of the substrate layer, and a second conductive type doped region is formed on the upper surface of the epitaxial layer;
forming a first conductive type doped region on the upper surface of the second conductive type doped region;
the protective layer grows on the upper surface of the epitaxial layer, a contact hole is formed in the protective layer, and the contact hole is used for exposing the first conduction type doping area and the second conduction type doping area;
a first metal layer is formed on the upper surface of the protective layer and in the contact hole, and the first metal layer is used for short-circuiting a P-N junction formed by the first conductive type doped region and the second conductive type doped region;
and a second metal layer is formed on the lower surface of the first conductive substrate layer.
8. The low residual voltage surge protection device according to claim 7, further comprising:
the isolation groove penetrates through the substrate layer and the epitaxial layer, and the isolation groove is arranged around the second conduction type doping area.
9. The low residual voltage surge protection device according to claim 8, wherein said isolation trench is filled with TEOS.
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| US20190074274A1 (en) * | 2017-03-31 | 2019-03-07 | Alpha And Omega Semiconductor (Cayman) Ltd. | High surge bi-directional transient voltage suppressor |
| US20190157257A1 (en) * | 2017-03-31 | 2019-05-23 | Alpha And Omega Semiconductor (Cayman) Ltd. | High surge transient voltage suppressor |
| CN110504324A (en) * | 2019-08-12 | 2019-11-26 | 电子科技大学 | A kind of high-voltage transient voltage suppressor diode |
| CN110534581A (en) * | 2019-09-06 | 2019-12-03 | 电子科技大学 | A kind of semiconductor devices and its manufacturing method |
| CN110556416A (en) * | 2019-06-29 | 2019-12-10 | 上海长园维安微电子有限公司 | Low-residual-voltage large-surge unidirectional snapback TVS device and manufacturing method thereof |
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| CN110504324A (en) * | 2019-08-12 | 2019-11-26 | 电子科技大学 | A kind of high-voltage transient voltage suppressor diode |
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Application publication date: 20200519 Assignee: Xindao Technology (Wuxi) Co.,Ltd. Assignor: Shanghai Xindao Electronic Technology Co.,Ltd. Contract record no.: X2024980011240 Denomination of invention: A low residual voltage surge protection device and manufacturing method Granted publication date: 20210730 License type: Common License Record date: 20240805 |