CN107256883A - A kind of two-way TVS diode of two-way and preparation method thereof - Google Patents
A kind of two-way TVS diode of two-way and preparation method thereof Download PDFInfo
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- CN107256883A CN107256883A CN201710315387.3A CN201710315387A CN107256883A CN 107256883 A CN107256883 A CN 107256883A CN 201710315387 A CN201710315387 A CN 201710315387A CN 107256883 A CN107256883 A CN 107256883A
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- 238000002360 preparation method Methods 0.000 title claims abstract description 22
- 239000000758 substrate Substances 0.000 claims abstract description 59
- 238000002161 passivation Methods 0.000 claims abstract description 13
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 46
- 238000005516 engineering process Methods 0.000 claims description 31
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 29
- 238000002513 implantation Methods 0.000 claims description 27
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 24
- 239000000377 silicon dioxide Substances 0.000 claims description 23
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 18
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 claims description 18
- 229910052796 boron Inorganic materials 0.000 claims description 18
- 150000002500 ions Chemical class 0.000 claims description 18
- 235000012239 silicon dioxide Nutrition 0.000 claims description 18
- 230000015572 biosynthetic process Effects 0.000 claims description 17
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 claims description 12
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 9
- 229910052698 phosphorus Inorganic materials 0.000 claims description 9
- 239000011574 phosphorus Substances 0.000 claims description 9
- 238000004519 manufacturing process Methods 0.000 claims description 8
- 238000001039 wet etching Methods 0.000 claims description 8
- 238000004026 adhesive bonding Methods 0.000 claims description 6
- 238000005260 corrosion Methods 0.000 claims description 6
- 230000007797 corrosion Effects 0.000 claims description 6
- 238000011161 development Methods 0.000 claims description 6
- 230000008020 evaporation Effects 0.000 claims description 6
- 238000001704 evaporation Methods 0.000 claims description 6
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 6
- 229910052737 gold Inorganic materials 0.000 claims description 6
- 239000010931 gold Substances 0.000 claims description 6
- 238000001259 photo etching Methods 0.000 claims description 6
- 239000004408 titanium dioxide Substances 0.000 claims description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 4
- -1 aluminium copper silicon Chemical group 0.000 claims description 4
- 239000003153 chemical reaction reagent Substances 0.000 claims description 4
- 239000013078 crystal Substances 0.000 claims description 4
- 230000008021 deposition Effects 0.000 claims description 4
- 238000005530 etching Methods 0.000 claims description 4
- 239000007789 gas Substances 0.000 claims description 4
- 238000005468 ion implantation Methods 0.000 claims description 4
- 239000007788 liquid Substances 0.000 claims description 4
- 238000000034 method Methods 0.000 claims description 4
- 230000003647 oxidation Effects 0.000 claims description 4
- 238000007254 oxidation reaction Methods 0.000 claims description 4
- 238000004806 packaging method and process Methods 0.000 claims description 4
- 229920002120 photoresistant polymer Polymers 0.000 claims description 4
- 238000001020 plasma etching Methods 0.000 claims description 4
- 238000007789 sealing Methods 0.000 claims description 4
- 229910052710 silicon Inorganic materials 0.000 claims description 4
- 239000010703 silicon Substances 0.000 claims description 4
- 239000011521 glass Substances 0.000 claims description 3
- DDFHBQSCUXNBSA-UHFFFAOYSA-N 5-(5-carboxythiophen-2-yl)thiophene-2-carboxylic acid Chemical compound S1C(C(=O)O)=CC=C1C1=CC=C(C(O)=O)S1 DDFHBQSCUXNBSA-UHFFFAOYSA-N 0.000 claims description 2
- 238000002156 mixing Methods 0.000 claims 1
- 238000002955 isolation Methods 0.000 abstract description 6
- 239000000203 mixture Substances 0.000 description 3
- AJROUILWTHWZFO-UHFFFAOYSA-N [F-].[NH4+].[Si] Chemical compound [F-].[NH4+].[Si] AJROUILWTHWZFO-UHFFFAOYSA-N 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 240000007594 Oryza sativa Species 0.000 description 1
- 235000007164 Oryza sativa Nutrition 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 229910052681 coesite Inorganic materials 0.000 description 1
- 229910052906 cristobalite Inorganic materials 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 235000009566 rice Nutrition 0.000 description 1
- 229910052682 stishovite Inorganic materials 0.000 description 1
- 230000001052 transient effect Effects 0.000 description 1
- 229910052905 tridymite Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0642—Isolation within the component, i.e. internal isolation
- H01L29/0646—PN junctions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
- H01L29/6609—Diodes
Abstract
The invention discloses two-way TVS diode of a kind of two-way and preparation method thereof.Including：Back electrode, N+ substrates, P epitaxial layers, two p-wells being set up in parallel in P epitaxial layers, the N-type isolated area positioned at p-well both sides, the p-type doped region in each p-well, the n-type doping area in each p-type doped region, the oxide layer positioned at P epi-layer surfaces, the position in each n-type doping area of correspondence is electrically connected, positioned at the passivation layer of front electrode and oxide layer provided with contact hole, two front electrodes by respective contact hole with corresponding n-type doping area in oxide layer.Two TVS diodes are made up of n-type doping region, p-type doped region, p-well and N+ substrates respectively, and distinctive NPN structure makes TVS diode possess the function of bi-directional symmetrical.Distinguished between two TVS by N-type isolation, and also have N-type isolation at the edge of device, this causes the electric leakage of electric leakage in device before two diodes and device edge to be preferably minimized.
Description
Technical field
The present invention relates to technical field of semiconductors, and in particular to a kind of two-way TVS diode of two-way and preparation method thereof.
Background technology
With the development of semiconductor technology, sub-micro has become the prevailing technology of integrated circuit processing.But
Various interface sections can always have various unexpected surges and electrostatic, to ensure the reliability of integrated circuit, with the poles of TVS bis-
Protection class device based on pipe is widely applied to the sensitive port for having produced surge.TVS diode is parallel to and protected
The front end of circuit.Under normal condition, TVS is in that can regard open circuit as in high impedance, perfect condition.When extraneous one transient state of input suddenly
High pressure, TVS utilizes the avalanche breakdown effect of PN junction at once, and impedance is reduced, and the surge that high pressure is produced is shunted by TVS diode.
The voltage at TVS two ends is clamped down on to below maximum clamp voltage simultaneously.After surge disappears, TVS returns to previous high resistant again
Anti- state.
Widely, mobile phone, tablet personal computer, liquid crystal display, camera, set top box have its for TVS diode application
Figure.The upper engineer of tradition application can on the port for the surge being also easy to produce a TVS diode all in parallel, if so
If I/O ports are more, cost is not talked, and also occupies resource on too many pcb board.
The content of the invention
The technical problems to be solved by the invention are：How two-way TVS diode of a kind of two-way and preparation method thereof is provided,
The two-way TVS diode that the present invention is designed using Integration Concept a, device just can protect two-way I/O interfaces.
The present invention is achieved by the following technical programs：
A kind of preparation method of the two-way TVS diode of two-way, comprises the following steps：
（1）N+ substrates are provided；
（2）Silicon dioxide layer and silicon nitride layer are grown successively respectively in the tow sides of the N+ substrates；
（3）The positive silicon dioxide layer and silicon nitride layer of the N+ substrates are removed, retains the titanium dioxide of the N+ substrate backs
Silicon layer and silicon nitride layer are used as back of the body sealing；
（4）A P- epitaxial layers are grown in the front of N+ substrates, then wet etching removes the silica of the N+ substrate backs
Layer and silicon nitride layer；
（5）Boron is carried out in the P- epitaxial layers using mask to adulterate two p-wells to be formed and be set up in parallel；
（6）Pass through phosphorus doping formation N-type isolated area between the P- epitaxial layers both sides of the edge and two p-wells；
（7）Pass through boron ion implantation formation p-type doped region in each p-well；
（8）Pass through ion implanting phosphorus formation n-type doping area in each p-type doped region；
（9）Oxide layer is formed on the P- epitaxial layers, the position in each n-type doping area of correspondence forms contact in oxide layer
Hole, in each contact hole and oxidation layer surface deposit to form front electrode；
（10）Passivation layer is formed on front electrode surface, the hole as rear end packaging and routing is formed in the passivation layer；
（11）The N+ substrates are thinned, then backplate are prepared at the back side of the N+ substrates, to complete the two-way TVS bis- of two-way
The making of pole pipe.
Preferably, the step（1）Described in N+ substrates be<111>Crystal orientation, mixes As, and resistivity is 0.007Ohm.cm,
675 microns of thickness.
Preferably, the step（2）In, the thickness of the silicon dioxide layer is 1-3 microns, the thickness of the silicon nitride layer
Spend for 1-3 microns, the step（3）In, the positive silicon nitride layer of the N+ substrates is removed first with plasma etching,
Then the positive silicon dioxide layer of the N+ substrates is removed using the mix reagent of hydrofluoric acid and ammonium fluoride.
Preferably, the step（4）In, the thickness of the P- epitaxial layers is 3-6 microns, the resistance of the P- epitaxial layers
Rate is 50-150 Ohm.cm, protects the P- epitaxial layers using photoresist, the etching liquid of wet etching is hydrofluoric acid.
Preferably, the step（5）Concrete technology be：700 nanometers of oxide layer of growth, then gluing, photoetching, aobvious
Shadow, corrosion, in appropriate region openings, the ion implanting boron element in opening, implantation dosage is 4E14/cm2, Implantation Energy
For 70KeV.
Preferably, the step（5）Concrete technology be：Formation mask, then gluing, photoetching, development, corrosion,
Appropriate region windowing, the ion implanting boron element in window, implantation dosage is 4E14/cm2, Implantation Energy is 70KeV,
The step（6）Concrete technology be：Mask is formed, in appropriate region windowing, the N+ substrates are then put into 1000
DEG C boiler tube, be passed through PoCL3 gases and be doped, Yanzhong forms n-type doping area outside P-, is connected with N-type substrate, forms N
Type isolated area.
Preferably, the step（7）Concrete technology be：Mask is formed, in the Production Zones Suitable windowing of the p-well,
And ion implanting boron element, implantation dosage is 4E14/cm2, Implantation Energy is 160KeV, forms p-type doped region；The step
（8）Concrete technology be：Mask is formed, in the Production Zones Suitable windowing of the p-type doped region, and ion implanting P elements, note
Enter dosage for 3E15/cm2, Implantation Energy is 45KeV, forms n-type doping area.
Preferably, the step（9）Concrete technology be：Oxide layer is silicon dioxide layer, and the thickness of oxide layer is
200-500 nanometers, front electrode is aluminium copper silicon electrode, and the thickness of front electrode is 1-4 microns.
Preferably, the step（10）Concrete technology be：In 1-3 microns of thick PSG (phosphorus of front electrode surface deposition
Silica glass) and 1-3 microns of thick Si3N4It is used as passivation layer.
Preferably, the step（11）Concrete technology be：The N+ substrate thinnings pass through evaporation to 250 microns
Technique makes back of the body gold, forms backplate.
The back of the body gold can be that metallic element evaporation is made, it is preferred to use gold element evaporation is made.
The invention also provides a kind of two-way TVS diode of two-way, the two-way TVS diode of two-way is according to above-mentioned two-way
Prepared by the preparation method of two-way TVS diode.
Two TVS diodes of the present invention are respectively by the n-type doping region of region, p-type doped region, p-well and N
+ substrate and constitute, distinctive NPN structure, TVS diode is possessed the function of bi-directional symmetrical.By N-type between two TVS
Isolation is distinguished, and also has N-type isolation at the edge of device, and this causes the electric leakage before two diodes and device in device
The electric leakage at edge is preferably minimized, and two two-way TVS diodes are integrated in a chips by the present invention using integrated thinking,
One device can just protect two-way I/O ports, greatly save the area taken on pcb board, saved cost.
Brief description of the drawings
Fig. 1-11 is the flow chart of the preparation method of the two-way TVS diode of two-way of the present invention..
Embodiment
As shown in figs. 1-11, a kind of preparation method of the two-way TVS diode of two-way, comprises the following steps：
（1）N+ substrates are provided, as shown in figure 1, the N+ substrates are<111>Crystal orientation, mixes As, and resistivity is 0.007 Ohm.cm,
675 microns of thickness；
（2）Silicon dioxide layer and silicon nitride layer are grown successively respectively in the tow sides of the N+ substrates, as shown in Fig. 2 described
The thickness of silicon dioxide layer is 1-3 microns, and the thickness of the silicon nitride layer is 1-3 microns；
（3）The positive silicon dioxide layer and silicon nitride layer of the N+ substrates are removed, retains the titanium dioxide of the N+ substrate backs
Silicon layer and silicon nitride layer are as back of the body sealing, as shown in figure 3, specifically, removing the N+ substrates first with plasma etching
Positive silicon nitride layer, then remove the positive titanium dioxide of the N+ substrates using the mix reagent of hydrofluoric acid and ammonium fluoride
Silicon layer；
（4）A P- epitaxial layers are grown in the front of N+ substrates, then wet etching removes the silica of the N+ substrate backs
Layer and silicon nitride layer, as shown in figure 4, the thickness of the P- epitaxial layers is 3-6 microns, the resistivity of the P- epitaxial layers is 50-
150 Ohm.cm, protect the P- epitaxial layers, the etching liquid of wet etching is hydrofluoric acid using photoresist；
（5）Carry out in the P- epitaxial layers boron using mask to adulterate two p-wells to be formed and be set up in parallel, as shown in figure 5, it has
Body technology is：The oxide layer of 700 nanometers of growth, then gluing, photoetching, development, corrosion, in appropriate region openings, in opening
Interior ion implanting boron element, implantation dosage is 4E14/cm2, Implantation Energy is 70KeV；
（6）Pass through phosphorus doping formation N-type isolated area, such as Fig. 6 between the P- epitaxial layers both sides of the edge and two p-wells
Shown, its concrete technology is：Mask is formed, in appropriate region windowing, then the N+ substrates are put into 1000 DEG C of stove
Pipe, is passed through PoCL3 gases and is doped, and Yanzhong forms n-type doping area outside P-, is connected with N-type substrate, forms N-type isolation
Area；
（7）By boron ion implantation formation p-type doped region in each p-well, as shown in fig. 7, its concrete technology is：Formation is covered
Film, in the Production Zones Suitable windowing of the p-well, and ion implanting boron element, implantation dosage is 4E14/cm2, Implantation Energy is
160KeV, forms p-type doped region；
（8）By ion implanting phosphorus formation n-type doping area in each p-type doped region, as shown in figure 8, its concrete technology is：Shape
Into mask, in the Production Zones Suitable windowing of the p-type doped region, and ion implanting P elements, implantation dosage is 3E15/cm2,
Implantation Energy is 45KeV, forms n-type doping area；
（9）Oxide layer is formed on the P- epitaxial layers, the position in each n-type doping area of correspondence forms contact in oxide layer
Hole, in each contact hole and oxidation layer surface deposit to form front electrode, as shown in figure 9, its concrete technology is：Oxide layer
For silicon dioxide layer, the thickness of oxide layer is 200-500 nanometers, and front electrode is aluminium copper silicon electrode, and the thickness of front electrode is
1-4 microns；
（10）Passivation layer is formed on front electrode surface, the hole as rear end packaging and routing is formed in the passivation layer, such as Figure 10 institutes
Show, its concrete technology is：In front electrode surface deposition 1-3 microns of thick PSG (phosphorosilicate glass) and 1-3 microns of thick Si3N4Come
It is used as passivation layer；
（11）The N+ substrates are thinned, then backplate, as shown in figure 11, its specific work are prepared at the back side of the N+ substrates
Skill is：The N+ substrate thinnings make back of the body gold by the technique of evaporation, form backplate to 250 microns, double to complete two-way
To the making of TVS diode.
The invention also provides a kind of two-way TVS diode of two-way, as shown in figure 11, the two-way TVS diode of two-way
According to prepared by the preparation method of the two-way TVS diode of above-mentioned two-way.
Embodiment 1
As shown in figs. 1-11, a kind of preparation method of the two-way TVS diode of two-way, comprises the following steps：
（1）N+ substrates are provided, as shown in figure 1, the N+ substrates are<111>Crystal orientation, mixes As, and resistivity is 0.007 Ohm.cm,
675 microns of thickness；
（2）Silicon dioxide layer and silicon nitride layer are grown successively respectively in the tow sides of the N+ substrates, as shown in Fig. 2 described
The thickness of silicon dioxide layer is 1 micron, and the thickness of the silicon nitride layer is 1 micron；
（3）The positive silicon dioxide layer and silicon nitride layer of the N+ substrates are removed, retains the titanium dioxide of the N+ substrate backs
Silicon layer and silicon nitride layer are as back of the body sealing, as shown in figure 3, specifically, removing the N+ substrates first with plasma etching
Positive silicon nitride layer, then remove the positive titanium dioxide of the N+ substrates using the mix reagent of hydrofluoric acid and ammonium fluoride
Silicon layer；
（4）A P- epitaxial layers are grown in the front of N+ substrates, then wet etching removes the silica of the N+ substrate backs
Layer and silicon nitride layer, as shown in figure 4, the thickness of the P- epitaxial layers is 6 microns, the resistivity of the P- epitaxial layers is 100
Ohm.cm, protects the P- epitaxial layers, the etching liquid of wet etching is hydrofluoric acid using photoresist, i.e., with hydrofluoric acid by the back side
SiO2And Si3N4All drift is gone；
（5）Carry out in the P- epitaxial layers boron using mask to adulterate two p-wells to be formed and be set up in parallel, as shown in figure 5, it has
Body technology is：The oxide layer of 700 nanometers of growth, then gluing, photoetching, development, corrosion, in appropriate region openings, in opening
Interior ion implanting boron element, implantation dosage is 4E14/cm2, Implantation Energy is 70KeV；
（6）Pass through phosphorus doping formation N-type isolated area, such as Fig. 6 between the P- epitaxial layers both sides of the edge and two p-wells
Shown, its concrete technology is：Mask is formed, in appropriate region windowing, then the N+ substrates are put into 1000 DEG C of stove
Pipe, is passed through PoCL3 gases and is doped, and Yanzhong forms n-type doping area outside P-, is connected with N-type substrate, forms N-type isolation
Area；
（7）By boron ion implantation formation p-type doped region in each p-well, as shown in fig. 7, its concrete technology is：Formation is covered
Film, in the Production Zones Suitable windowing of the p-well, and ion implanting boron element, implantation dosage is 4E14/cm2, Implantation Energy is
160KeV, forms p-type doped region；
（8）By ion implanting phosphorus formation n-type doping area in each p-type doped region, as shown in figure 8, its concrete technology is：Shape
Into mask, in the Production Zones Suitable windowing of the p-type doped region, and ion implanting P elements, implantation dosage is 3E15/cm2,
Implantation Energy is 45KeV, forms n-type doping area；
（9）Oxide layer is formed on the P- epitaxial layers, the position in each n-type doping area of correspondence forms contact in oxide layer
Hole, in each contact hole and oxidation layer surface deposit to form front electrode, as shown in figure 9, its concrete technology is：Oxide layer
For silicon dioxide layer, the thickness of oxide layer is 300 nanometers, and front electrode is aluminium copper silicon electrode, and the thickness of front electrode is micro- for 2
Rice；
（10）Passivation layer is formed on front electrode surface, the hole as rear end packaging and routing is formed in the passivation layer, such as Figure 10 institutes
Show, its concrete technology is：In 1 micron of thick PSG (phosphorosilicate glass) of front electrode surface deposition and 1 micron of thick Si3N4It is used as
Passivation layer；
（11）The N+ substrates are thinned, then backplate, as shown in figure 11, its specific work are prepared at the back side of the N+ substrates
Skill is：The N+ substrate thinnings make back of the body gold by the technique of evaporation, form backplate to 250 microns, double to complete two-way
To the making of TVS diode.
The invention also provides a kind of two-way TVS diode of two-way, as shown in figure 11, the two-way TVS diode of two-way
According to prepared by the preparation method of the two-way TVS diode of above-mentioned two-way.
Described above is the preferred embodiment of the present invention, it is noted that for those skilled in the art
For, under the premise without departing from the principles of the invention, some improvements and modifications can also be made, these improvements and modifications are also considered as
Protection scope of the present invention.
Claims (10)
1. a kind of preparation method of the two-way TVS diode of two-way, it is characterised in that comprise the following steps：
（1）N+ substrates are provided；
（2）Silicon dioxide layer and silicon nitride layer are grown successively respectively in the tow sides of the N+ substrates；
（3）The positive silicon dioxide layer and silicon nitride layer of the N+ substrates are removed, retains the titanium dioxide of the N+ substrate backs
Silicon layer and silicon nitride layer are used as back of the body sealing；
（4）A P- epitaxial layers are grown in the front of N+ substrates, then wet etching removes the silica of the N+ substrate backs
Layer and silicon nitride layer；
（5）Boron is carried out in the P- epitaxial layers using mask to adulterate two p-wells to be formed and be set up in parallel；
（6）Pass through phosphorus doping formation N-type isolated area between the P- epitaxial layers both sides of the edge and two p-wells；
（7）Pass through boron ion implantation formation p-type doped region in each p-well；
（8）Pass through ion implanting phosphorus formation n-type doping area in each p-type doped region；
（9）Oxide layer is formed on the P- epitaxial layers, the position in each n-type doping area of correspondence forms contact in oxide layer
Hole, in each contact hole and oxidation layer surface deposit to form front electrode；
（10）Passivation layer is formed on front electrode surface, the hole as rear end packaging and routing is formed in the passivation layer；
（11）The N+ substrates are thinned, then backplate are prepared at the back side of the N+ substrates, to complete the two-way TVS bis- of two-way
The making of pole pipe.
2. the preparation method of the two-way TVS diode of two-way according to claim 1, it is characterised in that the step（1）In
The N+ substrates are<111>Crystal orientation, mixes As, and resistivity is 0.007 Ohm.cm, 675 microns of thickness.
3. the preparation method of the two-way TVS diode of two-way according to claim 1, it is characterised in that the step（2）
In, the thickness of the silicon dioxide layer is 1-3 microns, and the thickness of the silicon nitride layer is 1-3 microns, the step（3）In, it is first
The positive silicon nitride layer of the N+ substrates is removed first with plasma etching, the mixing of hydrofluoric acid and ammonium fluoride is then utilized
Reagent removes the positive silicon dioxide layer of the N+ substrates.
4. the preparation method of the two-way TVS diode of two-way according to claim 1, it is characterised in that the step（4）
In, the thickness of the P- epitaxial layers is 3-6 microns, and the resistivity of the P- epitaxial layers is 50-150 Ohm.cm, utilizes photoresist
The P- epitaxial layers are protected, the etching liquid of wet etching is hydrofluoric acid.
5. the preparation method of the two-way TVS diode of two-way according to claim 1, it is characterised in that the step（5）'s
Concrete technology is：The oxide layer of 700 nanometers of growth, then gluing, photoetching, development, corrosion, in appropriate region openings, is being opened
Intraoral ion implanting boron element, implantation dosage is 4E14/cm2, Implantation Energy is 70KeV.
6. the preparation method of the two-way TVS diode of two-way according to claim 1, it is characterised in that the step（5）'s
Concrete technology is：Formation mask, then gluing, photoetching, development, corrosion, in appropriate region windowing, ion is noted in window
Enter boron element, implantation dosage is 4E14/cm2, Implantation Energy is 70KeV, the step（6）Concrete technology be：Formation is covered
The N+ substrates, in appropriate region windowing, are then put into 1000 DEG C of boiler tube, are passed through PoCL3 gases and are doped by film,
Yanzhong forms n-type doping area outside P-, is connected with N-type substrate, forms N-type isolated area.
7. the preparation method of the two-way TVS diode of two-way according to claim 1, it is characterised in that the step（7）'s
Concrete technology is：Mask is formed, in the Production Zones Suitable windowing of the p-well, and ion implanting boron element, implantation dosage is 4E14
/cm2, Implantation Energy is 160KeV, forms p-type doped region；The step（8）Concrete technology be：Mask is formed, in the P
The Production Zones Suitable windowing of type doped region, and ion implanting P elements, implantation dosage are 3E15/cm2, Implantation Energy is
45KeV, forms n-type doping area.
8. the preparation method of the two-way TVS diode of two-way according to claim 1, it is characterised in that the step（9）'s
Concrete technology is：Oxide layer is silicon dioxide layer, and the thickness of oxide layer is 200-500 nanometers, and front electrode is aluminium copper silicon electrode,
The thickness of front electrode is 1-4 microns.
9. the preparation method of the two-way TVS diode of two-way according to claim 1, it is characterised in that the step（10）
Concrete technology be：In front electrode surface deposition 1-3 microns of thick PSG (phosphorosilicate glass) and 1-3 microns of thick Si3N4To make
For passivation layer, the step（11）Concrete technology be：The N+ substrate thinnings are made to 250 microns by the technique of evaporation
Back of the body gold, forms backplate.
10. a kind of two-way TVS diode of two-way, the two-way TVS diode of two-way is according to claim any one of 1-9
Prepared by the preparation method of the two-way TVS diode of two-way.
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| CN108933131A (en) * | 2018-07-18 | 2018-12-04 | 深圳市诚朗科技有限公司 | A kind of interface protection device and its manufacturing method |
| CN109599332A (en) * | 2018-12-27 | 2019-04-09 | 朝阳无线电元件有限责任公司 | A kind of low volt voltage adjustment diode manufacturing method |
| CN109659232A (en) * | 2018-12-11 | 2019-04-19 | 江南大学 | A kind of plane bidirectional trigger diode and preparation method thereof |
| CN111180336A (en) * | 2019-12-30 | 2020-05-19 | 上海芯导电子科技有限公司 | Low residual voltage surge protection device and manufacturing method thereof |
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| CN108933131A (en) * | 2018-07-18 | 2018-12-04 | 深圳市诚朗科技有限公司 | A kind of interface protection device and its manufacturing method |
| CN109659232A (en) * | 2018-12-11 | 2019-04-19 | 江南大学 | A kind of plane bidirectional trigger diode and preparation method thereof |
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