CN111176364A - High-order temperature compensation circuit and low-temperature drift voltage reference circuit - Google Patents
High-order temperature compensation circuit and low-temperature drift voltage reference circuit Download PDFInfo
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- CN111176364A CN111176364A CN202010040760.0A CN202010040760A CN111176364A CN 111176364 A CN111176364 A CN 111176364A CN 202010040760 A CN202010040760 A CN 202010040760A CN 111176364 A CN111176364 A CN 111176364A
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- G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
- G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
- G05F1/565—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor
- G05F1/567—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor for temperature compensation
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Abstract
The invention discloses a high-order temperature compensation circuit and a low-temperature drift voltage reference circuit, wherein the high-order temperature compensation circuit comprises a first current summing circuit, a first resistor and a first PNP triode; the first current summing circuit is used for summing a first current and a second current to obtain a third current, wherein the first current is linearly related to the temperature, and the second current is negatively related to the temperature; an emitter of the first PNP triode is connected with one end of the first resistor and is suitable for receiving the third current, and a collector of the third PNP triode is connected with a base of the third PNP triode and is grounded; the other end of the first resistor is connected with a branch circuit through which the second current flows. The high-order temperature compensation circuit and the low-temperature drift voltage reference circuit have the characteristics of simple structure and small area.
Description
Technical Field
The invention relates to the technical field of integrated circuits, in particular to a high-order temperature compensation circuit and a low-temperature drift voltage reference circuit.
Background
The voltage reference circuit has the advantages of low temperature drift coefficient, high power supply rejection ratio and the like, and is widely applied to various analog circuits. The stability and noise immunity of the output voltage of the voltage reference circuit affect the accuracy and reliability of the whole system. With the improvement of the precision requirement of an application system, the traditional voltage reference circuit cannot meet the requirements of high precision and high reliability. Therefore, the need for voltage reference circuits with ultra-low temperature drift and even zero temperature coefficient has become very urgent. In general, a reference voltage is obtained according to a current linearly related to positive temperature and a current linearly related to negative temperature, and in order to obtain the current linearly related to negative temperature, the current negatively related to temperature needs to be compensated by a high-order temperature compensation circuit so as to eliminate a high-order component in the current negatively related to temperature. However, the conventional high-order temperature compensation circuit has the problems of complex circuit and large occupied area.
Disclosure of Invention
The invention aims to solve the problems that a high-order temperature compensation circuit in a voltage reference circuit is complex and occupies a large area.
The invention is realized by the following technical scheme:
a high-order temperature compensation circuit comprises a first current summing circuit, a first resistor and a first PNP triode;
the first current summing circuit is used for summing a first current and a second current to obtain a third current, wherein the first current is linearly related to the temperature, and the second current is negatively related to the temperature;
an emitter of the first PNP triode is connected with one end of the first resistor and is suitable for receiving the third current, and a collector of the third PNP triode is connected with a base of the third PNP triode and is grounded;
the other end of the first resistor is connected with a branch circuit through which the second current flows.
Optionally, the first current summing circuit includes a first current mirror branch and a second current mirror branch connected in parallel;
the first current mirror branch is used for mirroring the first current;
the second current mirror branch is used for mirroring the second current.
Optionally, the first current mirror branch includes a first PMOS transistor, and the second current mirror branch includes a second PMOS transistor;
the source electrode of the first PMOS transistor is connected with the source electrode of the second PMOS transistor and is suitable for receiving a power supply voltage, the grid electrode of the first PMOS transistor is suitable for receiving a first bias voltage, and the drain electrode of the first PMOS transistor is connected with the drain electrode of the second PMOS transistor and is suitable for generating the third current;
the gate of the second PMOS transistor is adapted to receive a second bias voltage.
Based on the same inventive concept, the invention also provides a low-temperature drift voltage reference circuit, which comprises a first current generating circuit, a second current summing circuit, a converting circuit and the high-order temperature compensating circuit;
the first current generating circuit is used for generating the first current;
the second current generating circuit is used for generating the second current;
the high-order temperature compensation circuit is used for compensating the second current;
the second summing circuit is used for summing the first current and the compensated second current to obtain a fourth current;
the conversion circuit is used for converting the fourth current into a reference voltage.
Optionally, the first current generating circuit includes a third PMOS transistor, a fourth PMOS transistor, a second resistor, a second PNP triode, a third PNP triode, and a first operational amplifier, and a width-to-length ratio of the third PMOS transistor is equal to a width-to-length ratio of the fourth PMOS transistor;
the source electrode of the third PMOS transistor is connected with the source electrode of the fourth PMOS transistor and is suitable for receiving power supply voltage, the drain electrode of the third PMOS transistor is connected with the emitter electrode of the second PNP triode and the inverting input end of the first operational amplifier, and the grid electrode of the third PMOS transistor is connected with the grid electrode of the fourth PMOS transistor and the output end of the first operational amplifier;
the drain electrode of the fourth PMOS transistor is connected with one end of the second resistor and the non-inverting input end of the first operational amplifier;
the other end of the second resistor is connected with an emitting electrode of the third PNP triode;
the collector electrode of the second PNP triode is connected with the base electrode of the second PNP triode and grounded, and the collector electrode of the third PNP triode is connected with the base electrode of the third PNP triode and grounded.
Optionally, the second current generating circuit includes a fifth PMOS transistor, a third resistor, and a second operational amplifier;
the source of the fifth PMOS transistor is suitable for receiving the power supply voltage, the drain of the fifth PMOS transistor is connected with one end of the third resistor, the non-inverting input end of the second operational amplifier and the other end of the first resistor, and the grid of the fifth PMOS transistor is connected with the output end of the second operational amplifier;
the inverting input end of the second operational amplifier is connected with one end of the second resistor;
the other end of the third resistor is grounded.
Optionally, the second summing circuit includes a sixth PMOS transistor and a seventh PMOS transistor, and the converting circuit includes a fourth resistor;
a source of the sixth PMOS transistor is connected to a source of the seventh PMOS transistor and adapted to receive the power supply voltage, a gate of the sixth PMOS transistor is connected to a gate of the third PMOS transistor, and a drain of the sixth PMOS transistor is connected to a drain of the seventh PMOS transistor and one end of the fourth resistor and adapted to generate the reference voltage;
the grid electrode of the seventh PMOS transistor is connected with the grid electrode of the fifth PMOS transistor;
the other end of the fourth resistor is grounded.
Optionally, the low temperature drift voltage reference circuit further includes:
a first start-up circuit to provide a bias voltage to the first operational amplifier;
a second start-up circuit to provide a bias voltage to the second operational amplifier.
Optionally, the first starting circuit includes an eighth PMOS transistor, a ninth PMOS transistor, a tenth PMOS transistor, an eleventh PMOS transistor, a twelfth PMOS transistor, a first NMOS transistor, a second NMOS transistor, and a fifth resistor;
a gate of the eighth PMOS transistor and a gate of the eleventh PMOS transistor are connected to a gate of the third PMOS transistor, a source of the eighth PMOS transistor is connected to a source of the ninth PMOS transistor, a source of the tenth PMOS transistor, a source of the eleventh PMOS transistor, and a source of the twelfth PMOS transistor and is adapted to receive the power supply voltage, and a drain of the eighth PMOS transistor is connected to one end of the fifth resistor, a gate of the ninth PMOS transistor, and a gate of the tenth PMOS transistor;
the other end of the fifth resistor is connected with the source electrode of the first NMOS transistor and the source electrode of the second NMOS transistor and is grounded;
the drain electrode of the ninth PMOS transistor is connected with the emitter electrode of the second PNP triode;
the drain electrode of the tenth PMOS transistor is connected with the drain electrode of the first NMOS transistor, the grid electrode of the second NMOS transistor and the drain electrode of the eleventh PMOS transistor;
the drain of the second NMOS transistor is connected to the gate of the twelfth PMOS transistor, the drain of the twelfth PMOS transistor, and the bias voltage input terminal of the first operational amplifier.
Optionally, the second starting circuit includes a thirteenth PMOS transistor, a fourteenth PMOS transistor, a fifteenth PMOS transistor, a sixteenth PMOS transistor, a seventeenth PMOS transistor, a third NMOS transistor, a fourth NMOS transistor, and a sixth resistor;
a gate of the thirteenth PMOS transistor and a gate of the sixteenth PMOS transistor are connected to a gate of the fifth PMOS transistor, a source of the thirteenth PMOS transistor is connected to a source of the fourteenth PMOS transistor, a source of the fifteenth PMOS transistor, a source of the sixteenth PMOS transistor, and a source of the seventeenth PMOS transistor and is adapted to receive the power supply voltage, and a drain of the thirteenth PMOS transistor is connected to one end of the sixth resistor, a gate of the fourteenth PMOS transistor, and a gate of the fifteenth PMOS transistor;
the other end of the sixth resistor is connected with the source electrode of the third NMOS transistor and the source electrode of the fourth NMOS transistor and is grounded;
the drain electrode of the fourteenth PMOS transistor is connected with the emitter electrode of the third PNP triode;
the drain of the fifteenth PMOS transistor is connected with the drain of the third NMOS transistor, the gate of the fourth NMOS transistor and the drain of the sixteenth PMOS transistor;
the drain of the fourth NMOS transistor is connected to the gate of the seventeenth PMOS transistor, the drain of the seventeenth PMOS transistor, and the bias voltage input terminal of the second operational amplifier.
Compared with the prior art, the invention has the following advantages and beneficial effects:
according to the high-order temperature compensation circuit and the low-temperature drift voltage reference circuit, the high-order temperature compensation circuit is adopted to compensate high-order components in the current which is negatively related to the temperature, the current which is linearly related to the negative temperature is generated, the current which is linearly related to the negative temperature and the current which is linearly related to the positive temperature are summed, and finally the summed current is converted into the reference voltage. The high-order temperature compensation circuit has the characteristics of simple structure and small area because the number of the resistors in the high-order temperature compensation circuit is one. Meanwhile, the low-temperature-drift voltage reference circuit also has extremely high power supply rejection ratio and extremely high stability.
Drawings
The accompanying drawings, which are included to provide a further understanding of the embodiments of the invention and are incorporated in and constitute a part of this application, illustrate embodiment(s) of the invention and together with the description serve to explain the principles of the invention. In the drawings:
FIG. 1 is a schematic circuit diagram of a low temperature drift voltage reference circuit according to an embodiment of the present invention;
FIG. 2 is a circuit diagram of a first start-up circuit according to an embodiment of the present invention;
FIG. 3 is a circuit diagram of a second start-up circuit according to an embodiment of the present invention;
fig. 4 is a functional simulation diagram of the low temperature drift voltage reference circuit according to the embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is further described in detail below with reference to examples and accompanying drawings, and the exemplary embodiments and descriptions thereof are only used for explaining the present invention and are not meant to limit the present invention.
Examples
Fig. 1 is a schematic circuit structure diagram of the low temperature drift voltage reference circuit, the low temperature drift voltage reference circuit includes a high-order temperature compensation circuit 11, a first current generation circuit 12, a second current generation circuit 13, a second current summation circuit 14, and a conversion circuit 15, wherein the high-order temperature compensation circuit 11 includes a first current summation circuit 11, a first resistor R1, and a first PNP transistor Q1.
Specifically, the first current summing circuit 10 is configured to sum the first current i1 and the second current i2 to obtain a third current i 3. Wherein the first current i1 is linearly related to temperature, and the second current i2 is negatively related to temperature, i.e. the second current i2 includes high-order terms related to temperature. In an alternative implementation, the first current summing circuit 10 includes a first current mirror branch and a second current mirror branch connected in parallel, wherein the first current mirror branch is used for mirroring the first current i1, and the second current mirror branch is used for mirroring the second current i 2. In the present embodiment, the first current mirror branch includes a first PMOS transistor P1, and the second current mirror branch includes a second PMOS transistor P2. The source of the first PMOS transistor P1 is connected to the source of the second PMOS transistor P2 and adapted to receive a power supply voltage Vdd, the gate of the first PMOS transistor P1 is adapted to receive a first bias voltage vb1, the drain of the first PMOS transistor P1 is connected to the drain of the second PMOS transistor P2 and adapted to generate the third current i 3; the gate of the second PMOS transistor P2 is adapted to receive a second bias voltage vb 2.
The emitter of the first PNP transistor Q1 is connected to one end of the first resistor R1 and is adapted to receive the third current i3, the collector of the third PNP transistor Q1 is connected to the base of the third PNP transistor Q1 and is grounded, and the other end of the first resistor R1 is connected to the branch through which the second current i2 flows, that is, the other end of the first resistor R1 is connected to the branch of the second current generating circuit 13 that generates the second current i 2.
The first current generating circuit 12 is configured to generate the first current i 1. As an alternative implementation manner, the first current generating circuit 12 includes a third PMOS transistor P3, a fourth PMOS transistor P4, a second resistor R2, a second PNP transistor Q2, a third PNP transistor Q3, and a first operational amplifier a1, wherein a width-to-length ratio of the third PMOS transistor P3 is equal to a width-to-length ratio of the fourth PMOS transistor P4. A source of the third PMOS transistor P3 is connected to a source of the fourth PMOS transistor P4 and adapted to receive the power supply voltage Vdd, a drain of the third PMOS transistor P3 is connected to an emitter of the second PNP transistor Q2 and an inverting input of the first operational amplifier a1, and a gate of the third PMOS transistor P3 is connected to a gate of the fourth PMOS transistor P4 and an output of the first operational amplifier a 1; the drain of the fourth PMOS transistor P4 is connected to one end of the second resistor R2 and the non-inverting input terminal of the first operational amplifier A1; the other end of the second resistor R2 is connected with the emitter of the third PNP triode Q3; the collector of the second PNP triode Q2 is connected to the base of the second PNP triode Q2 and ground, and the collector of the third PNP triode Q3 is connected to the base of the third PNP triode Q3 and ground. It should be noted that the gate voltage of the third PMOS transistor P3 may be the first bias voltage vb1, that is, the gate of the first PMOS transistor P1 may be connected to the gate of the third PMOS transistor P3.
The second current generating circuit 13 is configured to generate the second current i 2. As an alternative implementation, the second current generation circuit 13 includes a fifth PMOS transistor P5, a third resistor R3, and a second operational amplifier a 2. The source of the fifth PMOS transistor P5 is adapted to receive the power voltage Vdd, the drain of the fifth PMOS transistor P5 is connected to one end of the third resistor R3, the non-inverting input of the second operational amplifier a2 and the other end of the first resistor R1, and the gate of the fifth PMOS transistor P5 is connected to the output of the second operational amplifier a 2; the inverting input end of the second operational amplifier A2 is connected with one end of the second resistor R2; the other end of the third resistor R3 is grounded. It should be noted that the gate voltage of the fifth PMOS transistor P5 may be the second bias voltage vb2, that is, the gate of the second PMOS transistor P2 may be connected to the gate of the fifth PMOS transistor P5.
The second summing circuit 14 is configured to sum the first current i1 and the compensated second current i2 to obtain a fourth current i 4; the conversion circuit 15 is configured to convert the fourth current i4 into a reference voltage Vref. As an alternative implementation, the second summing circuit 14 includes a sixth PMOS transistor P6 and a seventh PMOS transistor P7, and the conversion circuit includes a fourth resistor R4. A source of the sixth PMOS transistor P6 is connected to a source of the seventh PMOS transistor P7 and adapted to receive the power supply voltage Vdd, a gate of the sixth PMOS transistor P6 is connected to a gate of the third PMOS transistor P3, a drain of the sixth PMOS transistor P6 is connected to a drain of the seventh PMOS transistor P7 and one end of the fourth resistor R4 and adapted to generate the reference voltage i 4; the gate of the seventh PMOS transistor P7 is connected to the gate of the fifth PMOS transistor P5; the other end of the fourth resistor R4 is grounded.
In the first current generating circuit 12, since the width-to-length ratio of the third PMOS transistor P3 and the width-to-length ratio of the fourth PMOS transistor P4 are equal, if the ratio of the areas of the third PNP transistor Q3 and the second PNP transistor Q2 is n, there are:
ΔVBE＝VBE2-VBE2＝VT1n(n) (3)
wherein, I2Is the emitter current, I, of the second PNP transistor Q2S2Is the saturation current, V, of the second PNP transistor Q2BE2Is the voltage difference between the base electrode and the emitter electrode of the second PNP triode Q2, VTIs a thermal voltage, I3Is the emitter current, I, of the third PNP transistor Q3S3Is the saturation current, V, of the third PNP transistor Q3BE3The voltage difference between the base and the emitter of the third PNP transistor Q3. Since the high gain of the first operational amplifier A1 forces A, B two-point voltages to be equal, Δ VBEI.e. the voltage difference across the second resistor R2, thus there is:
in the second current generation circuit 13, the high gain of the second operational amplifier a2 makes the voltages at C, B two points equal, so the current flowing through the third resistor R3 is:
wherein, VG(T) is the temperature function of the forbidden band voltage of silicon, T is the absolute temperature, TrAt a specific temperature, VG(Tr) At a temperature of Trthe forbidden band voltage of Si, η is a constant independent of temperature, k is the Boltzmann constant, q is the electron chargeBE2Does not vary completely linearly with temperature.
In the high-order temperature compensation circuit 11, I2And IR3Adding with appropriate weights makes the current through the first PNP transistor Q1 first order independent of temperature, thus:
wherein, VBE1Is the voltage difference between the base electrode and the emitter electrode of the first PNP triode Q1, VBE1(T) is a temperature function of the difference between the base and emitter voltages of the first PNP transistor Q1, VBE1(Tr) At a temperature of TrThe voltage difference between the base electrode and the emitter electrode of the first PNP triode Q1 is measured. Thus, adding the first resistor R1 between points C and D creates an AND
A proportional high order temperature term current that, when added to the current through the third resistor R3, compensates for the non-linear temperature term in equation (5). Finally, the current flowing through the fifth PMOS transistor P5 is negatively linearly dependent on temperature.
The second summing circuit 14 duplicates the current flowing through the third PMOS transistor P3 and the current flowing through the fifth PMOS transistor P5, the fourth resistor R4 converts the fourth current i4 into the output of the reference voltage Vref, which can be expressed as:
the power consumption of the circuit can be controlled by properly adjusting the ratio of the resistors, and a voltage reference with a high-order compensation ultralow temperature drift coefficient is realized.
When the low-temperature ticket voltage reference circuit is just started, the circuit may be in a metastable state, so that the first operational amplifier A1 and the second operational amplifier A2 are not operated, and no current flows in the circuit. In order to eliminate the possibility of the low temperature ticket voltage reference circuit falling into a metastable state, the low temperature ticket voltage reference circuit may further include: a first start-up circuit for providing a bias voltage to the first operational amplifier A1; a second start-up circuit for providing a bias voltage to the second operational amplifier A2.
Fig. 2 is a circuit diagram of the first start-up circuit, which includes an eighth PMOS transistor P8, a ninth PMOS transistor P9, a tenth PMOS transistor P10, an eleventh PMOS transistor P11, a twelfth PMOS transistor P12, a first NMOS transistor N1, a second NMOS transistor N2, and a fifth resistor R5. A gate of the eighth PMOS transistor P8 and a gate of the eleventh PMOS transistor P11 are connected to the gate of the third PMOS transistor P3, a source of the eighth PMOS transistor P8 is connected to a source of the ninth PMOS transistor P9, a source of the tenth PMOS transistor P10, a source of the eleventh PMOS transistor P11 and a source of the twelfth PMOS transistor P12 and is adapted to receive the power supply voltage Vdd, and a drain of the eighth PMOS transistor P8 is connected to one end of the fifth resistor R5, a gate of the ninth PMOS transistor P9 and a gate of the tenth PMOS transistor P10; the other end of the fifth resistor R5 is connected with the source of the first NMOS transistor N1 and the source of the second NMOS transistor N2 and grounded; the drain electrode of the ninth PMOS transistor P9 is connected with the emitter electrode of the second PNP triode Q2; the drain of the tenth PMOS transistor P10 is connected to the drain of the first NMOS transistor N1, the gate of the first NMOS transistor N1, the gate of the second NMOS transistor N2, and the drain of the eleventh PMOS transistor P11; the drain of the second NMOS transistor N2 is connected to the gate of the twelfth PMOS transistor P12, the drain of the twelfth PMOS transistor P12 and the bias voltage input terminal vp1 of the first operational amplifier A1.
Fig. 3 is a circuit diagram of the second start-up circuit, which includes a thirteenth PMOS transistor P13, a fourteenth PMOS transistor P14, a fifteenth PMOS transistor P15, a sixteenth PMOS transistor P16, a seventeenth PMOS transistor P17, a third NMOS transistor N3, a fourth NMOS transistor N4, and a sixth resistor R6. A gate of the thirteenth PMOS transistor P13 and a gate of the sixteenth PMOS transistor P16 are connected to the gate of the fifth PMOS transistor P5, a source of the thirteenth PMOS transistor P13 is connected to the source of the fourteenth PMOS transistor P14, the source of the fifteenth PMOS transistor P15, the source of the sixteenth PMOS transistor P16 and the source of the seventeenth PMOS transistor P17 and is adapted to receive the power supply voltage Vdd, and a drain of the thirteenth PMOS transistor P13 is connected to one end of the sixth resistor R6, the gate of the fourteenth PMOS transistor P14 and the gate of the fifteenth PMOS transistor P15; the other end of the sixth resistor R6 is connected to the source of the third NMOS transistor N3 and the source of the fourth NMOS transistor N4 and grounded; the drain electrode of the fourteenth PMOS transistor P14 is connected with the emitter electrode of the third PNP triode Q3; the drain of the fifteenth PMOS transistor 15 is connected to the drain of the third NMOS transistor N3, the gate of the third NMOS transistor N3, the gate of the fourth NMOS transistor N4 and the drain of the sixteenth PMOS transistor P16; the drain of the fourth NMOS transistor N4 is connected to the gate of the seventeenth PMOS transistor P17, the drain of the seventeenth PMOS transistor P17 and the bias voltage input vp2 of the second operational amplifier a 2.
When the low temperature ticket voltage reference circuit is started, the voltage at point a is close to zero, the gate voltage of the third PMOS transistor P3 is close to the power supply voltage Vdd, the ninth PMOS transistor P9, the tenth PMOS transistor P10, the fourteenth PMOS transistor P14, and the fifteenth PMOS transistor P15 are turned on, injecting current into the second PNP transistor Q2 and the third PNP transistor Q3, raising voltages at a point a and B, while the current mirror formed by the first NMOS transistor N1 and the second NMOS transistor N2 mirrors the current flowing through the tenth PMOS transistor P10, the current mirror formed by the third NMOS transistor N3 and the fourth NMOS transistor N4 mirrors the current flowing through the fifteenth PMOS transistor P15, and provides a bias current for the first operational amplifier a1 and the second operational amplifier a2 to start the operation thereof, so that the output voltage drops to make the circuit go out of the metastable state and enter the normal operating state.
Fig. 4 is a schematic diagram of a functional simulation of the voltage reference circuit provided in this embodiment. As can be seen from fig. 4, the low temperature drift voltage reference circuit provided by this embodiment compensates the high-order component in the current negatively correlated to temperature by using the high-order temperature compensation circuit 10, generates a current negatively linearly correlated to temperature, and finally converts the summed current into the reference voltage Vref by summing the current negatively linearly correlated to temperature and the current positively linearly correlated to temperature. Since the number of the resistors in the high-order temperature compensation circuit 10 is one, the high-order temperature compensation circuit 10 has the characteristics of simple structure and small area. Meanwhile, the low-temperature-drift voltage reference circuit also has extremely high power supply rejection ratio and extremely high stability. It should be noted that specific circuits of the first current generating circuit 12, the second current generating circuit 13, the second current summing circuit 14 and the converting circuit 15 are not limited to the description of the present embodiment, and the high-order temperature compensating circuit 10 is not limited to the first current generating circuit 12, the second current generating circuit 13, the second current summing circuit 14 and the converting circuit 15 described in the present embodiment to constitute the low-temperature drift voltage reference circuit, that is, high-order components in the current negatively correlated to temperature can be compensated by using the high-order temperature compensating circuit 10.
The above-mentioned embodiments are intended to illustrate the objects, technical solutions and advantages of the present invention in further detail, and it should be understood that the above-mentioned embodiments are merely exemplary embodiments of the present invention, and are not intended to limit the scope of the present invention, and any modifications, equivalent substitutions, improvements and the like made within the spirit and principle of the present invention should be included in the scope of the present invention.
Claims (10)
1. A high-order temperature compensation circuit is characterized by comprising a first current summing circuit, a first resistor and a first PNP triode;
the first current summing circuit is used for summing a first current and a second current to obtain a third current, wherein the first current is linearly related to the temperature, and the second current is negatively related to the temperature;
an emitter of the first PNP triode is connected with one end of the first resistor and is suitable for receiving the third current, and a collector of the third PNP triode is connected with a base of the third PNP triode and is grounded;
the other end of the first resistor is connected with a branch circuit through which the second current flows.
2. The higher order temperature compensation circuit of claim 1, wherein the first current summing circuit comprises a first current mirror branch and a second current mirror branch connected in parallel;
the first current mirror branch is used for mirroring the first current;
the second current mirror branch is used for mirroring the second current.
3. The higher-order temperature compensation circuit of claim 2, wherein the first current mirror branch comprises a first PMOS transistor and the second current mirror branch comprises a second PMOS transistor;
the source electrode of the first PMOS transistor is connected with the source electrode of the second PMOS transistor and is suitable for receiving a power supply voltage, the grid electrode of the first PMOS transistor is suitable for receiving a first bias voltage, and the drain electrode of the first PMOS transistor is connected with the drain electrode of the second PMOS transistor and is suitable for generating the third current;
the gate of the second PMOS transistor is adapted to receive a second bias voltage.
4. A low temperature drift voltage reference circuit, comprising a first current generating circuit, a second current summing circuit, a converting circuit and the high order temperature compensation circuit of any one of claims 1 to 3;
the first current generating circuit is used for generating the first current;
the second current generating circuit is used for generating the second current;
the high-order temperature compensation circuit is used for compensating the second current;
the second summing circuit is used for summing the first current and the compensated second current to obtain a fourth current;
the conversion circuit is used for converting the fourth current into a reference voltage.
5. The low temperature drift voltage reference circuit according to claim 4, wherein the first current generating circuit comprises a third PMOS transistor, a fourth PMOS transistor, a second resistor, a second PNP transistor, a third PNP transistor and a first operational amplifier, and the width-to-length ratio of the third PMOS transistor is equal to the width-to-length ratio of the fourth PMOS transistor;
the source electrode of the third PMOS transistor is connected with the source electrode of the fourth PMOS transistor and is suitable for receiving power supply voltage, the drain electrode of the third PMOS transistor is connected with the emitter electrode of the second PNP triode and the inverting input end of the first operational amplifier, and the grid electrode of the third PMOS transistor is connected with the grid electrode of the fourth PMOS transistor and the output end of the first operational amplifier;
the drain electrode of the fourth PMOS transistor is connected with one end of the second resistor and the non-inverting input end of the first operational amplifier;
the other end of the second resistor is connected with an emitting electrode of the third PNP triode;
the collector electrode of the second PNP triode is connected with the base electrode of the second PNP triode and grounded, and the collector electrode of the third PNP triode is connected with the base electrode of the third PNP triode and grounded.
6. The low temperature drift voltage reference circuit according to claim 5, wherein the second current generating circuit comprises a fifth PMOS transistor, a third resistor and a second operational amplifier;
the source of the fifth PMOS transistor is suitable for receiving the power supply voltage, the drain of the fifth PMOS transistor is connected with one end of the third resistor, the non-inverting input end of the second operational amplifier and the other end of the first resistor, and the grid of the fifth PMOS transistor is connected with the output end of the second operational amplifier;
the inverting input end of the second operational amplifier is connected with one end of the second resistor;
the other end of the third resistor is grounded.
7. The low temperature drift voltage reference circuit according to claim 6, wherein the second summing circuit comprises a sixth PMOS transistor and a seventh PMOS transistor, and the converting circuit comprises a fourth resistor;
a source of the sixth PMOS transistor is connected to a source of the seventh PMOS transistor and adapted to receive the power supply voltage, a gate of the sixth PMOS transistor is connected to a gate of the third PMOS transistor, and a drain of the sixth PMOS transistor is connected to a drain of the seventh PMOS transistor and one end of the fourth resistor and adapted to generate the reference voltage;
the grid electrode of the seventh PMOS transistor is connected with the grid electrode of the fifth PMOS transistor;
the other end of the fourth resistor is grounded.
8. The low temperature drift voltage reference circuit of claim 6, further comprising:
a first start-up circuit to provide a bias voltage to the first operational amplifier;
a second start-up circuit to provide a bias voltage to the second operational amplifier.
9. The low temperature-drift voltage reference circuit of claim 8, wherein the first start-up circuit comprises an eighth PMOS transistor, a ninth PMOS transistor, a tenth PMOS transistor, an eleventh PMOS transistor, a twelfth PMOS transistor, a first NMOS transistor, a second NMOS transistor, and a fifth resistor;
a gate of the eighth PMOS transistor and a gate of the eleventh PMOS transistor are connected to a gate of the third PMOS transistor, a source of the eighth PMOS transistor is connected to a source of the ninth PMOS transistor, a source of the tenth PMOS transistor, a source of the eleventh PMOS transistor, and a source of the twelfth PMOS transistor and is adapted to receive the power supply voltage, and a drain of the eighth PMOS transistor is connected to one end of the fifth resistor, a gate of the ninth PMOS transistor, and a gate of the tenth PMOS transistor;
the other end of the fifth resistor is connected with the source electrode of the first NMOS transistor and the source electrode of the second NMOS transistor and is grounded;
the drain electrode of the ninth PMOS transistor is connected with the emitter electrode of the second PNP triode;
the drain electrode of the tenth PMOS transistor is connected with the drain electrode of the first NMOS transistor, the grid electrode of the second NMOS transistor and the drain electrode of the eleventh PMOS transistor;
the drain of the second NMOS transistor is connected to the gate of the twelfth PMOS transistor, the drain of the twelfth PMOS transistor, and the bias voltage input terminal of the first operational amplifier.
10. The low temperature-drift voltage reference circuit of claim 8, wherein the second start-up circuit comprises a thirteenth PMOS transistor, a fourteenth PMOS transistor, a fifteenth PMOS transistor, a sixteenth PMOS transistor, a seventeenth PMOS transistor, a third NMOS transistor, a fourth NMOS transistor and a sixth resistor;
a gate of the thirteenth PMOS transistor and a gate of the sixteenth PMOS transistor are connected to a gate of the fifth PMOS transistor, a source of the thirteenth PMOS transistor is connected to a source of the fourteenth PMOS transistor, a source of the fifteenth PMOS transistor, a source of the sixteenth PMOS transistor, and a source of the seventeenth PMOS transistor and is adapted to receive the power supply voltage, and a drain of the thirteenth PMOS transistor is connected to one end of the sixth resistor, a gate of the fourteenth PMOS transistor, and a gate of the fifteenth PMOS transistor;
the other end of the sixth resistor is connected with the source electrode of the third NMOS transistor and the source electrode of the fourth NMOS transistor and is grounded;
the drain electrode of the fourteenth PMOS transistor is connected with the emitter electrode of the third PNP triode;
the drain of the fifteenth PMOS transistor is connected with the drain of the third NMOS transistor, the gate of the fourth NMOS transistor and the drain of the sixteenth PMOS transistor;
the drain of the fourth NMOS transistor is connected to the gate of the seventeenth PMOS transistor, the drain of the seventeenth PMOS transistor, and the bias voltage input terminal of the second operational amplifier.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202010040760.0A CN111176364A (en) | 2020-01-14 | 2020-01-14 | High-order temperature compensation circuit and low-temperature drift voltage reference circuit |
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| CN202010040760.0A CN111176364A (en) | 2020-01-14 | 2020-01-14 | High-order temperature compensation circuit and low-temperature drift voltage reference circuit |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN112015226A (en) * | 2020-08-20 | 2020-12-01 | 南京物间科技有限公司 | High-precision voltage reference source with wide power supply voltage range |
| CN112859996A (en) * | 2021-01-22 | 2021-05-28 | 中国科学院上海微系统与信息技术研究所 | Low-voltage high-precision band-gap reference circuit |
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| CN105786077A (en) * | 2016-04-20 | 2016-07-20 | 广东工业大学 | High-order temperature drift compensation band-gap reference circuit without operational amplifier |
| CN107045370A (en) * | 2017-06-20 | 2017-08-15 | 上海灿瑞科技股份有限公司 | It is a kind of that there is high-order temperature compensated band gap reference voltage source circuit |
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| CN102323842A (en) * | 2011-05-13 | 2012-01-18 | 电子科技大学 | Band-gap voltage reference source for high-order temperature compensation |
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| CN112859996A (en) * | 2021-01-22 | 2021-05-28 | 中国科学院上海微系统与信息技术研究所 | Low-voltage high-precision band-gap reference circuit |
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Application publication date: 20200519 |