CN113820574A - SoC (system on chip) architecture and device for arc detection - Google Patents
SoC (system on chip) architecture and device for arc detection Download PDFInfo
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Abstract
The present application relates to a SoC architecture for sampling electrical signals in an electrical grid and obtaining target sampling data for identifying a fault arc, the SoC architecture comprising: the acquisition front end is used for sampling electric signals in a power grid, acquiring initial sampling data, and processing the initial sampling data to obtain target sampling data comprising fault arcs; the memory is used for storing programs and data, and the programs comprise user programs and bootstrap programs; the microcontroller is electrically connected with the memory and the acquisition front end and is used for responding to a starting instruction and controlling a user program in an external storage space to be stored to a first preset position in the memory; and controlling the target sampling data under the preset sampling mode to be stored in a second preset position in the memory according to the program. By adopting the method, the electric signal taken out from the power grid can be sampled, and then the fault electric arc can be researched through software analysis and electric arc identification processing.
Description
Technical Field
The present application relates to the field of power failure detection technologies, and in particular, to an SoC architecture and an apparatus for arc detection.
Background
When the power supply of the electric wire or the electric appliance in the power distribution system is in a long-time overload running state or bad electric connection and the like, the insulating layer of the electric wire is aged, so that the insulating effect is reduced, or the insulating layer is damaged to cause arc faults. When an arc fault occurs in the line, it is likely to cause a fire by spraying high temperature particles or high temperature gas to ignite surrounding combustibles.
The cause of arc faults, the damage caused and countermeasures have been intensively studied from the 90 s internationally. However, due to the complexity of arc faults, there is no reliable method for fully detecting and protecting arc faults. With the rise and the rapid development of the smart power grid, when a circuit breaks down, the air switch and the leakage protector can be used for effectively and timely disconnecting the circuit, but the traditional circuit breaker cannot effectively screen out the fault arc and disconnect the circuit to achieve a protection effect. Therefore, the detection of fault arcs is of paramount importance in intelligent power distribution systems.
Most of domestic and foreign researches are around arc identification methods for research and analysis, such as time domain and frequency domain characteristics, wavelet analysis, neural networks, fault identification based on fusion technology of certain or some characteristics of series arc current and overall characteristics, and the like, and are based on arc detection system on chip (SoC) hardware platforms. However, with the development of the nano-scale CMOS process, the large-scale integrated circuit is rapidly developed and applied, and the conventional system on chip (SoC) hardware platform cannot well satisfy the arc identification method. Therefore, how to design a special power SoC for arc detection is of great significance.
Disclosure of Invention
In view of the above, it is desirable to provide an SoC architecture and apparatus for arc detection.
To achieve the above and other objects, an aspect of the present application provides an SoC architecture for arc detection, characterized by sampling an electrical signal in a power grid and acquiring target sampling data for identifying a fault arc, the SoC architecture comprising:
the system comprises an acquisition front end, a fault detection front end and a fault detection front end, wherein the acquisition front end is used for sampling an electric signal in a power grid, acquiring initial sampling data, and processing the initial sampling data to obtain target sampling data comprising a fault arc;
a memory for storing programs and data, the programs including a user program and a bootstrap program;
the microcontroller is electrically connected with the memory and the acquisition front end and used for responding to a starting instruction and controlling a user program in an external storage space to be stored to a first preset position in the memory; and controlling the target sampling data under the preset sampling mode to be stored in a second preset position in the memory according to the program.
In the SoC architecture for arc detection in the above embodiment, the electrical signal taken out of the power grid is sampled, processed and analyzed by the acquisition front end, and the processed target sampling data is stored so as to rapidly determine the type of the fault and make corresponding measures when an arc fault occurs.
In one embodiment, the acquisition front end comprises a nyquist analog-to-digital converter; the Nyquist analog-to-digital converter includes:
a sampling switch configured to: the input end is connected with a common mode voltage;
a comparator configured to: the reverse-phase input end is connected with the output end of the sampling switch, the normal-phase input end is connected with the common-mode voltage, and the output end is used for outputting the target sampling data;
the capacitive array digital-to-analog converter comprises a capacitive array and a plurality of change-over switches, wherein each change-over switch comprises an output terminal, a first input terminal, a second input terminal and a third input terminal which are connected with a corresponding capacitor; the first input terminal is connected to a reference voltage, the second input terminal is connected to a signal voltage, and the third input terminal is connected to a ground line. The Nyquist analog-to-digital converter adopts a successive approximation type analog-to-digital converter structure, and the successive approximation type analog-to-digital converter is widely applied to the field of medium and low speed application due to simple structure, few analog modules, small area and low power consumption. In order to achieve a sampling rate of 1M.
In one embodiment, the second preset location comprises a register; the comparator includes:
a pre-amplification unit configured to: the first input end is connected with the common-mode voltage, the second input end is connected with the output end of the sampling switch, the third input end is connected with the first clock signal, the first output end is used for outputting a first differential signal, and the second output end is used for outputting a second differential signal;
a latch compare unit connected to the pre-amplification unit and configured to: the first input end is connected with the first differential signal, the second input end is connected with the second differential signal, and the output end is used for outputting the target sampling data;
the microcontroller is configured to:
in a first clock cycle of the first clock signal, controlling the comparator to successively compare the highest position 1 of the register, instructing the capacitor array digital-to-analog converter to output a corresponding voltage to an inverting input end of the comparator, and controlling the comparator to compare a voltage received by the inverting input end of the comparator with the common-mode voltage; if the common mode voltage is larger than the voltage received by the reverse input end, controlling the comparator to output 1, otherwise, enabling the highest position of the register to be 0;
and in the second clock cycle of the first clock signal, indicating the second highest position 1 of the register to output a corresponding voltage to the inverting input end of the comparator by the capacitor array digital-to-analog converter, and controlling the comparator to compare the received voltage and output a corresponding comparison result. In order to reduce power consumption compared to a static comparator.
In one embodiment, the acquisition front end comprises a sigma-delta analog-to-digital converter; the sigma-delta analog-to-digital converter comprises:
a delta-sigma modulator module configured to: the input end is connected with signal voltage, and the output end outputs a modulation and demodulation signal;
and the digital down-sampling filtering module is connected with the delta-sigma modulator module and is used for extracting and filtering the modulation and demodulation signals and outputting the target sampling data. So as to reduce the quantization noise in the system frequency band, and the low-pass filter is added after the delta-sigma modulator, so that the quantization noise outside the signal bandwidth can be effectively filtered, and the system performance is greatly improved.
In one embodiment, the delta-sigma modulator module comprises:
a subtractor configured to: the input end is connected with both the signal voltage and the modulation and demodulation signal and is used for calculating the difference value of the signal voltage and the voltage amplitude of the modulation and demodulation signal;
an integrator for generating a comparison reference voltage from the received difference value;
a dynamic comparator configured to: the inverting input end is grounded, the non-inverting input end is connected with the comparison reference voltage, and the output end outputs the modulation and demodulation signal. The delta-sigma modulator module adopts a single-ring first-order structure so as to facilitate the speed reduction and the precision improvement of the delta-sigma modulator.
In one embodiment, the SoC architecture for arc detection further comprises:
and the distributed temperature sensing module is connected with the acquisition front end and used for monitoring the temperature change of the framework at the corresponding position in the working process so as to realize temperature compensation. So as to monitor the temperature change of the corresponding position of the system in the working process and realize the quantitative output of the temperature.
In one embodiment, the distributed temperature sensing module includes: a first transistor configured to: the source electrode is grounded, and the grid electrode is connected with a first direct current power supply;
a second transistor configured to: the source electrode is grounded, and the drain electrode is connected with the grid electrode of the first transistor;
a third transistor configured to: the source electrode is grounded, and the drain electrode is connected with a second direct current power supply;
a fourth transistor configured to: the source electrode is connected with the drain electrode of the second transistor, the drain electrode is connected with the grid electrode, and the grid electrode is connected with the grid electrode of the second transistor;
a fifth transistor configured to: the source electrode is connected with the drain electrode of the third transistor, the drain electrode is connected with the grid electrode, and the grid electrode is connected with the grid electrode of the third transistor;
a sixth transistor configured to: the drain electrode is connected with the drain electrode of the first transistor;
a seventh transistor configured to: the source electrode of the fourth transistor is connected with the source electrode of the sixth transistor, the drain electrode of the fourth transistor is connected with the drain electrode of the fourth transistor, and the grid electrode of the fourth transistor is connected with the grid electrode of the sixth transistor;
an eighth transistor configured to: and the source electrode is connected with the source electrode of the seventh transistor, the drain electrode is connected with the drain electrode of the fifth transistor, and the grid electrode is connected with the grid electrode of the seventh transistor.
In one embodiment, the SoC architecture for arc detection further comprises:
the reset circuit is connected with the microcontroller and is used for resetting the microcontroller to an initial state; and/or
And the phase-locked loop circuit is connected with the microcontroller and is used for setting the main clock frequency of the microcontroller by configuring the frequency dividing ratio of the register. The reset circuit is used for restoring the framework to the original state so as to ensure the stable and reliable work of the framework, and the phase-locked loop circuit is used for realizing a stable and high-frequency clock signal.
In one embodiment, the SoC architecture for arc detection further comprises:
and the low dropout regulator is used for providing working electric energy. So as to provide a stable dc voltage supply.
Another aspect of the present application provides an arc detection apparatus comprising any of the architectures described in the embodiments of the present application.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
Fig. 1 is a schematic structural diagram of an SoC architecture for arc detection provided in a first embodiment;
fig. 2 is a schematic structural diagram of an SoC architecture for arc detection provided in a second embodiment;
fig. 3 is a schematic structural diagram of a SAR ADC provided in an embodiment of the present invention;
fig. 4 is a schematic structural diagram of an SoC architecture for arc detection provided in the third embodiment;
FIG. 5 is a schematic diagram of a comparator structure provided in an embodiment of the present invention;
fig. 6 is a graph of a SAR ADC power spectrum test result provided in an embodiment of the present invention;
fig. 7 is a schematic structural diagram of an SoC architecture for arc detection provided in the fourth embodiment;
fig. 8 is a schematic structural diagram of a delta-sigma modulator provided in an embodiment of the present invention;
FIG. 9 is a graph of the results of a sigma-delta ADC power spectrum test provided in an embodiment of the present invention;
fig. 10 is a schematic structural diagram of an SoC architecture for arc detection provided in the fifth embodiment;
fig. 11 is a schematic structural diagram of a distributed temperature sensing module according to an embodiment of the present invention;
fig. 12 is a measurement result diagram of a distributed temperature sensing module according to an embodiment of the present invention;
fig. 13 is a schematic structural diagram of an SoC architecture for arc detection provided in the sixth embodiment;
FIG. 14 is a block diagram of a test system according to an embodiment of the present invention;
description of reference numerals:
100. collecting a front end; 200. a microcontroller; 300. a memory; 120. a Nyquist analog-to-digital converter; 122. a sampling switch; 124. a comparator; 126. a capacitive array digital-to-analog converter; 1242. a pre-amplification unit; 1244. a latch comparison unit; 140. a sigma-delta analog-to-digital converter; 142. a delta-sigma modulator module; 144. a digital down-sampling filtering module; 1422. a subtractor; 1424. an integrator; 1426. a dynamic comparator; 400. distributed temperature sensing module.
Detailed Description
To facilitate an understanding of the present application, the present application will now be described more fully with reference to the accompanying drawings. Embodiments of the present application are set forth in the accompanying drawings. This application may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the description of the present application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.
It will be understood that, as used herein, the terms "first," "second," and the like may be used herein to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish one element from another.
It will be understood that when an element is referred to as being "connected" to another element, it can be directly connected to the other element or be connected to the other element through intervening elements. Further, "connection" in the following embodiments is understood to mean "electrical connection", "communication connection", or the like, if there is a transfer of electrical signals or data between the connected objects.
When an arc fault occurs in the line, it is likely to cause a fire by spraying high temperature particles or high temperature gas to ignite surrounding combustibles. The cause of arc faults, the damage caused and countermeasures have been intensively studied from the 90 s internationally. However, due to the complexity of arc faults, there is no reliable method for fully detecting and protecting arc faults. Most of domestic and foreign researches are around arc identification methods for research and analysis, such as time domain and frequency domain characteristics, wavelet analysis, neural networks, fault identification based on fusion technology of certain or some characteristics of series arc current and overall characteristics, and the like, and are based on arc detection system on chip (SoC) hardware platforms. With the development of the nano-scale CMOS process, a large-scale integrated circuit is rapidly developed and applied, and the independent research and design of the special power SoC for arc detection has very important significance. The invention designs an SoC hardware system for arc detection aiming at arc detection, and researches a fault arc by sampling an electric signal taken out from a power grid and then performing software analysis and arc identification processing.
The acquisition front end 100 is used for sampling an electric signal in a power grid, acquiring initial sampling data, and processing the initial sampling data to obtain target sampling data including a fault arc; the memory 300 is used for storing programs and data, the programs including a user program and a boot program; the microcontroller 200 is configured to respond to a start instruction, control a user program in an external storage space to be stored in a first preset position in the memory 300, and control target sampling data in a preset sampling mode to be stored in a second preset position in the memory 300 according to the program.
By way of example, with continued reference to fig. 1, the overall Architecture Bus employs an AMBA Bus (Advanced Microcontroller Bus Architecture, on-chip Bus protocol), and in the embodiment of the present invention, the Bus employs a two-level Bus interconnection structure of an AHB (Advanced High-performance Bus) and an APB (Advanced Peripheral Bus). The Advanced eXtensible Interface (AXI) bus is an early version of an AXI bus, has relatively low performance but low power consumption, and is suitable for the low-power consumption requirement of the system. The microcontroller 200 adopts a CK 80332-bit CPU, and the working frequency can reach 120MHz at most. The CKCPU adopts an embedded CPU of an AMBA/AXI interface independently designed by Hangzhou Zhongtian micro system company, the CK803 has the performance similar to ARM Cortex-M3, and is a 32-bit high-energy-efficiency embedded CPU core oriented to the control field, and the CKCPU has the characteristics of low cost, low power consumption, high code density and the like. An 16/32-bit mixed coding instruction system is adopted, and a simplified and efficient 3-stage pipeline is designed. The Memory 300 includes a 32KB SRAM (Static Random-Access Memory), an 8KB SRAM, and a 2KB ROM (Read-Only Memory), where the SRAM is used as a user program and a data storage space, the ROM is used to store a bootstrap program of the SoC, the user program can be stored in a first preset position in the Memory 300 when the ROM is used, and then the user program in the first preset position in the Memory 300 is loaded into a second preset position in the Memory 300 through a Serial Peripheral Interface (SPI) bus during a framework startup process, and the program can be directly downloaded into the SRAM through a Joint Test Action Group (JTAG) during actual debugging.
By way of example, referring to fig. 2, in one embodiment of the present application, the acquisition front end 100 includes a nyquist analog-to-digital converter 120, the nyquist analog-to-digital converter 120 including a sampling switch 122, a comparator 124, and a capacitive array digital-to-analog converter 126. The nyquist adc 120 adopts a successive approximation type analog-to-digital converter structure, the basic structure is as shown in fig. 3, and the input end of the sampling switch 122 is connected to a common mode voltage; the inverting input terminal of the comparator 124 is connected to the output terminal of the sampling switch 122, the non-inverting input terminal is connected to the common-mode voltage, and the output terminal is used for outputting the target sampling data; a capacitor array digital-to-analog converter 126 including a capacitor array and a plurality of switches, each of the switches including an output terminal connected to a corresponding capacitor, and a first input terminal, a second input terminal, and a third input terminal; the first input terminal is connected with reference voltage, the second input terminal is connected with signal voltage, the third input terminal is connected with a grounding wire, the capacitor array adopts a 10-bit binary single-ended structure, the bottom plate samples, and the control switch adopts a transmission gate. The successive approximation type analog-to-digital converter is widely applied to the field of medium and low speed application due to simple structure, few analog modules, small area and low power consumption. In order to achieve a sampling rate of 1M.
For example, referring to fig. 4, in an embodiment of the present application, the second preset location includes a register, and the comparator 124 includes a pre-amplifying unit 1242 and a latch comparing unit 1244. Compared with the static comparator 124, the comparator 124 has low power consumption, and the structure is shown in fig. 5, a first input terminal of the pre-amplification unit 1242 is connected to the common-mode voltage, a second input terminal is connected to the output terminal of the sampling switch 122, a third input terminal is connected to the first clock signal, a first output terminal is used for outputting a first differential signal, and a second output terminal is used for outputting a second differential signal; the latch comparing unit 1244 is connected to the pre-amplifying unit 1242, and has a first input end connected to the first differential signal, a second input end connected to the second differential signal, and an output end for outputting the target sampling data. The grid electrode of the ninth transistor is connected with the first input end; the grid electrode of the tenth transistor is connected with the second input end, and the source electrode of the tenth transistor is connected with the source electrode of the ninth transistor; the source electrode of the eleventh transistor is grounded, and the drain electrode of the eleventh transistor is connected with the source electrode of the tenth transistor; the grid electrode of the twelfth transistor is connected with the first clock signal, the source electrode of the twelfth transistor is grounded, and the drain electrode of the twelfth transistor is connected with the first output end; the grid electrode of the thirteenth transistor is connected with the second output end, the source electrode of the thirteenth transistor is grounded, and the drain electrode of the thirteenth transistor is connected with the drain electrode of the twelfth transistor; the grid electrode of the fourteenth transistor is connected with the drain electrode of the thirteenth transistor, the source electrode of the fourteenth transistor is grounded, and the drain electrode of the fourteenth transistor is connected with the grid electrode of the thirteenth transistor; a grid electrode of the fifteenth transistor is connected with the grid electrode of the twelfth transistor, a source electrode of the fifteenth transistor is grounded, and a drain electrode of the fifteenth transistor is connected with the drain electrode of the fourteenth transistor; the source electrode of the sixteenth transistor is connected with the grid electrode of the fifteenth transistor, and the drain electrode of the sixteenth transistor is connected with the drain electrode of the ninth transistor; a gate of the seventeenth transistor is connected with a gate of the sixteenth transistor, a source of the seventeenth transistor is connected with a source of the sixteenth transistor, and a drain of the seventeenth transistor is connected with a drain of the tenth transistor; the grid electrode of the eighteenth transistor is connected with the drain electrode of the sixteenth transistor, and the drain electrode of the eighteenth transistor is connected with the grid electrode of the fourteenth transistor; the grid electrode of the nineteenth transistor is connected with the drain electrode of the fifteenth transistor, and the drain electrode of the nineteenth transistor is connected with the source electrode of the eighteenth transistor; the grid electrode of the twentieth transistor is connected with the drain electrode of the eighteenth transistor, and the source electrode of the twentieth transistor is connected with the source electrode of the nineteenth transistor; and the grid electrode of the twenty-first transistor is connected with the drain electrode of the seventeenth transistor, the source electrode of the twenty-first transistor is connected with the drain electrode of the twentieth transistor, and the drain electrode of the twenty-first transistor is connected with the grid electrode of the nineteenth transistor. The ninth transistor, the tenth transistor, the eleventh transistor, the twelfth transistor, the thirteenth transistor, the fourteenth transistor and the fifteenth transistor are all PMOS transistors, and the sixteenth transistor, the seventeenth transistor, the eighteenth transistor, the nineteenth transistor, the twentieth transistor and the twenty-first transistor are all NMOS transistors.
The microcontroller 200 is configured to: in the first clock cycle of the first clock signal, controlling the comparator 124 to successively compare the highest bit 1 of the register, instructing the capacitor array dac 126 to output a corresponding voltage to the inverting input terminal of the comparator 124, and controlling the comparator 124 to compare the voltage received at the inverting input terminal thereof with the common mode voltage; if the common mode voltage is greater than the voltage received by the inverting input terminal, the comparator 124 is controlled to output 1, otherwise, the highest position of the register is set to 0; in the second clock cycle of the first clock signal, the next-highest position 1 of the register is used to instruct the capacitor array dac 126 to output a corresponding voltage to the inverting input terminal of the comparator 124, so as to control the comparator 124 to compare the received voltages and output a corresponding comparison result. The invention adopts 10bit SAR ADC, 1MHz sampling rate, and the test result obtained by importing the data obtained by test into MATLAB for spectrum analysis is shown in figure 6, and the result shows that the actual effective digit is about 6 bits. The detailed test results are shown in table 1.
TABLE 1
Referring to fig. 7 as an example, in an embodiment of the present application, the acquisition front end 100 includes a sigma-delta analog-to-digital converter 140, and the sigma-delta analog-to-digital converter 140 includes a delta-sigma modulator module 142 and a digital down-sampling filter module 144. The input end of the delta-sigma modulator module 142 is connected with the signal voltage, and the output end outputs a modulation and demodulation signal; and a digital down-sampling filtering module 144, connected to the delta-sigma modulator module 142, for decimating and filtering the modulation and demodulation signal and outputting the target sampling data. The delta-sigma modulator module 142 includes a subtractor 1422, an integrator 1424, and a dynamic comparator 1426. The input end of the subtractor 1422 is connected to both the signal voltage and the modem signal, and is configured to calculate a difference between the signal voltage and the voltage amplitude of the modem signal; the integrator 1424 is configured to generate a comparison reference voltage according to the received difference, and the switched capacitor type integrator 1424 formed by a single-ended cascode operational amplifier is widely applied to a low-speed high-precision delta-sigma modulator; the inverting input terminal of the dynamic comparator 1426 is grounded, the non-inverting input terminal is connected to the comparison reference voltage, and the output terminal outputs the modulation and demodulation signal, which also adopts the structure shown in fig. 5. Unlike the nyquist adc 120 described above, oversampling is to sample the input signal using a frequency much greater than the nyquist sampling frequency, so that quantization noise within the system band is reduced. Meanwhile, the noise shaping technology is applied, so that the noise in a low-frequency band is greatly reduced, most quantization noise is pushed to a higher frequency band, and thus, a low-pass filter is added behind a delta-sigma modulator, so that the quantization noise outside a signal bandwidth can be effectively filtered, and the system performance is greatly improved. Wherein the delta-sigma modulator module 142 employs a single-loop first-order structure, as shown in fig. 8. The digital down-sampling module mainly utilizes hardware description language to construct a CIC decimation filter, and performs decimation filtering on the output of the modulator to finally obtain digital codes. The digital code obtained by the test is introduced into MATLAB software for spectral analysis to obtain the test result shown in fig. 9. The significance was 8.67 bits and the detailed test results are shown in table 2. The test results in tables 1 and 2 show that the accuracy of the ADC can process the electrical signal, thereby achieving the function of arc detection.
TABLE 2
As an example, referring to fig. 10, in one embodiment, the SoC architecture for arc detection further includes a distributed temperature sensing module 400, connected to the acquisition front end 100, for monitoring temperature variation of the architecture at a corresponding position during operation to implement temperature compensation. So as to monitor the temperature change of the corresponding position of the system in the working process and realize the quantitative output of the temperature. The traditional temperature sensor realizes the temperature sensing function by utilizing the temperature characteristic of a Bipolar Junction Transistor (BJT), and has large area and high power consumption although the accuracy is high and the linearity is good. The full digital temperature sensor based on the MOSFETS has a small area and low power consumption, and is suitable for the distributed temperature sensing module 400 in the present design. The structure of the distributed temperature sensing module 400 is shown in fig. 11. The distributed temperature sensing module 400 includes: a first transistor configured to: the source electrode is grounded, and the grid electrode is connected with a first direct current power supply; a second transistor configured to: the source electrode is grounded, and the drain electrode is connected with the grid electrode of the first transistor; a third transistor configured to: the source electrode is grounded, and the drain electrode is connected with a second direct current power supply; a fourth transistor configured to: the source electrode is connected with the drain electrode of the second transistor, the drain electrode is connected with the grid electrode, and the grid electrode is connected with the grid electrode of the second transistor; a fifth transistor configured to: the source electrode is connected with the drain electrode of the third transistor, the drain electrode is connected with the grid electrode, and the grid electrode is connected with the grid electrode of the third transistor; a sixth transistor configured to: the drain electrode is connected with the drain electrode of the first transistor; a seventh transistor configured to: the source electrode of the fourth transistor is connected with the source electrode of the sixth transistor, the drain electrode of the fourth transistor is connected with the drain electrode of the fourth transistor, and the grid electrode of the fourth transistor is connected with the grid electrode of the sixth transistor; an eighth transistor configured to: and the source electrode is connected with the source electrode of the seventh transistor, the drain electrode is connected with the drain electrode of the fifth transistor, and the grid electrode is connected with the grid electrode of the seventh transistor. The first transistor, the second transistor, the third transistor, the fourth transistor and the fifth transistor are all PMOS tubes, and the sixth transistor, the seventh transistor and the eighth transistor are all NMOS tubes.
The distributed temperature sensing module 400 employs differential output, which not only enhances the resistance to power noise, but also improves the linearity of the temperature characteristic curve. The layout of the eight temperature sensors refers to the implementation form of the digital standard unit, is compatible with the digital automatic layout and wiring process, can be embedded into a digital standard unit row with any equal height, has the area equivalent to that of a common standard unit, and hardly consumes static current. The temperature sensor is connected to the ADC front end to realize quantized output of temperature. As shown in the test result of fig. 12, in the range from-10 ℃ to 70 ℃, the area of the temperature sensing unit of the temperature sensor is only 24.08 square micrometers, and the maximum measurement error is-1.25 ℃/+2 ℃, which is enough to monitor the temperature change of the framework at different positions in the working process, so that the temperature compensation can be realized.
As an example, please refer to fig. 13, in one embodiment, the SoC architecture for arc detection further includes a reset circuit and a phase-locked loop circuit. The reset circuit is connected with the microcontroller 200 and is used for resetting the microcontroller 200 to an initial state; the phase-locked loop circuit is connected to the microcontroller 200, and is configured to set a main clock frequency of the microcontroller 200 by configuring a frequency division ratio of the register. The reset circuit is used for restoring the framework to the original state so as to ensure the stable and reliable work of the framework, and the phase-locked loop circuit is used for realizing a stable and high-frequency clock signal. In one embodiment, the architecture further comprises four timers for single overflow triggered interrupts or cycle overflow triggered interrupts; the debugging interface comprises a Watchdog, a GPIO (General-purpose input/output) and a JTAG debugging interface; the communication interface comprises a UART (Universal Asynchronous Receiver/Transmitter, which uses an Asynchronous transceiver Transmitter) interface and an SPI interface, the SPI interface is used for transmitting a program stored in an external FLASH framework into an SRAM when a system is guided from a ROM, and the SPI interface can be used as a common SPI bus after the system is guided; two paths of PWM (Pulse width modulation) signals are used for realizing the speed regulation/inversion of the motor. In one embodiment, the architecture further comprises a low dropout regulator for providing operating power. So as to provide a stable dc voltage supply. In one embodiment, the SoC software development environment for arc detection uses the Zhongtian C-SKY CPU software development kit CDS Release V4.3. And the CDS Workbench is used for compiling the program written by the C language and downloading the compiled executable file to the CK CPU for debugging and running. CDS Workbench is based on Eclipse quadratic development, similar to many ARM/Xilinx development tool interfaces. The method of use is essentially the same. When software is downloaded and debugged, a CK CPU downloader is required to be connected with a JTAG interface of the SoC through the JTAG interface.
After the Design of a system Register Transfer Level (RTL), the integration of IP and the functional simulation verification are completed, a Design Compiler tool is used for synthesizing the RTL to obtain a gate-Level netlist of a corresponding process and the simulation after the synthesis is completed. If the simulation has problems, the simulation may need to be modified and resynthesized on the synthesized constraint or the RTL is modified and then resynthesized until the simulation is verified to be correct. And performing comprehensive simulation, and then, utilizing Innovus software to lay out and route the system. The architecture is first sized, the location and number of PADs determined, and the placement of the various IPs. And then planning a power grid, laying out the digital units, designing a clock tree, and finally performing wiring optimization and adding virtualization to meet the requirement of DRC (Design Rule Check) on density. By looking at the timing report to ensure that the timing meets the requirements. And finally, verifying the design, performing time sequence denotation post-simulation after verifying DRC (design rule, verification of the identity of the Layout and the circuit diagram) and LVS (Layout rule, verification of the identity of the Layout and the circuit diagram) and ANTENNA (anti-routing), if the simulation has problems, re-performing Layout and wiring and post-verification, and delivering the tape-out after confirming that the simulation is correct.
By way of example, referring to FIG. 14, in one embodiment, a test system includes a PC, a JTAG downloader, a DC regulator, a signal generator, and a UART-to-USB module; the PC is connected with a JTAG debugging interface of the SoC system through a JTAG downloader and is connected with a UART interface of the SoC system through a UART-to-USB module; the direct current voltage stabilizing source is used for providing voltage for the SoC system; the signal generator is used for providing sine wave input to an ADC (analog to digital converter) of the SoC system. The test process comprises the following steps: the method comprises the steps of debugging on line through a JTAG downloader, configuring a measurement mode of a Nyquist analog-to-digital converter and an oversampling analog-to-digital converter through compiling C language, storing data obtained by ADC sampling into an SRAM of an SoC system in a continuous sampling mode, transmitting ADC sampling results stored in the SRAM to a PC through a UART-to-USB interface after accessing a certain number of data, storing or printing the data obtained by the UART interface through python processing, and importing the stored data into Matlab to perform spectrum analysis processing on the data.
In the description herein, references to the description of "some embodiments," "other embodiments," "desired embodiments," etc., mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, a schematic description of the above terminology may not necessarily refer to the same embodiment or example.
The technical features of the above embodiments can be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the above embodiments are not described, but should be considered as the scope of the present specification as long as there is no contradiction between the combinations of the technical features.
The above-mentioned embodiments only express several embodiments of the present application, and the description thereof is more specific and detailed, but not construed as limiting the scope of the invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the concept of the present application, which falls within the scope of protection of the present application. Therefore, the protection scope of the present patent shall be subject to the appended claims.
Claims (10)
1. An SoC architecture for arc detection for sampling electrical signals in an electrical grid and obtaining target sampling data for identifying a fault arc, the SoC architecture comprising:
the system comprises an acquisition front end, a fault detection front end and a fault detection front end, wherein the acquisition front end is used for sampling an electric signal in a power grid, acquiring initial sampling data, and processing the initial sampling data to obtain target sampling data comprising a fault arc;
a memory for storing programs and data, the programs including a user program and a bootstrap program;
the microcontroller is electrically connected with the memory and the acquisition front end and used for responding to a starting instruction and controlling a user program in an external storage space to be stored to a first preset position in the memory; and controlling the target sampling data under the preset sampling mode to be stored in a second preset position in the memory according to the program.
2. The SoC architecture for arc detection of claim 1, wherein the acquisition front end comprises a nyquist analog-to-digital converter; the Nyquist analog-to-digital converter includes:
a sampling switch configured to: the input end is connected with a common mode voltage;
a comparator configured to: the reverse-phase input end is connected with the output end of the sampling switch, the normal-phase input end is connected with the common-mode voltage, and the output end is used for outputting the target sampling data;
the capacitive array digital-to-analog converter comprises a capacitive array and a plurality of change-over switches, wherein each change-over switch comprises an output terminal, a first input terminal, a second input terminal and a third input terminal which are connected with a corresponding capacitor; the first input terminal is connected to a reference voltage, the second input terminal is connected to a signal voltage, and the third input terminal is connected to a ground line.
3. The SoC architecture for arc detection of claim 2, wherein the second preset location comprises a register; the comparator includes:
a pre-amplification unit configured to: the first input end is connected with the common-mode voltage, the second input end is connected with the output end of the sampling switch, the third input end is connected with the first clock signal, the first output end is used for outputting a first differential signal, and the second output end is used for outputting a second differential signal;
a latch compare unit connected to the pre-amplification unit and configured to: the first input end is connected with the first differential signal, the second input end is connected with the second differential signal, and the output end is used for outputting the target sampling data;
the microcontroller is configured to:
in a first clock cycle of the first clock signal, controlling the comparator to successively compare the highest position 1 of the register, instructing the capacitor array digital-to-analog converter to output a corresponding voltage to an inverting input end of the comparator, and controlling the comparator to compare a voltage received by the inverting input end of the comparator with the common-mode voltage; if the common mode voltage is larger than the voltage received by the reverse input end, controlling the comparator to output 1, otherwise, enabling the highest position of the register to be 0;
and in the second clock cycle of the first clock signal, indicating the second highest position 1 of the register to output a corresponding voltage to the inverting input end of the comparator by the capacitor array digital-to-analog converter, and controlling the comparator to compare the received voltage and output a corresponding comparison result.
4. The SoC architecture for arc detection of claim 1, wherein the acquisition front end comprises a sigma-delta analog-to-digital converter; the sigma-delta analog-to-digital converter comprises:
a delta-sigma modulator module configured to: the input end is connected with signal voltage, and the output end outputs a modulation and demodulation signal;
and the digital down-sampling filtering module is connected with the delta-sigma modulator module and is used for extracting and filtering the modulation and demodulation signals and outputting the target sampling data.
5. The SoC architecture for arc detection of claim 4, wherein the delta-sigma modulator module comprises:
a subtractor configured to: the input end is connected with both the signal voltage and the modulation and demodulation signal and is used for calculating the difference value of the signal voltage and the voltage amplitude of the modulation and demodulation signal;
an integrator for generating a comparison reference voltage from the received difference value;
a dynamic comparator configured to: the inverting input end is grounded, the non-inverting input end is connected with the comparison reference voltage, and the output end outputs the modulation and demodulation signal.
6. The SoC architecture for arc detection of any of claims 1-5, further comprising:
and the distributed temperature sensing module is connected with the acquisition front end and used for monitoring the temperature change of the framework at the corresponding position in the working process so as to realize temperature compensation.
7. The SoC architecture for arc detection of claim 6, wherein the distributed temperature sensing module comprises: a first transistor configured to: the source electrode is grounded, and the grid electrode is connected with a first direct current power supply;
a second transistor configured to: the source electrode is grounded, and the drain electrode is connected with the grid electrode of the first transistor;
a third transistor configured to: the source electrode is grounded, and the drain electrode is connected with a second direct current power supply;
a fourth transistor configured to: the source electrode is connected with the drain electrode of the second transistor, the drain electrode is connected with the grid electrode, and the grid electrode is connected with the grid electrode of the second transistor;
a fifth transistor configured to: the source electrode is connected with the drain electrode of the third transistor, the drain electrode is connected with the grid electrode, and the grid electrode is connected with the grid electrode of the third transistor;
a sixth transistor configured to: the drain electrode is connected with the drain electrode of the first transistor;
a seventh transistor configured to: the source electrode of the fourth transistor is connected with the source electrode of the sixth transistor, the drain electrode of the fourth transistor is connected with the drain electrode of the fourth transistor, and the grid electrode of the fourth transistor is connected with the grid electrode of the sixth transistor;
an eighth transistor configured to: and the source electrode is connected with the source electrode of the seventh transistor, the drain electrode is connected with the drain electrode of the fifth transistor, and the grid electrode is connected with the grid electrode of the seventh transistor.
8. The SoC architecture for arc detection of any of claims 3-5, further comprising:
the reset circuit is connected with the microcontroller and is used for resetting the microcontroller to an initial state; and/or
And the phase-locked loop circuit is connected with the microcontroller and is used for setting the main clock frequency of the microcontroller by configuring the frequency dividing ratio of the register.
9. The SoC architecture for arc detection of any of claims 1-5, further comprising:
and the low dropout regulator is used for providing working electric energy.
10. An arc detection device is characterized in that,
the method comprises the following steps:
the architecture of any one of claims 1-10.
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