CN115617115A - Reference voltage generating circuit, chip and electronic device - Google Patents

Reference voltage generating circuit, chip and electronic device Download PDF

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Publication number
CN115617115A
CN115617115A CN202211344115.3A CN202211344115A CN115617115A CN 115617115 A CN115617115 A CN 115617115A CN 202211344115 A CN202211344115 A CN 202211344115A CN 115617115 A CN115617115 A CN 115617115A
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transistor
current
reference voltage
source
circuit
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CN115617115B (en
Inventor
赵东艳
李明节
王于波
李振国
原义栋
胡毅
赵天挺
侯佳力
王亚彬
苏萌
刘宇
常乃超
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State Grid Corp of China SGCC
Beijing Smartchip Microelectronics Technology Co Ltd
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State Grid Corp of China SGCC
Beijing Smartchip Microelectronics Technology Co Ltd
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Publication of CN115617115B publication Critical patent/CN115617115B/en
Priority to PCT/CN2023/122790 priority patent/WO2024093602A1/en
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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
    • G05F3/02—Regulating voltage or current
    • G05F3/08—Regulating voltage or current wherein the variable is dc
    • G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
    • G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
    • G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
    • G05F3/26—Current mirrors
    • G05F3/262—Current mirrors using field-effect transistors only

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Electromagnetism (AREA)
  • General Physics & Mathematics (AREA)
  • Radar, Positioning & Navigation (AREA)
  • Automation & Control Theory (AREA)
  • Control Of Electrical Variables (AREA)

Abstract

The present disclosure relates to the field of integrated circuit technology, and in particular, to a reference voltage generating circuit, a chip, and an electronic device, wherein the reference voltage generating circuit includes: a reference voltage generation circuit for generating a first reference voltage; voltage stabilizing circuit, voltage stabilizing circuit includes voltage conversion circuit, source current steady voltage branch road and irritates current steady voltage branch road, wherein: the voltage conversion circuit is used for converting the first reference voltage into the reference voltage, converting the reference voltage into a first control voltage when the reference voltage generation circuit receives an external source current, and converting the reference voltage into a second control voltage when the reference voltage generation circuit receives an external sink current; the source current voltage stabilizing branch circuit receives the first control voltage, and the sink current voltage stabilizing branch circuit receives the second control voltage to stabilize the reference voltage, so that the reliability of the circuit is improved.

Description

Reference voltage generating circuit, chip and electronic device
Technical Field
The disclosure relates to the technical field of integrated circuits, in particular to a reference voltage generating circuit, a chip and electronic equipment.
Background
Reference voltage generation circuits such as bandgap reference sources are widely used in integrated circuits to provide a voltage independent of process, voltage and temperature, and the voltage can be used in modules and chips such as data converters, reference voltage sources, and large-scale digital System on a Chip (SoC).
In a high-precision data acquisition system in the industrial field, the sampling precision and the sampling precision of a chip depend on a high-precision reference source on the chip along with the load variation seriously, and in order to ensure that the amplitude of the absolute sampling precision along with the load variation is reduced when the chip works in a wide load range, a reference voltage generating circuit with source current and sink current at the same time needs to be developed urgently, so that the problem that the sampling precision is reduced because the reference voltage is changed due to the load variation faced by the high-precision sampling system is solved.
Disclosure of Invention
In order to solve the problems in the related art, embodiments of the present disclosure provide a reference voltage generating circuit, a chip and an electronic device.
In a first aspect, the disclosed embodiments provide a reference voltage generation circuit, a chip and an electronic device.
Specifically, the reference voltage generating circuit includes:
a reference voltage generation circuit for generating a first reference voltage that is invariant to process and temperature;
voltage stabilizing circuit, voltage stabilizing circuit includes voltage conversion circuit, source current steady voltage branch road and irritates current steady voltage branch road, wherein:
the voltage conversion circuit is used for converting the first reference voltage into the reference voltage, converting the reference voltage into a first control voltage when the reference voltage generation circuit receives an external source current, and converting the reference voltage into a second control voltage when the reference voltage generation circuit receives an external sink current, wherein the voltage conversion circuit comprises a first transistor MP5 and a second transistor MP6, the first transistor MP5 and the second transistor MP6 are connected by adopting a common gate, a source electrode of the first transistor MP5 is connected to the first reference voltage, a drain electrode of the first transistor MP5 is grounded through a third current source, and the third current source is a current source formed by mirroring the first current; the source electrode of the second transistor MP6 is connected to the reference voltage, and the drain electrode of the second transistor MP6 is connected to the input ends of the source current voltage stabilizing branch and the sink current voltage stabilizing branch;
the source current voltage stabilizing branch comprises a third transistor MN6 and a fourth transistor MP8, the source electrode of the third transistor MN6 is connected to the first control voltage, and the drain electrode of the fourth transistor MP8 is connected to the reference voltage, so that when the reference voltage generating circuit receives an external source current to cause the reference voltage to be reduced, the reference voltage is stabilized to a rated value;
the current-sinking voltage-stabilizing branch circuit comprises a fifth transistor MN7, wherein the grid electrode of the fifth transistor MN7 is connected to the second control voltage, and the drain electrode of the fifth transistor MN7 is connected to the reference voltage, so that when the reference voltage generating circuit receives external current sinking and the reference voltage is increased, the reference voltage is stabilized to a rated value.
In an embodiment of the disclosure, the reference voltage generation circuit is further configured to generate a first current.
In the embodiment of the present disclosure, the reference voltage generating circuit includes a first bipolar transistor Q1, a second bipolar transistor Q2, a third bipolar transistor Q3, a first resistor R1, a second resistor R2, and a first current mirror circuit; wherein the content of the first and second substances,
the first bipolar transistor Q1, the second bipolar transistor Q2, the third bipolar transistor Q3, the first resistor R1, and the second resistor R2 are used to generate the first reference voltage, and the first current mirror circuit is used to generate the first current.
In the embodiment of the present disclosure, the bases and the collectors of the first bipolar transistor Q1 and the second bipolar transistor Q2 are both grounded, the emitter of the first bipolar transistor Q1 is connected to the first input terminal of the first current mirror circuit, and the emitter of the second bipolar transistor Q2 is connected to the second input terminal of the first current mirror circuit through the first resistor R1;
the reference voltage generating circuit further comprises a second current source, the base electrode and the collector electrode of the third bipolar transistor Q3 are grounded, the emitter electrode is connected to the second current source and the source electrode of the first transistor MN5 through the second resistor, the second current source is a current source formed by twice mirroring of the first current, and the other end of the second current source is connected to the power supply voltage.
In the embodiment of the present disclosure, the first transistor MP5 and the second transistor MP6 have the same feature size.
In this disclosure, the drain of the second transistor MP6 is further connected to a fourth current source, the fourth current source is formed by twice mirroring the first current, and the other end of the fourth current source is grounded.
In the embodiment of the present disclosure, the gate of the third transistor MN6 is connected to a first bias voltage, the drain is connected to the gate of the fourth transistor MP8, and the source of the fourth transistor MP8 is connected to a power supply voltage;
the source of the fifth transistor MN7 is grounded.
In the embodiment of the present disclosure, the drain of the third transistor MN6 is further connected to a fifth current source, where the fifth current source is formed by mirroring the first current by one time, and the other end of the fifth current source is connected to a power supply voltage.
In the disclosed embodiment, the first bias voltage is generated by a bias branch, which includes a sixth current source, a sixth transistor MN8, and a seventh transistor MN9;
the sixth current source is a current source formed by mirroring the first current, one end of the sixth current source is connected to a power supply voltage, and the other end of the sixth current source is connected to the first bias voltage and the drain of the sixth transistor MN 8;
the grid drain of the sixth transistor MN8 is in short circuit, and the source electrode of the sixth transistor MN8 is connected to the drain electrode of the seventh transistor MN9;
and the grid drain of the seventh transistor MN9 is in short circuit, and the source electrode is grounded.
In the embodiment of the disclosure, the first current mirror circuit includes an eighth transistor MN1, a ninth transistor MN2, a tenth transistor MP1, and an eleventh transistor MP2, a source of the eighth transistor MN1 is a first input terminal of the first current mirror, a source of the ninth transistor MN2 is a second input terminal of the first current mirror, a gate-drain of the eighth transistor MN1 is shorted, and is connected to a gate of the ninth transistor MN2 and a drain of the tenth transistor MP1, a gate-drain of the eleventh transistor MP2 is shorted, and is connected to a gate of the tenth transistor MP1 and a drain of the ninth transistor MN2, and sources of the tenth transistor MP1 and the eleventh transistor MP2 are both connected to a power supply voltage.
In the embodiment of the present disclosure, the second current source includes a twelfth transistor MP3, a gate of the twelfth transistor MP3 is connected to a gate of the eleventh transistor MP2, a drain of the twelfth transistor MP3 is connected to the second resistor R2, and a source of the twelfth transistor MP3 is connected to the power supply voltage.
In the embodiment of the present disclosure, the third current source includes a thirteenth transistor MP4, a fourteenth transistor MN3, and a fifteenth transistor MN4, wherein a gate of the thirteenth transistor MP4 is connected to a gate of the twelfth transistor MP3, a drain of the thirteenth transistor MP4 is connected to a drain of the fourteenth transistor MN3, and a source of the thirteenth transistor MP4 is connected to the power supply voltage; the gate-drain of the fourteenth transistor MN3 is shorted and connected to the gate of the fifteenth transistor MN4, the sources of the fourteenth transistor MN3 and the fifteenth transistor MN4 are both grounded, and the drain of the fifteenth transistor MN4 is connected to the drain of the first transistor MP5 as one end of a third current source.
In the embodiment of the present disclosure, the fourth current source includes a sixteenth transistor MN5, a gate of the sixteenth transistor MN5 is connected to a gate of the fifteenth transistor MN4, a drain of the sixteenth transistor MN5 is connected to the drain of the second transistor MP6 as one end of the fourth current source, and a source of the fourth current source is grounded.
In the embodiment of the present disclosure, the fifth current source includes a seventeenth transistor MP7, a gate of the seventeenth transistor MP7 is connected to the gate of the twelfth transistor MP2, one end of a drain of the fifth current source is connected to the drain of the third transistor MN6, and a source of the fifth current source is connected to the power supply voltage.
In the embodiment of the present disclosure, the sixth current source includes an eighteenth transistor MP9, a gate of the eighteenth transistor MP9 is connected to the gate of the twelfth transistor MP2, one end of a drain as the sixth current source is connected to the drain of the sixth transistor MN8, and a source is connected to the power voltage.
In the disclosed embodiment, the transistors MP1, MP2, MP4, MP7 and MP9 have the same feature size, the transistor MP3 has twice the feature size of the transistor MP1, the transistors MN3 and MN4 have the same feature size, and the transistor MN5 has twice the feature size of the transistor MN 3.
In a second aspect, an embodiment of the present disclosure provides a chip including the reference voltage generation circuit according to any one of the first aspect.
In a third aspect, the present disclosure provides an electronic device, which includes the chip according to the second aspect.
According to the technical scheme provided by the embodiment of the disclosure, the voltage stabilizing circuit which simultaneously comprises the source current voltage stabilizing branch and the sink current voltage stabilizing branch is additionally arranged in the reference voltage generating circuit, so that the reference voltage generating circuit can rapidly stabilize the reference voltage to a rated value when receiving the external source current to cause the reference voltage to be reduced and receiving the external sink current to cause the reference voltage to be increased, and the reliability of the circuit is improved.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure.
Drawings
Other features, objects, and advantages of the present disclosure will become more apparent from the following detailed description of non-limiting embodiments when taken in conjunction with the accompanying drawings. In the drawings.
Fig. 1 is a block diagram showing a reference voltage generating circuit in the prior art.
Fig. 2 illustrates a block diagram of a reference voltage generating circuit according to an embodiment of the present disclosure.
Fig. 3 shows a block diagram of a reference voltage generating circuit according to an embodiment of the present disclosure.
Fig. 4 shows a block diagram of an electronic device according to an embodiment of the present disclosure.
Fig. 5 shows a block diagram of a chip according to an embodiment of the disclosure.
Detailed Description
Hereinafter, exemplary embodiments of the present disclosure will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily implement them. Also, for the sake of clarity, parts not relevant to the description of the exemplary embodiments are omitted in the drawings.
In the present disclosure, it is to be understood that terms such as "including" or "having," etc., are intended to indicate the presence of the disclosed features, numerals, steps, actions, components, parts, or combinations thereof in the specification, and are not intended to preclude the possibility that one or more other features, numerals, steps, actions, components, parts, or combinations thereof are present or added.
It should be further noted that the embodiments and features of the embodiments in the present disclosure may be combined with each other without conflict. The present disclosure will be described in detail below with reference to the accompanying drawings in conjunction with embodiments.
In order to ensure that the sampling precision and the sampling precision of the chip are seriously dependent on the high-precision reference source on the chip along with the load variation in the high-precision data acquisition system in the industrial field, and reduce the amplitude of the absolute sampling precision along with the load variation when the chip works in a wide load range, a reference voltage generating circuit with source current and sink current is urgently needed to be developed, so that the problem that the sampling precision is reduced due to the fact that the reference voltage is changed due to the load variation faced by the high-precision sampling system is solved.
Fig. 1 is a block diagram showing a reference voltage generating circuit in the prior art. As shown in FIG. 1, the circuit composed of the bipolar transistor, the resistor and the error amplifier can provide a band-gap reference voltage which is not changed with the process and the temperature, and the circuit also has certain forward driving capability due to the existence of the metal oxide field effect MOS transistor in the figure. Under the condition that the reference voltage generating circuit receives an external source current, the MOS tube can play a role in stabilizing voltage and quickly recover the reference voltage; however, under the condition that the reference voltage generating circuit receives an external sink current, the reference voltage can be repaired and stabilized only by the resistor, the recovery time is long, the voltage overshoot duration caused by the sink current is also long, adverse effects are easily caused on devices in the circuit, the service life of the devices is shortened, even the devices are damaged, and the reliability of the circuit is low.
In view of this, the embodiment of the present disclosure provides a reference voltage generating circuit, including: a reference voltage generation circuit for generating a first reference voltage that is invariant to process and temperature; voltage stabilizing circuit, voltage stabilizing circuit includes voltage conversion circuit, source current steady voltage branch road and irritates current steady voltage branch road, wherein: the voltage conversion circuit is used for converting the first reference voltage into the reference voltage, converting the reference voltage into a first control voltage when the reference voltage generation circuit receives an external source current, and converting the reference voltage into a second control voltage when the reference voltage generation circuit receives an external sink current; the source current stabilizing branch circuit receives the first control voltage to stabilize the reference voltage to a rated value when the reference voltage generating circuit receives an external source current to cause the reference voltage to be reduced; and the current-pouring voltage stabilizing branch circuit receives the second control voltage so as to stabilize the reference voltage to a rated value when the reference voltage generating circuit receives external pouring current and the reference voltage is increased. The voltage stabilizing circuit which simultaneously comprises the source current voltage stabilizing branch and the sink current voltage stabilizing branch is additionally arranged in the reference voltage generating circuit, so that the reference voltage generating circuit can quickly stabilize the reference voltage to a rated value when receiving the reduction of the reference voltage caused by the external source current and when receiving the increase of the reference voltage caused by the external sink current, and the reliability of the circuit is improved. Wherein the first control voltage is the same as the second control voltage.
Fig. 2 shows a block diagram of a reference voltage generating circuit according to an embodiment of the present disclosure.
As shown in fig. 2, the reference voltage generating circuit includes:
a reference voltage generation circuit for generating a first reference voltage that is invariant to process and temperature;
voltage stabilizing circuit, voltage stabilizing circuit includes voltage conversion circuit, source current steady voltage branch road and irritates current steady voltage branch road, wherein:
the voltage conversion circuit is used for converting the first reference voltage into the reference voltage, converting the reference voltage into a first control voltage when the reference voltage generation circuit receives an external source current, and converting the reference voltage into a second control voltage when the reference voltage generation circuit receives an external sink current, wherein the voltage conversion circuit comprises a first transistor MP5 and a second transistor MP6, the first transistor MP5 and the second transistor MP6 are connected by adopting a common gate, the source of the first transistor MP5 is connected to the first reference voltage, the drain of the first transistor MP5 is grounded through a third current source, and the third current source is a current source formed by mirroring the first current; the source electrode of the second transistor MP6 is connected to the reference voltage, and the drain electrode of the second transistor MP6 is connected to the input ends of the source current voltage stabilizing branch and the sink current voltage stabilizing branch;
the source current stabilizing branch comprises a third transistor MN6 and a fourth transistor MP8, the source electrode of the third transistor MN6 is connected to the first control voltage, and the drain electrode of the fourth transistor MP8 is connected to the reference voltage, so that when the reference voltage generating circuit receives an external source current to cause the reference voltage to be reduced, the reference voltage is stabilized to a rated value;
the current-sinking voltage-stabilizing branch circuit comprises a fifth transistor MN7, wherein the grid electrode of the fifth transistor MN7 is connected to the second control voltage, and the drain electrode of the fifth transistor MN7 is connected to the reference voltage, so that when the reference voltage generating circuit receives external current sinking and the reference voltage is increased, the reference voltage is stabilized to a rated value.
In the embodiment of the present disclosure, the reference voltage generating circuit may be a bandgap reference voltage generating circuit, and the reference voltage generating circuit generates a bandgap reference first reference voltage which does not vary with process and temperature. The reference voltage generating circuit can be a classical circuit composed of two bipolar transistors, a differential amplifier and a plurality of resistors as shown in fig. 1, and can also be an improved circuit of the classical circuit. The improved circuit will be described in detail later with reference to fig. 3.
If the first reference voltage generated by the reference voltage generation circuit is directly output as the reference voltage, when the output node receives an external pull circuit or a sink current, the output voltage of the output node is correspondingly reduced or pulled up, so that the output reference voltage deviates from the rated value thereof, and the stable reference voltage cannot be provided.
In view of this, in the embodiment of the disclosure, a voltage stabilizing circuit is further disposed in the reference voltage generating circuit, and the voltage stabilizing circuit includes a voltage converting circuit, a source current stabilizing branch, and a sink current stabilizing branch. The voltage conversion circuit is used for converting the first reference voltage into the reference voltage, converting the reference voltage into a first control voltage when the reference voltage generation circuit receives an external source current, and converting the reference voltage into a second control voltage when the reference voltage generation circuit receives an external sink current. The source current stabilizing branch circuit receives the first control voltage to stabilize the reference voltage to a rated value when the reference voltage generating circuit receives an external source current to cause the reference voltage to be reduced; and the current-pouring voltage stabilizing branch circuit receives the second control voltage so as to stabilize the reference voltage to a rated value when the reference voltage generating circuit receives external pouring current and the reference voltage is increased.
In the embodiment of the present disclosure, the rated value of the reference voltage refers to a value of the reference voltage that needs to be provided by the reference voltage generating circuit, and may be, for example, 3.3V, 1.8V, and the like, which is not limited herein.
In the embodiment of the disclosure, the source current voltage-stabilizing branch and the sink current voltage-stabilizing branch both include active devices to improve the responsiveness of the branches, and can stabilize the reference voltage reduced by the source current to the rated value and stabilize the reference voltage increased by the sink current to the rated voltage.
According to the technical scheme of the embodiment of the disclosure, the voltage stabilizing circuit which simultaneously comprises the source current voltage stabilizing branch and the sink current voltage stabilizing branch is additionally arranged in the reference voltage generating circuit, so that when the reference voltage generating circuit receives external source current and causes the reference voltage to be reduced and when the reference voltage is increased due to the received external sink current, the reference voltage can be rapidly stabilized to a rated value, and the reliability of the circuit is improved.
In the embodiment of the disclosure, the reference voltage generating circuit may be further configured to generate a first current, so that each branch in the voltage stabilizing circuit may set its own current source by mirroring the first current, thereby reducing a current deviation of each branch and further improving reliability of the circuit.
Fig. 3 illustrates a block diagram of a reference voltage generating circuit according to an embodiment of the present disclosure.
As shown in fig. 3, the reference voltage generating circuit may include a first bipolar transistor Q1, a second bipolar transistor Q2, a third bipolar transistor Q3, a first resistor R1, a second resistor R2, and a first current mirror circuit; the first bipolar transistor Q1, the second bipolar transistor Q2, the third bipolar transistor Q3, the first resistor R1, and the second resistor R2 are configured to generate the first reference voltage, and the first current mirror circuit is configured to generate the first current.
Specifically, the bases and the collectors of the first bipolar transistor Q1 and the second bipolar transistor Q2 are both grounded, the emitter of the first bipolar transistor Q1 is connected to the first input terminal of the first current mirror circuit, and the emitter of the second bipolar transistor Q2 is connected to the second input terminal of the first current mirror circuit through the first resistor R1. The first current mirror comprises an eighth transistor MN1, a ninth transistor MN2, a tenth transistor MP1 and an eleventh transistor MP2, the source electrode of the eighth transistor MN1 is the first input end of the first current mirror, the source electrode of the ninth transistor MN2 is the second input end of the first current mirror, the gate drain of the eighth transistor MN1 is in short circuit and is connected to the gate electrode of the ninth transistor MN2 and the drain electrode of the tenth transistor MP1, the gate drain of the eleventh transistor MP2 is in short circuit and is connected to the gate electrode of the tenth transistor MP1 and the drain electrode of the ninth transistor MN2, and the source electrodes of the tenth transistor MP1 and the eleventh transistor MP2 are both connected to a power supply voltage.
In the embodiment of the present disclosure, the reference voltage generating circuit may further include a second current source, a base and a collector of the third bipolar transistor Q3 are both grounded, an emitter is connected to the second current source and a source of the first transistor MN5 through the second resistor R2, the second current source is a current source formed by twice mirroring the first current, and another end of the second current source is connected to the power supply voltage. In an embodiment of the present disclosure, the second current source may include a twelfth transistor MP3, a gate of the twelfth transistor MP3 is connected to a gate of the eleventh transistor MP2, a drain of the twelfth transistor MP3 is connected to the second resistor R2, and a source of the twelfth transistor MP3 is connected to the power supply voltage. By reasonably setting the characteristic sizes of the first bipolar transistor Q1, the second bipolar transistor Q2 and the third bipolar transistor Q3, a first reference voltage Vref1 which does not change along with temperature and process can be obtained by comparing the difference (Veb 1-Veb 2) between the emitter-base voltages of the first bipolar transistor Q1 and the second bipolar transistor Q2 with positive temperature coefficients and the emitter-base voltage Veb3 of the third bipolar transistor Q3 with negative temperature coefficients.
Specifically, assuming that mismatches in the circuit, including mismatches between resistances, mismatches between transistors, and the like, are ignored, the transistors MN1, MN2, MP1, and MP2 constitute a self-bias loop, and the source voltages of MN1 and MN2 are taken into consideration. For a bipolar transistor, the collector current is related to the saturation current by: i is C ＝I S *e Veb/Vt Wherein, I C Is a collector circuit of a bipolar transistor, I S In a saturation circuit of a bipolar transistor, veb is an emitter-base voltage of the bipolar transistor, vt is a thermal voltage, vt = kT/q, k is a Boltzmann constant, T is an absolute temperature, and q is an electronic charge.
The bases and collectors of the bipolar transistors Q1, Q2 and Q3 in fig. 3 are all grounded, so that the currents of the bipolar transistors Q1, Q2 and Q3 are all: i is Q ＝I E ＝I B +I C ＝(1+1/β F )Is*e Veb/Vt In which I Q For the current flowing through the bipolar transistor, I E Is the emitter current of a bipolar transistor, I B Is the base current of a bipolar transistor. It can further be concluded that Veb = Vt × ln (I) Q /(Is*(1+1/β F )))。
The eighth transistor MN1 and the ninth transistor MN2 in fig. 3 are equal in size, and the tenth transistors MP1 and MP2The eleventh transistor MP2 is of equal size, so the current I flowing through the bipolar transistors Q1 and Q2 Q1 And I Q2 Equal, the emitter-base voltage difference between the two is: Δ Veb = Veb1-Veb2= Vt × ln ((I) Q1 *I S2 )/(I S1 *I Q2 ) N is an emitter area ratio of the second bipolar transistor Q2 to the first bipolar transistor Q1, and a saturation current ratio of the first bipolar transistor Q1 to the second bipolar transistor Q2 is: i is S1 ：I S2 ＝1：N。
As can be seen from fig. 3, the current in the bipolar transistors Q1 and Q2 is equal to the current in the first resistor R1, so that: i is Q1 ＝I Q2 ＝ΔVeb/R1＝Vt*ln(N/R1)。
The sizes of the devices are reasonably set, so that the current generated by the second current source is evenly distributed to the second resistor R2, the third bipolar transistor Q3 branch and the first reference voltage Vref1 output branch, and the current in the second resistor R2 is equal to the current in the first resistor R1, and then the first reference voltage Vref1 for realizing first-order temperature compensation can be obtained: vref1= Veb3+ ((Veb 1-Veb 2)/R1) × R2.
In the embodiment of the present disclosure, the first transistor MP5 and the second transistor MP6 may have the same characteristic size, so that the magnitudes of the currents flowing through the first transistor MP5 and the second transistor MP6 are also equal, and further, the gate-source voltages of the first transistor MP5 and the second transistor MP6 are also equal. By adopting the mode, the first reference voltage Vref1 can be copied from the source electrode of the first transistor MP5 to the source electrode of the second transistor MP6 for outputting in a lossless manner, and after the first reference voltage Vref1 is buffered and isolated by the first transistor MP5, the second transistor MP6 is used as a level conversion circuit to generate a first control voltage output to a source current voltage-stabilizing branch circuit and a second control voltage output to a sink current voltage-stabilizing branch circuit, so that the reliability of the circuit is improved. Through the transistors MP8, MN6 and MN7, a bandgap reference voltage VREF1 with source current and sink current is obtained as VREF1= VREF1 1 -V SGMP5 +V SGMP6 Wherein V is SGMP5 Is the source-gate voltage, V, of the first transistor MP5 SGMP6 Is said secondThe source-gate voltage of the transistor MP 6.
In the disclosed embodiment, the third current source may include a thirteenth transistor MP4, a fourteenth transistor MN3, and a fifteenth transistor MN4, wherein a gate of the thirteenth transistor MP4 is connected to a gate of the twelfth transistor MP3, a drain of the thirteenth transistor MP4 is connected to a drain of the fourteenth transistor MN3, and a source of the thirteenth transistor MP4 is connected to the power supply voltage; the gate and the drain of the fourteenth transistor MN3 are shorted and connected to the gate of the fifteenth transistor MN4, the sources of the fourteenth transistor MN3 and the fifteenth transistor MN4 are both grounded, and one end of the drain of the fifteenth transistor MN4, which is used as a third current source, is connected to the drain of the first transistor MP 5.
In this disclosure, the drain of the second transistor MP6 is further connected to a fourth current source, the fourth current source is formed by twice mirroring the first current, and the other end of the fourth current source is grounded. Specifically, the fourth current source may include a sixteenth transistor MN5, a gate of the sixteenth transistor MN5 is connected to the gate of the fifteenth transistor MN4, a drain of the sixteenth transistor MN5 is connected to the drain of the second transistor MP6 as a fourth current source, and a source of the sixteenth transistor MN5 is grounded.
In the embodiment of the present disclosure, the source of the third transistor MN6 is an input terminal of the source of the current stabilizing branch, the gate of the third transistor MN6 is connected to the first bias voltage, the drain of the third transistor MN6 is connected to the gate of the fourth transistor MP8, the source of the fourth transistor MP8 is connected to the power supply voltage, and the drain of the fourth transistor MP8 is connected to the reference voltage.
In the embodiment of the present disclosure, the drain of the third transistor MN6 may be further connected to a fifth current source, where the fifth current source is formed by mirroring the first current by one time, and the other end of the fifth current source is connected to a power supply voltage. Specifically, the fifth current source may include a seventeenth transistor MP7, wherein a gate of the seventeenth transistor MP7 is connected to the gate of the twelfth transistor MP2, a drain of the seventeenth transistor MP7 is connected to the drain of the third transistor MN6 as a fifth current source, and a source of the seventeenth transistor MP7 is connected to a power supply voltage.
When the reference voltage generating circuit receives an external source current, the output reference voltage Vref of the reference voltage generating circuit is pulled down, and at this time, the source voltage of the second transistor MP6 is lowered, which causes the gate-source voltage of the second transistor MP6 to increase, and further causes the leakage current of the second transistor MP6 to increase. Since the current provided by the fourth current source is kept constant, the current flowing through the third transistor MN6 will decrease, and the drain voltage of the third transistor MN6 will decrease, that is, the gate voltage of the fourth transistor MP8 will decrease, so that the fourth transistor MP8 will turn on, and the reference voltage will be quickly regulated to the rated value.
In the embodiment of the present disclosure, the sinking current stabilizing branch includes a fifth transistor MN7, a gate of the fifth transistor MN7 is an input end of the sinking current stabilizing branch, a source of the fifth transistor MN7 is grounded, and a drain of the fifth transistor MN7 is connected to the reference voltage.
When the reference voltage generating circuit receives the external sink current, the output reference voltage Vref of the reference voltage generating circuit increases, and at this time, the source voltage of the second transistor MP6 increases, which causes the drain voltage of the second transistor MP6 to increase, that is, the gate voltage of the fifth transistor MN7 increases, so that the fifth transistor MN7 is turned on, and the reference voltage is rapidly stabilized to a rated value.
According to the technical scheme of the embodiment of the disclosure, the source current voltage stabilizing circuit and the sink current voltage stabilizing circuit are formed by the active devices MN6, MP8 and MN7, so that the output reference voltage can be stabilized under the source current condition and the sink current condition, and the response speed is high.
In the disclosed embodiment, the first bias voltage is generated by a bias branch comprising a sixth current source, a sixth transistor MN8 and a seventh transistor MN9. The sixth current source is a current source formed by mirroring the first current, one end of the sixth current source is connected to a power supply voltage, and the other end of the sixth current source is connected to the first bias voltage and the drain of the sixth transistor MN 8; the grid drain of the sixth transistor MN8 is in short circuit, and the source electrode of the sixth transistor MN8 is connected to the drain electrode of the seventh transistor MN9; and the grid drain of the seventh transistor MN9 is in short circuit, and the source electrode is grounded. Further, the sixth current source may include an eighteenth transistor MP9, wherein a gate of the eighteenth transistor MP9 is connected to the gate of the twelfth transistor MP2, one end of a drain as the sixth current source is connected to the drain of the sixth transistor MN8, and a source is connected to the power supply voltage.
According to the technical scheme of the embodiment of the disclosure, the bias branch circuit is formed by the current source formed by mirroring the first current and the two transistors connected in series in the diode connection mode, so that the first bias voltage is provided for the source current voltage stabilization branch circuit, the structure is simple, and the performance is stable.
In the embodiment of the present disclosure, the transistors MN1 to MN9 may be N-type metal oxide field effect transistors NMOS, and the transistors MP1 to MP9 may be P-type metal oxide field effect transistors NMOS. Wherein transistors MP5 and MP6 have the same feature size, transistors MP1, MP2, MP4, MP7 and MP9 have the same feature size, transistor MP3 has twice the feature size of transistor MP1, transistors MN3 and MN4 have the same feature size, and transistor MN5 has twice the feature size of transistor MN 3.
In another embodiment of the present disclosure, the reference voltage generating circuit in the reference voltage generating circuit may be replaced by another reference voltage generating circuit, that is, the other reference voltage generating circuit may be combined with the voltage stabilizing circuit in the reference voltage generating circuit to implement the reference voltage generating circuit having both current sourcing and current sinking functions. Those skilled in the art can select different reference voltage generating circuits to combine with the voltage regulator circuit according to the requirements of practical application, and the disclosure is not described herein too much.
Fig. 4 shows a block diagram of an electronic device according to an embodiment of the present disclosure.
As shown in fig. 4, the electronic device includes the reference voltage generation circuit provided by the embodiment of the disclosure.
Specifically, the reference voltage generating circuit includes:
a reference voltage generation circuit for generating a first reference voltage that is invariant to process and temperature;
voltage stabilizing circuit, voltage stabilizing circuit includes voltage conversion circuit, source current steady voltage branch road and irritates current steady voltage branch road, wherein:
the voltage conversion circuit is used for converting the first reference voltage into the reference voltage, converting the reference voltage into a first control voltage when the reference voltage generation circuit receives an external source current, and converting the reference voltage into a second control voltage when the reference voltage generation circuit receives an external sink current;
the source current stabilizing branch comprises a third transistor MN6 and a fourth transistor MP8, the source electrode of the third transistor MN6 is connected to the first control voltage, and the drain electrode of the fourth transistor MP8 is connected to the reference voltage, so that when the reference voltage generating circuit receives an external source current to cause the reference voltage to be reduced, the reference voltage is stabilized to a rated value;
the sinking current stabilizing branch comprises a fifth transistor MN7, the grid electrode of the fifth transistor MN7 is connected to the second control voltage, and the drain electrode of the fifth transistor MN7 is connected to the reference voltage, so that when the reference voltage generating circuit receives external sinking current and the reference voltage is increased, the reference voltage is stabilized to a rated value.
In an embodiment of the disclosure, the reference voltage generation circuit is further configured to generate a first current.
In the embodiment of the present disclosure, the reference voltage generating circuit includes a first bipolar transistor Q1, a second bipolar transistor Q2, a third bipolar transistor Q3, a first resistor R1, a second resistor R2, and a first current mirror circuit; wherein the content of the first and second substances,
the first bipolar transistor Q1, the second bipolar transistor Q2, the third bipolar transistor Q3, the first resistor R1, and the second resistor R2 are configured to generate the first reference voltage, and the first current mirror circuit is configured to generate the first current.
In the embodiment of the present disclosure, the bases and the collectors of the first bipolar transistor Q1 and the second bipolar transistor Q2 are both grounded, the emitter of the first bipolar transistor Q1 is connected to the first input end of the first current mirror circuit, and the emitter of the second bipolar transistor Q2 is connected to the second input end of the first current mirror circuit through the first resistor R1;
the reference voltage generating circuit further comprises a second current source, the base electrode and the collector electrode of the third bipolar transistor Q3 are grounded, the emitter electrode is connected to the second current source and the source electrode of the first transistor MN5 through the second resistor, the second current source is a current source formed by twice mirroring of the first current, and the other end of the second current source is connected to the power supply voltage.
In the embodiment of the present disclosure, the voltage converting circuit includes a first transistor MP5 and a second transistor MP6, the first transistor MP5 and the second transistor MP6 are connected by using a common gate, a source of the first transistor MP5 is connected to the first reference voltage, a drain of the first transistor MP5 is grounded through a third current source, and the third current source is a current source formed by mirroring the first current; the source electrode of the second transistor MP6 is connected to the reference voltage, and the drain electrode is connected to the input terminals of the source current voltage stabilizing branch and the sink current voltage stabilizing branch.
In the embodiment of the present disclosure, the first transistor MP5 and the second transistor MP6 have the same feature size.
In this disclosure, the drain of the second transistor MP6 is further connected to a fourth current source, the fourth current source is formed by twice mirroring the first current, and the other end of the fourth current source is grounded.
In the embodiment of the present disclosure, the gate of the third transistor MN6 is connected to a first bias voltage, the drain is connected to the gate of the fourth transistor MP8, and the source of the fourth transistor MP8 is connected to a power supply voltage;
the source of the fifth transistor MN7 is grounded.
In the embodiment of the present disclosure, the drain of the third transistor MN6 is further connected to a fifth current source, where the fifth current source is formed by mirroring the first current by one time, and the other end of the fifth current source is connected to a power supply voltage.
In the disclosed embodiment, the first bias voltage is generated by a bias branch, which includes a sixth current source, a sixth transistor MN8 and a seventh transistor MN9;
the sixth current source is a current source formed by mirroring the first current, one end of the sixth current source is connected to a power supply voltage, and the other end of the sixth current source is connected to the first bias voltage and the drain of the sixth transistor MN 8;
the grid drain of the sixth transistor MN8 is in short circuit, and the source electrode of the sixth transistor MN8 is connected to the drain electrode of the seventh transistor MN9;
and the grid drain of the seventh transistor MN9 is in short circuit, and the source electrode is grounded.
Fig. 5 shows a block diagram of a chip according to an embodiment of the disclosure.
As shown in fig. 5, the chip includes an electronic device provided by the embodiment of the present disclosure, and the electronic device includes a reference voltage generation circuit provided by the embodiment of the present disclosure.
Specifically, the reference voltage generating circuit includes:
a reference voltage generation circuit for generating a first reference voltage that is invariant to process and temperature;
voltage stabilizing circuit, voltage stabilizing circuit includes voltage conversion circuit, source current steady voltage branch road and irritates current steady voltage branch road, wherein:
the voltage conversion circuit is used for converting the first reference voltage into the reference voltage, converting the reference voltage into a first control voltage when the reference voltage generation circuit receives an external source current, and converting the reference voltage into a second control voltage when the reference voltage generation circuit receives an external sink current;
the source current stabilizing branch comprises a third transistor MN6 and a fourth transistor MP8, the source electrode of the third transistor MN6 is connected to the first control voltage, and the drain electrode of the fourth transistor MP8 is connected to the reference voltage, so that when the reference voltage generating circuit receives an external source current to cause the reference voltage to be reduced, the reference voltage is stabilized to a rated value;
the current-sinking voltage-stabilizing branch circuit comprises a fifth transistor MN7, wherein the grid electrode of the fifth transistor MN7 is connected to the second control voltage, and the drain electrode of the fifth transistor MN7 is connected to the reference voltage, so that when the reference voltage generating circuit receives external current sinking and the reference voltage is increased, the reference voltage is stabilized to a rated value.
The foregoing description is only exemplary of the preferred embodiments of the disclosure and is illustrative of the principles of the technology employed. It will be appreciated by those skilled in the art that the scope of the invention in the present disclosure is not limited to the specific combination of the above-mentioned features, but also encompasses other embodiments in which any combination of the above-mentioned features or their equivalents is made without departing from the inventive concept. For example, the above features and the technical features disclosed in the present disclosure (but not limited to) having similar functions are replaced with each other to form the technical solution.

Claims (18)

1. A reference voltage generating circuit, comprising:
a reference voltage generation circuit for generating a first reference voltage that is invariant to process and temperature;
voltage stabilizing circuit, voltage stabilizing circuit includes voltage conversion circuit, source current steady voltage branch road and irritates current steady voltage branch road, wherein:
the voltage conversion circuit is used for converting the first reference voltage into the reference voltage, converting the reference voltage into a first control voltage when the reference voltage generation circuit receives an external source current, and converting the reference voltage into a second control voltage when the reference voltage generation circuit receives an external sink current, wherein the voltage conversion circuit comprises a first transistor MP5 and a second transistor MP6, the first transistor MP5 and the second transistor MP6 are connected by adopting a common gate, the source of the first transistor MP5 is connected to the first reference voltage, the drain of the first transistor MP5 is grounded through a third current source, and the third current source is a current source formed by mirroring the first current; the source electrode of the second transistor MP6 is connected to the reference voltage, and the drain electrode of the second transistor MP6 is connected to the input ends of the source current voltage stabilizing branch and the sink current voltage stabilizing branch;
the source current stabilizing branch comprises a third transistor MN6 and a fourth transistor MP8, the source electrode of the third transistor MN6 is connected to the first control voltage, and the drain electrode of the fourth transistor MP8 is connected to the reference voltage, so that when the reference voltage generating circuit receives an external source current to cause the reference voltage to be reduced, the reference voltage is stabilized to a rated value;
the sinking current stabilizing branch comprises a fifth transistor MN7, the grid electrode of the fifth transistor MN7 is connected to the second control voltage, and the drain electrode of the fifth transistor MN7 is connected to the reference voltage, so that when the reference voltage generating circuit receives external sinking current and the reference voltage is increased, the reference voltage is stabilized to a rated value.
2. The circuit of claim 1,
the reference voltage generation circuit is also used for generating a first current.
3. The circuit of claim 2,
the reference voltage generating circuit comprises a first bipolar transistor Q1, a second bipolar transistor Q2, a third bipolar transistor Q3, a first resistor R1, a second resistor R2 and a first current mirror circuit; wherein, the first and the second end of the pipe are connected with each other,
the first bipolar transistor Q1, the second bipolar transistor Q2, the third bipolar transistor Q3, the first resistor R1, and the second resistor R2 are used to generate the first reference voltage, and the first current mirror circuit is used to generate the first current.
4. The circuit of claim 3,
the bases and collectors of the first bipolar transistor Q1 and the second bipolar transistor Q2 are grounded, the emitter of the first bipolar transistor Q1 is connected to the first input end of the first current mirror circuit, and the emitter of the second bipolar transistor Q2 is connected to the second input end of the first current mirror circuit through the first resistor R1;
the reference voltage generating circuit further comprises a second current source, the base electrode and the collector electrode of the third bipolar transistor Q3 are grounded, the emitter electrode is connected to the second current source and the source electrode of the first transistor MN5 through the second resistor, the second current source is a current source formed by twice mirroring of the first current, and the other end of the second current source is connected to the power supply voltage.
5. The circuit of claim 1,
the first transistor MP5 and the second transistor MP6 have the same feature size.
6. The circuit of claim 5,
the drain of the second transistor MP6 is further connected to a fourth current source, which is a current source formed by twice mirroring the first current, and the other end of the fourth current source is grounded.
7. The circuit of claim 6,
a gate of the third transistor MN6 is connected to a first bias voltage, a drain thereof is connected to a gate of the fourth transistor MP8, and a source of the fourth transistor MP8 is connected to a power supply voltage;
the source of the fifth transistor MN7 is grounded.
8. The circuit of claim 7,
the drain of the third transistor MN6 is further connected to a fifth current source, which is a current source formed by one-time mirroring of the first current, and the other end of the fifth current source is connected to a power supply voltage.
9. The circuit of claim 8,
the first bias voltage is generated by a bias branch, and the bias branch comprises a sixth current source, a sixth transistor MN8 and a seventh transistor MN9;
the sixth current source is a current source formed by mirroring the first current, one end of the sixth current source is connected to a power supply voltage, and the other end of the sixth current source is connected to the first bias voltage and the drain of the sixth transistor MN 8;
the grid drain of the sixth transistor MN8 is in short circuit, and the source electrode of the sixth transistor MN8 is connected to the drain electrode of the seventh transistor MN9;
and the grid drain of the seventh transistor MN9 is in short circuit, and the source electrode is grounded.
10. The circuit of claim 9,
the first current mirror circuit includes an eighth transistor MN1, a ninth transistor MN2, a tenth transistor MP1, and an eleventh transistor MP2, wherein a source of the eighth transistor MN1 is a first input terminal of the first current mirror, a source of the ninth transistor MN2 is a second input terminal of the first current mirror, a gate-drain of the eighth transistor MN1 is shorted and connected to a gate of the ninth transistor MN2 and a drain of the tenth transistor MP1, a gate-drain of the eleventh transistor MP2 is shorted and connected to a gate of the tenth transistor MP1 and a drain of the ninth transistor MN2, and sources of the tenth transistor MP1 and the eleventh transistor MP2 are both connected to a power supply voltage.
11. The circuit of claim 10,
the second current source includes a twelfth transistor MP3, a gate of the twelfth transistor MP3 is connected to a gate of the eleventh transistor MP2, a drain of the twelfth transistor MP3 is connected to the second resistor R2, and a source of the twelfth transistor MP3 is connected to the power supply voltage.
12. The circuit of claim 11,
the third current source includes a thirteenth transistor MP4, a fourteenth transistor MN3 and a fifteenth transistor MN4, wherein the gate of the thirteenth transistor MP4 is connected to the gate of the twelfth transistor MP3, the drain is connected to the drain of the fourteenth transistor MN3, and the source is connected to the power supply voltage; the gate and the drain of the fourteenth transistor MN3 are shorted and connected to the gate of the fifteenth transistor MN4, the sources of the fourteenth transistor MN3 and the fifteenth transistor MN4 are both grounded, and one end of the drain of the fifteenth transistor MN4, which is used as a third current source, is connected to the drain of the first transistor MP 5.
13. The circuit of claim 12,
the fourth current source includes a sixteenth transistor MN5, a gate of the sixteenth transistor MN5 is connected to the gate of the fifteenth transistor MN4, one end of the drain serving as the fourth current source is connected to the drain of the second transistor MP6, and a source is grounded.
14. The circuit of claim 13,
the fifth current source includes a seventeenth transistor MP7, a gate of the seventeenth transistor MP7 is connected to the gate of the twelfth transistor MP2, a drain of the seventeenth transistor MP7 is connected to the drain of the third transistor MN6 as a fifth current source, and a source of the seventeenth transistor MP7 is connected to a power supply voltage.
15. The circuit of claim 14,
the sixth current source includes an eighteenth transistor MP9, a gate of the eighteenth transistor MP9 is connected to the gate of the twelfth transistor MP2, one end of a drain as a sixth current source is connected to the drain of the sixth transistor MN8, and a source is connected to the power supply voltage.
16. The circuit of claim 15,
the transistors MP1, MP2, MP4, MP7 and MP9 have the same feature size, the transistor MP3 has a feature size twice that of the transistor MP1, the transistors MN3 and MN4 have the same feature size, and the transistor MN5 has a feature size twice that of the transistor MN 3.
17. A chip, characterized in that,
the chip comprising a reference voltage generating circuit as claimed in any one of claims 1 to 16.
18. An electronic device, characterized in that it comprises a display,
the electronic device comprising the chip of claim 17.
CN202211344115.3A 2022-10-31 2022-10-31 Reference voltage generating circuit, chip and electronic equipment Active CN115617115B (en)

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PCT/CN2023/122790 WO2024093602A1 (en) 2022-10-31 2023-09-28 Voltage reference generation circuit, and chip and electronic device

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CN107741754A (en) * 2014-01-02 2018-02-27 意法半导体研发(深圳)有限公司 The ldo regulator with improved load transient performance for internal electric source
CN108427472A (en) * 2018-03-19 2018-08-21 广州慧智微电子有限公司 A kind of reference voltage output circuit
US20190011944A1 (en) * 2016-03-25 2019-01-10 Panasonic Intellectual Property Management Co., Ltd. Regulator circuit
CN110007708A (en) * 2019-04-18 2019-07-12 电子科技大学 A kind of linear voltage regulator with pull-up current and pull-down current ability
JP2021096554A (en) * 2019-12-16 2021-06-24 新日本無線株式会社 Constant current circuit
CN114510112A (en) * 2022-01-12 2022-05-17 电子科技大学 Transient enhancement circuit applied to low-power-consumption fully-integrated low dropout linear regulator

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102520757A (en) * 2011-12-28 2012-06-27 南京邮电大学 Sink current and source current generating circuit
CN107741754A (en) * 2014-01-02 2018-02-27 意法半导体研发(深圳)有限公司 The ldo regulator with improved load transient performance for internal electric source
US20190011944A1 (en) * 2016-03-25 2019-01-10 Panasonic Intellectual Property Management Co., Ltd. Regulator circuit
CN108427472A (en) * 2018-03-19 2018-08-21 广州慧智微电子有限公司 A kind of reference voltage output circuit
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JP2021096554A (en) * 2019-12-16 2021-06-24 新日本無線株式会社 Constant current circuit
CN114510112A (en) * 2022-01-12 2022-05-17 电子科技大学 Transient enhancement circuit applied to low-power-consumption fully-integrated low dropout linear regulator

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