CN111161664A

CN111161664A - Display device and terminal

Info

Publication number: CN111161664A
Application number: CN202010090013.8A
Authority: CN
Inventors: 肖光星
Original assignee: TCL Huaxing Photoelectric Technology Co Ltd
Current assignee: TCL Huaxing Photoelectric Technology Co Ltd
Priority date: 2020-02-13
Filing date: 2020-02-13
Publication date: 2020-05-15
Anticipated expiration: 2040-02-13
Also published as: CN111161664B

Abstract

The application provides a display device and a terminal, wherein the display device comprises a display panel and a control panel electrically connected with the display panel, the control panel comprises a time schedule controller, a first level shifter and a second level shifter, and the time schedule controller is used for providing a clock opening signal and a clock closing signal; the first level shifter is used for determining the rising edge of a clock signal required by the display panel according to the clock starting signal and determining the falling edge of the clock signal according to the clock closing signal; the second level shifter is used for converting the clock signal with the high voltage into the clock signal with the low voltage; the time schedule controller also comprises a detection module, wherein the detection module is used for detecting whether the clock signal of the low voltage is abnormal or not, and controlling the time schedule controller to stop outputting the clock opening signal and the clock closing signal when the clock signal is detected to be abnormal. According to the method and the device, when the clock signal is abnormal, the clock signal is timely stopped being input to the display panel, and therefore the display panel can be prevented from being damaged.

Description

Display device and terminal

Technical Field

The application relates to the technical field of display, in particular to a display device and a terminal.

Background

The GOA (Gate Driver On Array) and the Array substrate line driving are realized by integrating a gate line driving circuit On the Array substrate by utilizing an Array process, so that a gate driving IC On the Array substrate can be omitted, and the aims of reducing the production cost and realizing the frame are fulfilled. In general, the clock signal lines of the GOAs are routed outside the glass substrate of the display panel, and are designed by the array-outside wiring. However, when a short circuit or other abnormal condition occurs in the clock signal line, it is easy to cause an excessive current to damage the display panel.

Therefore, the conventional display device has the technical problem that the display panel is damaged due to the abnormal clock signal, and needs to be improved.

Disclosure of Invention

The application provides a display device and a terminal to alleviate the technical problem that a display panel is damaged due to clock signal abnormity in the conventional display device.

In order to solve the above problems, the technical solution provided by the present application is as follows:

the application provides a display device, including display panel and with display panel electric connection's control panel, the control panel includes:

a timing controller for providing a clock on signal and a clock off signal;

the first level shifter is used for determining the rising edge of a clock signal required by the display panel according to the clock starting signal and determining the falling edge of the clock signal according to the clock closing signal;

a second level shifter for converting the clock signal of the high voltage into a clock signal of a low voltage;

the timing controller further comprises a detection module, wherein the detection module is used for detecting whether a low-voltage clock signal is abnormal or not, controlling the timing controller to continue outputting the clock opening signal and the clock closing signal when detecting that the clock signal is normal, and controlling the timing controller to stop outputting the clock opening signal and the clock closing signal when detecting that the clock signal is abnormal.

In the display device of the present application, the detection module is a detection register.

In the display device of the application, the detection module is used for detecting the period and the duty ratio of the clock signal so as to judge whether the clock signal is abnormal or not.

In the display device of the application, the detection module is used for detecting the number of cycles of the clock signal so as to judge whether the clock signal is abnormal or not.

In the display device of the application, the detection module is used for detecting the phase relation between the clock signals so as to judge whether the clock signals are abnormal or not.

In the display device of the application, the detection module is used for comparing the clock signal with a standard time sequence so as to judge whether the clock signal is abnormal or not.

In the display device of the application, the timing controller is further configured to output a frame start signal, and the timing controller further includes a reset module, where the reset module is configured to reset the detection module at a rising edge of each frame start signal.

In the display device of this application, the control panel still includes power management integrated chip, power management integrated chip be used for to display panel output operating voltage, time schedule controller still is used for, detects when clock signal is unusual, cuts off power management integrated chip's output.

In the display device of this application, the control panel is still including the buffering chip of the gamma proofreading able to programme, the buffering chip of the gamma proofreading able to programme is used for to display panel output gamma reference voltage, time schedule controller still is used for, detects when clock signal is unusual, cuts off the output of buffering chip of the gamma proofreading able to programme.

The application also provides a terminal, which comprises a display device and a shell, wherein the display device is any one of the display devices.

The beneficial effect of this application: the application provides a display device and a terminal, wherein the display device comprises a display panel and a control panel electrically connected with the display panel, the control panel comprises a time schedule controller, a first level shifter and a second level shifter, and the time schedule controller is used for providing a clock opening signal and a clock closing signal; the first level shifter is used for determining the rising edge of a clock signal required by the display panel according to the clock starting signal and determining the falling edge of the clock signal according to the clock closing signal; the second level shifter is used for converting the clock signal with high voltage into a clock signal with low voltage; the timing controller further comprises a detection module, wherein the detection module is used for detecting whether a low-voltage clock signal is abnormal or not, controlling the timing controller to continue outputting the clock opening signal and the clock closing signal when detecting that the clock signal is normal, and controlling the timing controller to stop outputting the clock opening signal and the clock closing signal when detecting that the clock signal is abnormal. Through setting up second level shifter and detection module, convert the clock signal of high potential into the clock signal of low potential to detect the abnormal condition of clock signal, can be when appearing unusually, in time stop clock signal input to display panel, consequently can prevent that display panel from damaging.

Drawings

The technical solution and other advantages of the present application will become apparent from the detailed description of the embodiments of the present application with reference to the accompanying drawings.

Fig. 1 is a schematic structural diagram of a display device in the prior art.

Fig. 2 is a schematic structural diagram of a display device according to an embodiment of the present application.

Fig. 3 is a timing diagram of signals in a control board of a display device according to an embodiment of the present disclosure.

Fig. 4 is a schematic diagram illustrating a signal output process in a control board of a display device according to an embodiment of the present disclosure.

Detailed Description

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. It is to be understood that the embodiments described are only a few embodiments of the present application and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

In the description of the present application, it is to be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," and the like are used in the orientations and positional relationships indicated in the drawings for convenience in describing the present application and for simplicity in description, and are not intended to indicate or imply that the referenced devices or elements must have a particular orientation, be constructed in a particular orientation, and be operated in a particular manner, and are not to be construed as limiting the present application. Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, features defined as "first", "second", may explicitly or implicitly include one or more of the described features. In the description of the present application, "a plurality" means two or more unless specifically limited otherwise.

In the description of the present application, it is to be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; may be mechanically connected, may be electrically connected or may be in communication with each other; either directly or indirectly through intervening media, either internally or in any other relationship. The specific meaning of the above terms in the present application can be understood by those of ordinary skill in the art as appropriate.

In this application, unless expressly stated or limited otherwise, the first feature "on" or "under" the second feature may comprise direct contact of the first and second features, or may comprise contact of the first and second features not directly but through another feature in between. Also, the first feature being "on," "above" and "over" the second feature includes the first feature being directly on and obliquely above the second feature, or merely indicating that the first feature is at a higher level than the second feature. A first feature being "under," "below," and "beneath" a second feature includes the first feature being directly under and obliquely below the second feature, or simply meaning that the first feature is at a lesser elevation than the second feature.

The following disclosure provides many different embodiments or examples for implementing different features of the application. In order to simplify the disclosure of the present application, specific example components and arrangements are described below. Of course, they are merely examples and are not intended to limit the present application. Moreover, the present application may repeat reference numerals and/or letters in the various examples, such repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. In addition, examples of various specific processes and materials are provided herein, but one of ordinary skill in the art may recognize applications of other processes and/or use of other materials.

The application provides a display device to alleviate the technical problem that clock signal causes display panel to damage unusually among the current display device.

Fig. 1 is a schematic structural diagram of a display device in the prior art. The display device comprises a display panel 100 and a control panel 200, wherein the control panel 200 is connected with a printed circuit board 400 through a flexible circuit board 300, and the printed circuit board 400 is connected with the display panel 100 through a source electrode chip on film 500, so that the control panel 200 is electrically connected with the display panel 100.

The array substrate of the display panel 100 is integrated with a GOA circuit, the control board 100 is provided with a timing controller 21, a level shifter 22 and a programmable gamma correction buffer circuit chip 23, wherein the timing controller 21 inputs a clock control signal 212 to the level shifter 22, the clock control signal 212 is processed by the level shifter 22 and outputs a clock signal to the GOA circuit, and the timing controller 21 also outputs a point-to-point signal 21, a low voltage differential signal, a transistor-transistor logic signal, etc. (not shown in the figure) to the display panel, and all the signals are commonly supplied to the display panel 100 to drive the display panel 100 to display pictures.

However, when the traces of the clock signal are short-circuited or otherwise abnormal, if the input to the display panel 100 is continued, the current is easily excessive to damage the display panel 100. Therefore, the conventional display device has the technical problem that the display panel is damaged due to the abnormal clock signal, and needs to be improved.

Fig. 2 is a schematic structural diagram of a display device according to an embodiment of the present invention. The display device includes a display panel 100 and a control board 200 electrically connected to the display panel 100, the control board 200 includes:

a timing controller 201 for providing a clock turn-ON signal CK ON and a clock turn-OFF signal CK OFF;

a first level shifter 202 for determining a rising edge of a clock signal required by the display panel 100 according to the clock turn-ON signal CK ON and determining a falling edge of the clock signal according to the clock turn-OFF signal CK OFF;

a second level shifter 203 for converting the clock signal of the high voltage into a clock signal of a low voltage;

the timing controller 201 further includes a detection module (not shown) for detecting whether the low-voltage clock signal is abnormal, controlling the timing controller 201 to continue outputting the clock ON signal CK ON and the clock OFF signal CK OFF when detecting that the clock signal is normal, and controlling the timing controller 201 to stop outputting the clock ON signal CK ON and the clock OFF signal CK OFF when detecting that the clock signal is abnormal.

The control board 200 is connected to the printed circuit board 400 through the flexible circuit board 300, and the printed circuit board 400 is connected to the display panel 100 through the source chip on film 500, so as to electrically connect the control board 200 and the display panel 100.

The display panel 100 includes a GOA circuit, and clock signals required to drive the GOA circuit are provided from the control board 200.

The timing controller 201 is disposed in the control board 200, and the timing controller 201 converts the data signals in the V-By-One, LVDS, EDP format received from the outside into data signals in the Mini-LVDS, RSDS, TTL format and the like that the display panel can recognize, and then transmits the data signals to the GOA circuit, thereby finally realizing the image display of the display panel 100.

The clock ON signal CK ON and the clock OFF signal CK OFF provided by the timing controller 201 need to be subjected to level conversion before being supplied to the GOA circuit in the display panel 100, so the clock ON signal CK ON and the clock OFF signal CK OFF need to be input into the first level shifter 202, the first level shifter 202 determines the rising edge of the clock signal required by the display panel 100 according to the clock ON signal CKON, and determines the falling edge of the clock signal according to the clock OFF signal CK OFF. In the present embodiment, taking the number of clock signals as 8 as an example, the plurality of clock signals are CK1, CK2, CK8 in sequence, and may include more clock signals. The first rising edge of CK1, CK2,. and CK8 respectively corresponds to the first rising edge, the second rising edge, the eighth rising edge of a clock turn-ON signal CK ON, and the first falling edge of CK1, CK2,. and CK8 respectively corresponds to the first falling edge, the second falling edge, the. At this time, the voltage of the clock signal is a high voltage, and the high voltage clock signal is transmitted to the display panel to drive the GOA circuit to operate.

After the clock signals are converted, the second level converter 203 converts the high-voltage clock signals into low-voltage clock signals, which are also CK1, CK2, and CK8 in sequence, where the voltage of the clock signals is low.

After obtaining the low-voltage clock signal, the second level shifter 203 inputs the clock signal into the timing controller 201, and the detection module in the timing controller 201 detects the clock signal to determine whether it is normal. When the detection result is normal, the timing controller 201 continues to input the clock ON signal CK ON and the clock OFF signal CK OFF to the first level shifter 202, and the first level shifter 202 also continues to input the high-voltage clock signal to the display panel 100, so that the GOA circuit operates normally. When the detection result is abnormal, the timing controller 201 stops inputting the clock ON signal CK ON and the clock OFF signal CK OFF to the first level shifter 202, and the first level shifter 202 also stops inputting the high voltage clock signal to the display panel 100, so that the abnormal signal does not enter the display panel.

The clock signal processed by the first level shifter 202 is a high voltage signal, and therefore cannot be directly input to the timing controller 201, and it needs to be converted into a low voltage clock signal by the second level shifter 203 and then input to the timing controller 201 for detection, so as to prevent the timing controller 201 from being damaged.

By arranging the second level shifter 203 and the detection module, the clock signal with high potential is converted into the clock signal with low potential, the abnormal condition of the clock signal is detected, and the clock signal can be timely stopped from being input into the display panel 100 when the abnormality occurs, so that the display panel 100 can be prevented from being damaged.

Fig. 3 shows the timing of the signals in the control board 200. Where T1 represents a display period per frame, T2 represents a blank period between adjacent frames, and the sum of times of T1 and T2 represents a complete cycle of one frame. In this embodiment, the complete period of one frame is 16.667ms, and the frequency is 60 HZ.

STV IN is a frame start signal input to the timing controller 201, CK ON is a clock ON signal output by the timing controller 201, CK OFF is a clock OFF signal output by the timing controller 201, Data is a Data signal output by the timing controller 201, LC is a low frequency control signal output by the timing controller 201, STV OUT is a frame start signal output by the first level shifter 202, CK1 OUT, CK2 OUT are two high voltage clock signals output by the first level shifter 202, LC1 is a first low frequency control signal output by the first level shifter 202, and LC2 is a second low frequency control signal output by the first level shifter 202.

At the start of each frame, the external inputs to the timing controller 201 a frame start signal STV whose high level lasts for 37 μ s and then becomes low until the next frame starts appearing high again. At a time after the start of the rising edge of the frame start signal STV, the timing controller 201 starts outputting the clock ON signal CK ON and the clock OFF signal CK OFF, the first rising edge of the clock ON signal CK ON is spaced from the rising edge of the frame start signal STV by 14.8 μ s, and the first falling edge of the clock OFF signal CK OFF is spaced from the rising edge of the frame start signal STV by 38.8 μ s. The period of the clock turn-ON signal CK ON and the clock turn-OFF signal CK OFF is 7.4 μ s, wherein the period is the time between adjacent rising edges of the clock turn-ON signal CK ON or the time between adjacent falling edges of the clock turn-OFF signal CK OFF.

The first level shifter 202 outputs a frame start signal STV at the beginning of each frame, and the clock ON signal CK ON and the clock OFF signal CK OFF are input to the first level shifter 202 for processing, and outputs a plurality of high-voltage clock signals, of which only two clock signals CK1 and CK2 are shown for convenience of illustration, and the subsequent clock signals CK3, CK4, CK5, CK6, CK7, and CK8 are sequentially output. The clock turn-ON signal CK ON is active at a rising edge, so the first rising edge of the corresponding output CK1, CK2,. and CK8 respectively corresponds to the first, second,. and eighth rising edges of the clock turn-ON signal CK ON. The clock OFF signal CKOFF is active at the falling edge, so the first falling edge of the corresponding output CK1, CK2,. and CK8 corresponds to the first, second,. and eighth falling edge of the clock OFF signal CK OFF, respectively. The time between adjacent rising edges of CK1 is 60 μ s of the period of the clock signal, and the duration of each high level is 24 μ s. The other clock signals have the same period as the CK1 period.

Each clock signal has 271 cycles in a complete cycle of a frame, each cycle being 60 μ s, each clock signal having an active time of: 271 × 60 ═ 16260 μ s, i.e. 16.26 ms. During the period T1, the output voltage falls to-10V after 271 cycles, and the low voltage continues until the end of the period T2.

In addition, the timing controller 201 also outputs the low frequency control signal LC, and outputs the first low frequency control signal LC1 and the second low frequency control signal LC2 after being converted by the first level shifter 202, wherein the phases of the first low frequency control signal LC1 and the second low frequency control signal LC2 are opposite, the rising edge of the first low frequency control signal LC1 corresponds to the rising edge of the low frequency control signal LC, and the rising edge of the second low frequency control signal LC2 corresponds to the falling edge of the low frequency control signal LC. Two lines are usually arranged in the GOA circuit to realize control, the two lines are respectively connected with a first low-frequency control signal LC1 and a second low-frequency control signal LC2, when the first low-frequency control signal LC1 is at a high potential and the second low-frequency control signal LC2 is at a low potential, the line connected with the first low-frequency control signal LC1 is operated, the line connected with the second low-frequency control signal LC2 is not operated, and when the first low-frequency control signal LC1 is at a low potential and the second low-frequency control signal LC2 is at a high potential, the line connected with the first low-frequency control signal LC1 is not operated, and the line connected with the second low-frequency control signal LC2 is operated. Therefore, the first low-frequency control signal LC1 and the second low-frequency control signal LC2 work together to make the lines in the GOA circuit work alternately, which can prolong the service life of the transistors in each line. In this embodiment, the high potential duration and the low potential duration of each low frequency control signal are the same and are both 1.67s, that is, about 100 frames of potential change once, and the line is switched once, wherein the switching time point is about the middle point of the T2 time period, so that the transmission of each signal is not affected.

The timing controller 201 also outputs a Data signal Data which appears rising before the first falling edge of CK1, has a high potential duration of 7.4s, starts to appear falling edge 4s after the first falling edge of CK1, and then remains low until the next frame.

As can be seen from fig. 3, in a normal situation, the high-voltage clock signal processed by the first level shifter 202 has a certain period, duty ratio and phase relationship, while the second level shifter 203 only converts the high-voltage clock signal into a low-voltage clock signal, so that the period, duty ratio and phase relationship do not change. Based on this, the detection of the clock signal by the detection module includes a plurality of aspects.

In one embodiment, the detection module is a detection register. Registers are high-speed storage elements of limited storage capacity that may be used to temporarily store instructions, data, and addresses. The sensing result may be stored in a sensing register.

In one embodiment, the detecting module is configured to detect a number of cycles of the plurality of clock signals to determine whether the plurality of clock signals are abnormal.

As shown in fig. 3, each clock signal includes 271 cycles in a complete cycle of a frame, so that each converted clock signal also includes 271 cycles, and each cycle is 60 μ s, and when the detected cycle number is not 271, or the cycle number is 271, but the number of cycles with the duration of 60 μ s is not equal to 271, it indicates that the clock signal output is incorrect.

In one embodiment, the detecting module is configured to detect periods and duty ratios of a plurality of clock signals to determine whether the plurality of clock signals are abnormal.

As shown in fig. 3, the complete period of one frame is 16.667ms, the period of each clock signal is 60 μ s, the number of periods is 271, and the action time of each clock signal is: 271 × 60 μ s, i.e., 16.26ms, and the duty ratio is 16.26 ÷ 16.667 ═ 97.56%, so that each clock signal period after conversion is also 60 μ s, and the duty ratio is also 97.56%, and when the detected period is not 60 μ s or the duty ratio is not 97.56%, it indicates that the clock signal output is erroneous.

In one embodiment, the detecting module is configured to detect a phase relationship between the plurality of clock signals to determine whether the plurality of clock signals are abnormal.

As shown in fig. 3, the first rising edge of CK1, CK2, the.. and CK8 respectively corresponds to the first, second, and eighth rising edges of the clock turn-ON signal CK ON, the first falling edge of CK1, CK2, the.. and CK8 respectively corresponds to the first, second, and eighth falling edges of the clock turn-off signal CKOFF, and between adjacent clock signals, the first rising edge is separated by 7.4 μ s, the second rising edge is separated by 7.4 μ s, and so ON. Similarly, the interval time between the first falling edges of adjacent clock signals is 7.4 mus, the interval time between the second falling edges is also 7.4 mus, and so on. Therefore, the phase relation among the converted clock signals is also determined, and when the phase relation among the clock signals is detected to be abnormal, the clock signal output error is indicated.

In the above embodiment, the detecting module detects parameters such as the period, duty ratio, number of periods, and phase relationship of each clock signal to determine whether the clock signal is abnormal.

In one embodiment, the detection module is further configured to compare the plurality of clock signals with a standard timing to determine whether the plurality of clock signals are abnormal. The standard time sequences of a plurality of clock signals can be stored in the detection register, and then directly correspond to the actually output clock signals, and when the standard time sequences do not accord with the actually output clock signals, the clock signal output error is indicated.

Fig. 4 shows a signal output process of the control board 200, which includes the following specific steps:

s10: and starting up and powering on.

S20: and the initialization of the time schedule controller is completed.

S30: and the time schedule controller carries out zero clearing operation on the rising edge of each frame starting signal.

When each frame starts, the timing controller 201 outputs a frame start signal STV, and the timing controller 201 further includes a reset module (not shown) for performing a reset operation, i.e., a zero clearing operation, on the detection module at a rising edge of each frame start signal STV to clear various data detected during previous use, so as to reduce the memory space of the register and make the operation smoother.

After the clearing, the timing controller 201, the first level conversion module 202, and the second level conversion module 203 start to operate normally, and a clock signal with a low potential is input into the timing controller 201.

S40: detecting whether the clock signal is correct.

The detecting module in the timing controller 201 detects the number of cycles of the plurality of clock signals, the cycles and duty ratios of the plurality of clock signals, the phase relationship between the plurality of clock signals, and the like, to determine whether the plurality of clock signals are abnormal.

S50: if the clock signal is correct, the time schedule controller outputs normally.

When the detection result is normal, the timing controller 201 continues to input the clock ON signal CK ON and the clock OFF signal CK OFF to the first level shifter 202, and the first level shifter 202 also continues to process the clock ON signal CK ON and the clock OFF signal CK OFF, and inputs the high-voltage clock signal to the display panel 100, so that the GOA circuit operates normally.

S60: if the clock signal is wrong, the time schedule controller stops outputting the clock opening signal and the clock closing signal.

When the detection result is abnormal, the timing controller 201 stops inputting the clock ON signal CK ON and the clock OFF signal CK OFF to the first level shifter 202, and the first level shifter 202 also stops processing the clock ON signal CK ON and the clock OFF signal CK OFF, so that a plurality of clock signals with high voltage cannot be continuously input to the display panel 100, and thus the abnormal signal does not enter the display panel.

As shown in FIG. 2, the control board 200 further includes a power management integrated chip 204 and a programmable gamma correction buffer circuit chip 205. The power management integrated chip 204 is used to output operating voltages such as a digital operating voltage (DVDD) supplied to each chip, an Analog Voltage (AVDD) supplied to the programmable gamma correction buffer circuit chip 205 and the VCOM circuit, a gate-on voltage (Vgh or Von) and a gate-off voltage (Vgl or Voff) supplied to the scan driving integrated circuit, and the like to the display device. The programmable gamma correction buffer circuit chip 205 is mainly used for generating and inputting the gamma reference voltage to the display panel 100.

In one embodiment, the timing controller 201 is further configured to shut off the output of the power management integrated chip 204 when an abnormal clock signal is detected.

In one embodiment, the timing controller 201 is further configured to switch off the output of the programmable gamma correction buffer chip when detecting an abnormal clock signal.

Through the steps, when the clock signal is abnormal, the clock signal is stopped from being input into the display panel in time, so that the effects of preventing the display panel from being burnt, generating bright light and generating fire are achieved.

The application also provides a terminal, which comprises a display device and a shell, wherein the display device is the display device in any embodiment.

According to the above embodiments:

the application provides a display device and a terminal, wherein the display device comprises a display panel and a control panel electrically connected with the display panel, the control panel comprises a time schedule controller, a first level shifter and a second level shifter, and the time schedule controller is used for providing a clock opening signal and a clock closing signal; the first level shifter is used for determining the rising edge of a clock signal required by the display panel according to the clock starting signal and determining the falling edge of the clock signal according to the clock closing signal; the second level shifter is used for converting the clock signal with the high voltage into the clock signal with the low voltage; the time schedule controller also comprises a detection module, wherein the detection module is used for detecting whether the clock signal of the low voltage is abnormal or not, controlling the time schedule controller to continue outputting the clock opening signal and the clock closing signal when detecting that the clock signal is normal, and controlling the time schedule controller to stop outputting the clock opening signal and the clock closing signal when detecting that the clock signal is abnormal. Through setting up second level shifter and detection module, convert the clock signal of high potential into the clock signal of low potential to detect the abnormal condition of clock signal, can be when appearing unusually, in time stop clock signal input to display panel, consequently can prevent that display panel from damaging.

In summary, although the present application has been described with reference to the preferred embodiments, the above-described preferred embodiments are not intended to limit the present application, and those skilled in the art can make various changes and modifications without departing from the spirit and scope of the present application, so that the scope of the present application shall be determined by the appended claims.

Claims

1. The display device is characterized by comprising a display panel and a control panel electrically connected with the display panel, wherein the control panel comprises:

a timing controller for providing a clock on signal and a clock off signal;

2. The display device according to claim 1, wherein the detection module is a detection register.

3. The display device as claimed in claim 2, wherein the detecting module is configured to detect a period and a duty ratio of the clock signal to determine whether the clock signal is abnormal.

4. The display device as claimed in claim 2, wherein the detecting module is configured to detect a number of cycles of the clock signal to determine whether the clock signal is abnormal.

5. The display device as claimed in claim 2, wherein the detecting module is configured to detect a phase relationship between the clock signals to determine whether the clock signals are abnormal.

6. The display device as claimed in claim 1, wherein the detecting module is configured to compare the clock signal with a standard timing to determine whether the clock signal is abnormal.

7. The display device according to claim 1, wherein the timing controller is further configured to output a frame start signal, and the timing controller further comprises a reset module configured to reset the detection module at a rising edge of each of the frame start signals.

8. The display device of claim 1, wherein the control board further comprises a power management integrated chip for outputting an operating voltage to the display panel, and the timing controller is further configured to cut off an output of the power management integrated chip when the clock signal abnormality is detected.

9. The display device of claim 1, wherein the control board further comprises a programmable gamma correction buffer chip for outputting a gamma reference voltage to the display panel, and the timing controller is further configured to cut off an output of the programmable gamma correction buffer chip when the clock signal abnormality is detected.

10. A terminal, characterized by comprising a display device and a housing, the display device being the display device of any one of claims 1 to 9.