CN106228944A - Level shift circuit and display panels - Google Patents
Level shift circuit and display panels Download PDFInfo
- Publication number
- CN106228944A CN106228944A CN201610891410.9A CN201610891410A CN106228944A CN 106228944 A CN106228944 A CN 106228944A CN 201610891410 A CN201610891410 A CN 201610891410A CN 106228944 A CN106228944 A CN 106228944A
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- Prior art keywords
- signal
- level shift
- module
- output
- receiving
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Classifications
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3685—Details of drivers for data electrodes
- G09G3/3688—Details of drivers for data electrodes suitable for active matrices only
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0264—Details of driving circuits
- G09G2310/0289—Details of voltage level shifters arranged for use in a driving circuit
Abstract
The present invention provides a kind of level shift circuit and display panels, and wherein level shift circuit includes: time schedule controller, for output for controlling the logical signal of drive circuit；Level shift chip, is electrically connected with time schedule controller, including: receiver module, it is electrically connected with sequencing contro, is used for receiving logical signal；Judge module, the most correct for the reception sequential of decision logic signal, as correctly, then send output signal, such as mistake, then send shutdown signal；Output module, for when receiving output signal, output logic signal, to control drive circuit；Close module, for when receiving shutdown signal, close level shift chip.The level shift circuit of the present invention and display panels, by closing level shift chip when the reception timing error of logical signal, effectively prevent display panels and be destroyed, improve the safety of display panels.
Description
Technical field
The present invention relates to Display Technique field, particularly relate to a kind of level shift circuit and display panels.
Background technology
At present, the liquid crystal display taking GOA (Gate Driver onArray, array base palte row cutting) framework becomes
The most the most frequently used display device.
Gate switch circuit is integrated on the array base palte of display panels by GOA framework, needs to use film crystal
Gate drivers prepared on the glass substrate by pipe (Thin Film Transistor, TFT), it is therefore desirable to pass through level shift
The signal that time schedule controller (TCON) exports is changed, to drive in liquid crystal panel by (Level Shifter, LS) circuit
TFT works.Wherein, when TCON is drive circuit (Source drive, gate driver and the VCOM Polarity Control) offer on liquid crystal display screen
Sequence control signal, thus the display realizing analog rgb signal controls.
In order to make drive circuit normally work, needing TCON to produce correct clock signal, the most once LS circuit receives
Signal to timing error, it will cause liquid crystal display screen picture exception and electric current excessive, even results in TFT and damages.
Summary of the invention
It is an object of the invention to provide a kind of level making display panels picture, current stabilization and safety high to move
Position circuit and display panels, to solve the technical problem that existing picture is abnormal, electric current is excessive and safety is relatively low.
The embodiment of the present invention provides a kind of level shift circuit, comprising:
Time schedule controller, for output for controlling the logical signal of drive circuit；
Level shift chip, is electrically connected with described time schedule controller, including:
Receiver module, is electrically connected with described sequencing contro, is used for receiving described logical signal；
Judge module, the most correct for judging the reception sequential of described logical signal, as correctly, then send output letter
Number, such as mistake, then send shutdown signal；
Output module, for when receiving described output signal, exports described logical signal, to control drive circuit；
Close module, for when receiving described shutdown signal, close described level shift chip.
In level shift circuit of the present invention, described logical signal includes multiple clock signal, described reception mould
Block includes:
Multiple clock signals receive unit, are respectively used to receive the plurality of clock signal；
Described judge module is specifically for judging that adjacent clock signal receiving unit is the most just receiving the sequential of clock signal
Really, as correctly, then send output signal, such as mistake, then send shutdown signal.
In level shift circuit of the present invention, described closedown module is specifically for receiving described shutdown signal
Time, the plurality of clock signal is converted into high level clock signal, or is converted into low level clock signal, to close described electricity
Translational shifting chip.
In level shift circuit of the present invention, described logical signal includes grid enabling signal, described receiver module
Including:
Grid enabling signal receives unit, is used for receiving described grid enabling signal；
Described judge module is the most correct specifically for the reception sequential judging described grid enabling signal, as correctly, then sends out
Send output signal, such as mistake, then send shutdown signal.
In level shift circuit of the present invention, described logical signal also includes multiple clock signal, described closedown
The plurality of clock signal, specifically for when receiving described shutdown signal, is converted into high level clock signal by module, or
It is converted into low level clock signal, to close described level shift chip.
In level shift circuit of the present invention, described output module includes:
Converting unit, for when receiving described output signal, is converted into high voltage logic letter by described logical signal
Number；
Output unit, exports described high voltage logic signal, to control drive circuit.
The embodiment of the present invention also provides for a kind of display panels, and it includes level shift circuit and drive circuit；
Wherein, described level shift circuit includes:
Time schedule controller, for output for controlling the logical signal of drive circuit；
Level shift chip, is electrically connected with described time schedule controller, including:
Receiver module, is electrically connected with described sequencing contro, is used for receiving described logical signal；
Judge module, the most correct for judging the reception sequential of described logical signal, as correctly, then send output letter
Number, such as mistake, then send shutdown signal；
Output module, for when receiving described output signal, exports described logical signal, to control drive circuit；
Close module, for when receiving described shutdown signal, close described level shift chip.
In display panels of the present invention, described logical signal includes multiple clock signal, described receiver module
Including:
Multiple clock signals receive unit, are respectively used to receive the plurality of clock signal；
Described judge module is specifically for judging that adjacent clock signal receiving unit is the most just receiving the sequential of clock signal
Really, as correctly, then send output signal, such as mistake, then send shutdown signal.
In display panels of the present invention, described closedown module is specifically for receiving described shutdown signal
Time, the plurality of clock signal is converted into high level clock signal, or is converted into low level clock signal, to close described electricity
Translational shifting chip.
In display panels of the present invention, described logical signal includes grid enabling signal, described receiver module bag
Include:
Grid enabling signal receives unit, is used for receiving described grid enabling signal；
Described judge module is the most correct specifically for the reception sequential judging described grid enabling signal, as correctly, then sends out
Send output signal, such as mistake, then send shutdown signal.
Compared to existing level shift circuit and display panels, the level shift circuit of the present invention and liquid crystal display
Panel is by arranging receiver module, judge module, output module and closing module, when the reception sequential of logical signal is correct,
Export described logical signal, to control drive circuit；When the reception timing error of logical signal, close level shift chip.
Thus the logical signal avoiding mistake sequential causes display panels picture exception, electric current excessive, even causes liquid crystal
Show the situation of panel breakage；Solve the technical problem that existing picture is abnormal, electric current is excessive and safety is relatively low.
For the foregoing of the present invention can be become apparent, preferred embodiment cited below particularly, and coordinate institute's accompanying drawings, make
Describe in detail as follows:
Accompanying drawing explanation
Fig. 1 is the structural representation of the first preferred embodiment of the level shift circuit of the present invention；
Fig. 2 is that the clock signal of the level shift circuit of the present invention receives sequential chart；
Fig. 3 is the structural representation of the second preferred embodiment of the level shift circuit of the present invention；
Fig. 4 is that the grid enabling signal of the level shift circuit of the present invention receives sequential chart.
Detailed description of the invention
The explanation of following embodiment is particular implementation that is graphic with reference to add, that implement in order to illustrate the present invention may be used to
Example.The direction term that the present invention is previously mentioned, such as " on ", D score, "front", "rear", "left", "right", " interior ", " outward ", " side "
Deng, it is only the direction with reference to annexed drawings.Therefore, the direction term of use is to illustrate and understand the present invention, and is not used to
Limit the present invention.
In the drawings, the unit that structure is similar is to represent with identical label.
Refer to the structural representation of the first preferred embodiment of the level shift circuit that Fig. 1, Fig. 1 are the present invention.This is excellent
Select the level shift circuit of embodiment for corresponding drive circuit being controlled by the output of control logical signal, originally
The level shift circuit 1 of preferred embodiment includes time schedule controller 2 and level shift chip 3.Wherein, time schedule controller 2, go out use
In the logical signal controlling drive circuit；Level shift chip 3 is electrically connected with time schedule controller 2, including receiver module 31, sentences
Disconnected module 32, output module 33 and closedown module 34.
Receiver module 31, is electrically connected with sequencing contro, is used for receiving logical signal；Judge module 32, patrols for judgement
The reception sequential collecting signal is the most correct, as correctly, then sends output signal, such as mistake, then sends shutdown signal；Output module
33, for when receiving output signal, output logic signal, to control drive circuit；Close module 34, for receiving
During shutdown signal, close level shift chip.
When logical signal includes multiple clock signal, receiver module 31 includes that clock signal receives unit 311, this clock
Signal receiving unit 311 includes that the first clock signal receives unit, second clock signal receiving unit ..., N clock signal
Receiving unit, these clock signals receive unit and are respectively used to receive multiple clock signal.
Output module 33 includes converting unit 331 and output unit 332, wherein converting unit 331, for receive defeated
When going out signal, logical signal is converted into high voltage logic signal；Output unit 332, output HIGH voltage logical signal, to control
Drive circuit.
When the level shift circuit 1 of this preferred embodiment uses, first time schedule controller 2 output logic signal, to control
Drive circuit (Source drive, gate driver and VCOM Polarity Control) on display panels, thus realize analog rgb signal
Display control.
Wherein, logical signal specifically includes the STH (row data commencing signal) for controlling Source drive, MPOL (data
Reverse signal at once), for controlling the signals such as the STV (grid enabling signal) of gate driver, CPV (grid movable signal).These are patrolled
The output collecting signal all has certain timing requirements, if wherein the output of STV and CLK (clock signal) there occurs that sequential is wrong
By mistake, will result in that display panels electric current is excessive, picture output abnormality, the TFT even resulting in LCD intralaminar part damages.
Simultaneously because the logical signal of time schedule controller 2 output is low voltage logic signal, it is impossible to directly to LCD
Drive circuit on plate is controlled, it is therefore desirable to by level shift circuit 3, low voltage logic signal is converted into high pressure logic
Signal could realize the control to drive circuit.
Then, level shift chip 3 receives the logical signal of the low-voltage of time schedule controller 2 output, patrolling low-voltage
Collect signal and be converted into high-tension logical signal.In order to prevent display panels because of time schedule controller 2 output error sequential
STV and CLK and suffer damage, level shift circuit 3 be provided with receiver module 31, judge module 32, output module 33 and close
Module 34, the just output logic signal when determining that STV and CLK output timing is correct, otherwise close level shift chip, forbid defeated
Go out logical signal.
Concrete, first receiver module 31 receives the logical signal of time schedule controller 2 output, and wherein receiver module 31 includes
Clock signal receives unit 311, and this clock signal receives unit 311 and includes that the first clock signal receives unit, and second clock is believed
Number receive unit ..., N clock signal receives unit, and these clock signals receive unit and are respectively used to receive multiple clock letter
Number, receive the first clock signal clk IN as the first clock signal receives unit1N clock signal receives unit and receives N clock
Signal CLKINn.Then judge module 32 judges that adjacent clock signal receiving unit receives the sequential of clock signal the most correctly,
As correctly, then send and output signal to output module 33, such as mistake, then send shutdown signal to closing module 34.
Concrete, refer to Fig. 2, it is assumed that the first clock signal receives unit and receives CLKIN1Receive with second clock signal
Unit receives CLKIN2Time interval be Δ t1, second clock signal receiving unit receives CLKIN2And CLKIN3Time between
It is divided into Δ t2, it is judged that module 32 is by judging Δ t1With Δ t2Between difference whether be in preset difference value in the range of when determining
Clock signal sequence is the most correct, if in the range of being not at preset difference value, then judges clock signal timing error, sends and close letter
Number give close module 34；If in the range of being in preset difference value, then judging that clock signal sequential is correct, transmission outputs signal to defeated
Go out module 33.
After output module 33 receives output signal, its interior converting unit 331 is by patrolling that receiver module 31 receives
Collect signal and be converted into high voltage logic signal；Then export to drive circuit, to control drive circuit by output unit 332.
After closedown module 34 receives shutdown signal, clock signal is received multiple clock signals that unit 311 receives
It is wholly converted into high level clock signal, or is wholly converted into low level clock signal, thus reach to close level shift core
The purpose of sheet 3, to prevent the logical signal of mistake sequential from causing damage display panels.
The level shift circuit of this preferred embodiment is by arranging receiver module, judge module, output module and closing mold closing
Block, when the reception sequential of logical signal is correct, output logic signal, to control drive circuit；When the reception of logical signal
During sequence mistake, close level shift chip, thus the logical signal avoiding mistake sequential causes display panels picture different
Often, electric current excessive, and hurtful situation, improve the safety of display panels.
Refer to the structural representation of the second preferred embodiment of the level shift circuit that Fig. 3, Fig. 3 are the present invention.This is excellent
The level shift circuit 1 selecting embodiment includes time schedule controller 2 and level shift chip 3.Wherein, time schedule controller 2, go out for
Control the logical signal of drive circuit；Level shift chip 3 is electrically connected with time schedule controller 2, including receiver module 31, judges
Module 32, output module 33 and closedown module 34.
On the basis of the first preferred embodiment, the receiver module 31 of this preferred embodiment also includes that grid enabling signal receives
Unit 312.This grid enabling signal receives unit 312 for receiving grid enabling signal STVIN.
When the level shift circuit 1 of this preferred embodiment uses, after time schedule controller 2 output logic signal, grid start letter
Number receive unit 312 receive the grid enabling signal in logical signal；Then judge module 32 judges that grid enabling signal receives unit
312 receive the sequential of clock signal the most correctly, as correctly, then send and output signal to output module 33, such as mistake, then send
Shutdown signal is given and is closed module 34.
Concrete, refer to Fig. 4, it is assumed that grid enabling signal receives unit 312 and receives the time interval of two adjacent S TVIN
For Δ t3, it is judged that module 32 is by calculating Δ t3With reference value Δ t4Difference DELTA t, and judge Δ t whether more than predetermined threshold value,
Determine that the reception sequential of STVIN is the most correct.If greater than predetermined threshold value, then judge that STVIN receives timing error, sends and closes
Close signal to closing module 34；Such as no more than predetermined threshold value, then judge that STVIN receives sequential correct, send output signal to defeated
Go out module 33.
After output module 33 receives output signal, its interior converting unit 331 is by patrolling that receiver module 31 receives
Collect signal and be converted into high voltage logic signal；Then export to drive circuit, to control drive circuit by output unit 332.
After closedown module 34 receives shutdown signal, clock signal is received multiple clock signals that unit 311 receives
It is wholly converted into high level clock signal, or is wholly converted into low level clock signal, thus reach to close level shift core
The purpose of sheet 3, to prevent the logical signal of mistake sequential from causing damage display panels.
The specific works principle of the time schedule controller of this preferred embodiment is preferred with the first of above-mentioned level shift circuit
The specific works principle of the time schedule controller described in embodiment is same or similar, specifically refers to above-mentioned level shift circuit
Associated description in first preferred embodiment.
The present invention also provides for a kind of display panels, and it includes level shift circuit and drive circuit；Wherein, level moves
Position circuit includes time schedule controller and level shift chip.
Time schedule controller, for output for controlling the logical signal of drive circuit；Level shift chip, with sequencing contro
Device is electrically connected with.Wherein level shift chip includes receiver module, judge module, output module and closedown module.
Receiver module, is electrically connected with sequencing contro, is used for receiving logical signal；Judge module, believes for decision logic
Number reception sequential whether correct, as correctly, then send output signal, such as mistake, then send shutdown signal；Output module, uses
In when receiving output signal, output logic signal, to control drive circuit；Close module, for receiving closedown letter
Number time, close level shift chip.
Preferably, logical signal includes multiple clock signal, and receiver module includes multiple signal receiving unit, specifically describes
As follows:
Multiple clock signals receive unit, are respectively used to receive multiple clock signal；
Judge module is the most correct specifically for the sequential judging adjacent clock signal receiving unit reception clock signal, as
Correctly, then send output signal, such as mistake, then send shutdown signal.
Preferably, multiple clock signals, specifically for when receiving shutdown signal, are converted into high level by closedown module
Clock signal, or it is converted into low level clock signal, to close level shift chip.
Preferably, logical signal includes grid enabling signal, and receiver module includes that grid enabling signal receives unit, specifically describes
As follows:
Grid enabling signal receives unit, for receiving grid enabling signal；
Judge module is the most correct specifically for the reception sequential judging grid enabling signal, as correctly, then sends output letter
Number, such as mistake, then send shutdown signal.
In the specific works principle of the display panels of the present invention and the preferred embodiment of above-mentioned level shift circuit
Description same or similar, specifically refer to the associated description in the preferred embodiment of above-mentioned level shift circuit.
The level shift circuit of the present invention and display panels are by arranging receiver module, judge module, output module
And closedown module, when the reception sequential of logical signal is correct, output logic signal, to control drive circuit；At logical signal
Reception timing error time, close level shift chip.Thus the logical signal avoiding mistake causes display panels to be drawn
Face is abnormal, electric current is excessive, the situation even causing display panels to damage, and improves the safety of display panels；Solve
The technical problem that existing picture of having determined is extremely, electric current is excessive and safety is relatively low.
In sum, although the present invention is disclosed above with preferred embodiment, but above preferred embodiment and be not used to limit
The present invention processed, those of ordinary skill in the art, without departing from the spirit and scope of the present invention, all can make various change and profit
Decorations, therefore protection scope of the present invention defines in the range of standard with claim.
Claims (10)
1. a level shift circuit, it is characterised in that including:
Time schedule controller, for output for controlling the logical signal of drive circuit；
Level shift chip, is electrically connected with described time schedule controller, including:
Receiver module, is electrically connected with described sequencing contro, is used for receiving described logical signal；
Judge module, the most correct for judging the reception sequential of described logical signal, as correctly, then send output signal, as
Mistake, then send shutdown signal；
Output module, for when receiving described output signal, exports described logical signal, to control drive circuit；
Close module, for when receiving described shutdown signal, close described level shift chip.
Level shift circuit the most according to claim 1, it is characterised in that described logical signal includes that multiple clock is believed
Number, described receiver module includes:
Multiple clock signals receive unit, are respectively used to receive the plurality of clock signal；
Described judge module is the most correct specifically for the sequential judging adjacent clock signal receiving unit reception clock signal, as
Correctly, then send output signal, such as mistake, then send shutdown signal.
Level shift circuit the most according to claim 2, it is characterised in that described closedown module is specifically for receiving
During described shutdown signal, the plurality of clock signal is converted into high level clock signal, or is converted into low level clock signal,
To close described level shift chip.
Level shift circuit the most according to claim 1, it is characterised in that described logical signal includes grid enabling signal,
Described receiver module includes:
Grid enabling signal receives unit, is used for receiving described grid enabling signal；
Described judge module is the most correct specifically for the reception sequential judging described grid enabling signal, as correctly, then sends defeated
Go out signal, such as mistake, then send shutdown signal.
Level shift circuit the most according to claim 4, it is characterised in that described logical signal also includes that multiple clock is believed
Number, the plurality of clock signal, specifically for when receiving described shutdown signal, is converted into high level by described closedown module
Clock signal, or it is converted into low level clock signal, to close described level shift chip.
Level shift circuit the most according to claim 1, it is characterised in that described output module includes:
Converting unit, for when receiving described output signal, is converted into high voltage logic signal by described logical signal；
Output unit, exports described high voltage logic signal, to control drive circuit.
7. a display panels, it is characterised in that including: level shift circuit and drive circuit；
Wherein, described level shift circuit includes:
Time schedule controller, for output for controlling the logical signal of drive circuit；
Level shift chip, is electrically connected with described time schedule controller, including:
Receiver module, is electrically connected with described sequencing contro, is used for receiving described logical signal；
Judge module, the most correct for judging the reception sequential of described logical signal, as correctly, then send output signal, as
Mistake, then send shutdown signal；
Output module, for when receiving described output signal, exports described logical signal, to control drive circuit；
Close module, for when receiving described shutdown signal, close described level shift chip.
Display panels the most according to claim 7, it is characterised in that described logical signal includes that multiple clock is believed
Number, described receiver module includes:
Multiple clock signals receive unit, are respectively used to receive the plurality of clock signal；
Described judge module is the most correct specifically for the sequential judging adjacent clock signal receiving unit reception clock signal, as
Correctly, then send output signal, such as mistake, then send shutdown signal.
Display panels the most according to claim 8, it is characterised in that described closedown module is specifically for receiving
During described shutdown signal, the plurality of clock signal is converted into high level clock signal, or is converted into low level clock signal,
To close described level shift chip.
Display panels the most according to claim 7, it is characterised in that described logical signal includes grid enabling signal,
Described receiver module includes:
Grid enabling signal receives unit, is used for receiving described grid enabling signal；
Described judge module is the most correct specifically for the reception sequential judging described grid enabling signal, as correctly, then sends defeated
Go out signal, such as mistake, then send shutdown signal.
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| CN201610891410.9A CN106228944B (en) | 2016-10-12 | 2016-10-12 | Level shift circuit and liquid crystal display panel |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201610891410.9A CN106228944B (en) | 2016-10-12 | 2016-10-12 | Level shift circuit and liquid crystal display panel |
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| CN106228944B CN106228944B (en) | 2019-02-01 |
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| CN107424578A (en) * | 2017-08-15 | 2017-12-01 | 京东方科技集团股份有限公司 | A kind of drive circuit, display panel, display device and its control method |
| WO2019033825A1 (en) * | 2017-08-15 | 2019-02-21 | 京东方科技集团股份有限公司 | Drive circuit and control method therefor, and display panel, and display apparatus |
| US10726755B2 (en) | 2017-08-15 | 2020-07-28 | Hefei Xinsheng Optoelectronics Technology Co., Ltd. | Driving circuit, control method thereof, display panel and display device |
| CN107799043A (en) * | 2017-11-20 | 2018-03-13 | 深圳市华星光电技术有限公司 | Detection method, system and the electronic equipment of GOA circuits |
| CN109961732B (en) * | 2017-12-22 | 2022-08-02 | 乐金显示有限公司 | Display device |
| CN109961732A (en) * | 2017-12-22 | 2019-07-02 | 乐金显示有限公司 | Show equipment |
| CN108492791B (en) * | 2018-03-26 | 2019-10-11 | 京东方科技集团股份有限公司 | A kind of display driver circuit and its control method, display device |
| WO2019184355A1 (en) * | 2018-03-26 | 2019-10-03 | 京东方科技集团股份有限公司 | Display driving circuit and driving method therefor, and display device |
| US10930191B2 (en) | 2018-03-26 | 2021-02-23 | Chongqing Boe Optoelectronics Technology Co., Ltd. | Display driving circuit and driving method therefor, display device |
| CN108492791A (en) * | 2018-03-26 | 2018-09-04 | 京东方科技集团股份有限公司 | A kind of display driver circuit and its control method, display device |
| CN110136628A (en) * | 2019-05-29 | 2019-08-16 | 京东方科技集团股份有限公司 | Anti- blank screen circuit and method, driving circuit, display device |
| CN110136628B (en) * | 2019-05-29 | 2022-06-17 | 京东方科技集团股份有限公司 | Anti-black screen circuit and method, driving circuit and display device |
| CN111161664A (en) * | 2020-02-13 | 2020-05-15 | Tcl华星光电技术有限公司 | Display device and terminal |
| CN111341242A (en) * | 2020-04-09 | 2020-06-26 | Tcl华星光电技术有限公司 | Circuit driving system, driving chip and display device |
| CN114495860A (en) * | 2022-03-11 | 2022-05-13 | 深圳市华星光电半导体显示技术有限公司 | Display drive circuit and display drive device |
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| CN106228944B (en) | 2019-02-01 |
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