CN110136628B

CN110136628B - Anti-black screen circuit and method, driving circuit and display device

Info

Publication number: CN110136628B
Application number: CN201910458480.9A
Authority: CN
Inventors: 翁彬; 许炜泽; 翁祖伟; 赖意强
Original assignee: BOE Technology Group Co Ltd; Fuzhou BOE Optoelectronics Technology Co Ltd
Current assignee: BOE Technology Group Co Ltd; Fuzhou BOE Optoelectronics Technology Co Ltd
Priority date: 2019-05-29
Filing date: 2019-05-29
Publication date: 2022-06-17
Anticipated expiration: 2039-05-29
Also published as: CN110136628A

Abstract

The invention discloses a black screen prevention circuit and method, a driving circuit and a display device, and belongs to the technical field of display. The black screen prevention circuit is applied to the drive circuit of the display, the drive circuit comprises an integrated power management circuit, a level conversion circuit and a counter control register, and the black screen prevention circuit comprises: a determination sub-circuit configured to determine whether or not there are more than two clock signals among the plurality of clock signals output from the counter control register and the clock signals are active levels at the same time; and the control sub-circuit is configured to cut off the grid high level signal and the grid low level signal output by the integrated power management circuit to the level conversion circuit when the determining sub-circuit determines that more than two clock signals are simultaneously at effective levels, so that the phenomenon of black screen when the liquid crystal display is started is avoided.

Description

Anti-black screen circuit and method, driving circuit and display device

Technical Field

The invention relates to the technical field of display, in particular to a black screen prevention circuit and method, a driving circuit and a display device.

Background

With the development of display technology and the increase of the material level of people, the requirements of various aspects of the display are higher and higher. Aiming at the existing products, the elimination of various display defects is an important way for improving the product quality. The current liquid crystal display products, especially large-size liquid crystal display products, are prone to a black screen phenomenon in a starting or low-temperature state.

Disclosure of Invention

The embodiment of the invention provides a black screen prevention circuit and method, a driving circuit and a display device, which can solve the problem of starting up a black screen of a liquid crystal display product. The technical scheme is as follows:

in one aspect, an embodiment of the present invention provides a black screen prevention circuit, where the black screen prevention circuit is applied to a driving circuit of a display, the driving circuit includes a PMIC, a level shift L/S circuit, and a counter control register TCON, the L/S circuit is electrically connected to the PMIC and the TCON, respectively, and the black screen prevention circuit includes:

a determination sub-circuit configured to determine whether or not there are more than two clock signals among the plurality of clock signals output from the TCON while being active levels;

and the control sub-circuit is configured to cut off VGH and VGL signals output to the L/S circuit by the PMIC when the determining sub-circuit determines that more than two clock signals are simultaneously in an effective level.

In an implementation manner of the embodiment of the present invention, the determining sub-circuit includes:

the multi-channel analog-to-digital converters are arranged in one-to-one correspondence to the multi-channel clock signals and are configured to convert the multi-channel clock signals from analog signals to digital signals;

and the processing device is configured to determine whether more than two clock signals are simultaneously in an effective level according to the digital signals converted from the multipath clock signals.

In one implementation manner of the embodiment of the present invention, the control sub-circuit includes:

a first switch including a VGH input terminal, an output terminal, and a control terminal; the control end of the first switch is electrically connected with the output end of the determining sub-circuit, and the output end of the first switch is electrically connected with the L/S circuit;

a second switch comprising a VGL input terminal, an output terminal, and a control terminal; and the control end of the second switch is electrically connected with the output end of the determining sub-circuit, and the output end of the second switch is electrically connected with the L/S circuit.

In an implementation manner of the embodiment of the present invention, the control sub-circuit is further configured to control the PMIC to output VGH and VGL signals to the L/S circuit when the determining sub-circuit determines that there are no more than two clock signals and the two clock signals are active levels at the same time.

In an implementation manner of the embodiment of the present invention, the black screen prevention circuit further includes an impedance matching sub-circuit, and the impedance matching sub-circuit is electrically connected to the control sub-circuit, the determination sub-circuit, the integrated power management circuit, and the level conversion circuit, respectively.

On the other hand, the embodiment of the invention also provides a driving circuit, which comprises the black screen prevention circuit.

On the other hand, the embodiment of the invention also provides a display device, which comprises the driving circuit.

On the other hand, an embodiment of the present invention further provides a method for preventing a black screen, where the method is applied to a driving circuit of a display, the driving circuit includes a PMIC, an L/S circuit and a TCON, and the L/S circuit is electrically connected to the PMIC and the TCON respectively, and the method includes:

determining whether more than two paths of clock signals exist in the multi-path clock signals output by the TCON and are simultaneously effective levels;

and when the fact that more than two clock signals are simultaneously at effective levels is determined, the gate high level signal and the gate low level signal which are output to the L/S circuit by the PMIC are cut off.

In an implementation manner of the embodiment of the present invention, the determining whether there are more than two clock signals in the multiple clock signals output by the TCON and the clock signals are active levels at the same time includes:

converting the multi-path clock signals from analog signals to digital signals;

and determining whether more than two paths of clock signals are simultaneously effective electrical levels according to the digital signals converted from the plurality of paths of clock signals.

In an implementation manner of the embodiment of the present invention, when it is determined that there are two or more clock signals that are active at the same time, the cutting off the gate high level signal and the gate low level signal output by the PMIC to the L/S circuit includes:

outputting a first control signal to a first switch and a second switch, wherein the first control signal is used for controlling the first switch and the second switch to be switched off;

the first switch comprises a VGH input end, an output end and a control end, the second switch comprises a VGL input end, an output end and a control end, the control ends of the first switch and the second switch are used for receiving the control signal, and the output end of the first switch and the output end of the second switch are electrically connected with the L/S circuit.

The technical scheme provided by the embodiment of the invention has the following beneficial effects:

in the embodiment of the invention, whether more than two clock signals are simultaneously at effective level or not in the multi-path clock signals output by the TCON is determined, and when more than two clock signals are simultaneously at effective level, VGH and VGL signals output to the L/S circuit by the PMIC are cut off, so that when more than two clock signals are simultaneously at effective level, the L/S circuit cannot receive the VGH and the VGL and cannot output the VGH and the VGL to the gate drive circuit, and the gate drive circuit cannot simultaneously output gate conducting levels to a plurality of rows of pixel units when more than two clock signals are simultaneously at effective level, so that the plurality of rows of pixel units are driven to work simultaneously, the PMIC is prevented from triggering overload protection, and the phenomenon of black screen at startup (or in a low temperature state) is avoided.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.

FIG. 1 is a partial schematic diagram of a driver circuit;

FIG. 2 is a block diagram of a black screen prevention circuit according to an embodiment of the present invention;

FIG. 3 is a detailed structural diagram of a black screen prevention circuit provided by an embodiment of the present invention;

FIG. 4 is a detailed structural diagram of a control sub-circuit according to an embodiment of the present invention;

fig. 5 is a flowchart of a method for preventing a screen from being blacked out according to an embodiment of the present invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more apparent, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

To facilitate an understanding of the solutions provided herein. The following is a brief description of the display:

the display includes a display panel and a driving circuit. The display panel is used for emitting display patterns, and the driving circuit is used for providing signals required by the display panel to display and controlling the work of the display panel through the signals.

The display panel has different structures based on the types of displays, and for example, a liquid crystal display includes an array substrate, a color filter substrate aligned with the array substrate, and a liquid crystal layer interposed between the array substrate and the color filter substrate. The array substrate comprises a grid line and a data line, the grid line and the data line are crossed to form a plurality of sub-pixel regions, a thin film transistor is arranged in each sub-pixel region, the grid electrode of the thin film transistor is connected with the grid line, the source electrode of the thin film transistor is connected with the data line, the drain electrode of the thin film transistor is connected with a pixel electrode, and the on-off of the thin film transistor can be controlled through the grid line, so that whether signals of the data line are written into the pixel electrode or not is controlled. Here, the display may be other types of displays such as an organic light emitting diode display, in addition to the liquid crystal display.

The driving circuit is used for providing signals for the grid lines and the data lines so as to control the operation of the display panel. The driving circuit generally includes a counter Control Register (TCON) circuit, a gate driving circuit, and a source driving circuit. The TCON circuit is configured to provide various voltage signals, such as a start Signal (STV), a clock signal (CLK), a low level signal (VSS), a noise reduction voltage signal (VDDO/VDDE), and the like, to support operations of the gate driving circuit and the source driving circuit, and the gate driving circuit and the source driving circuit respectively generate the gate driving signal and the source driving signal using the signals output by the TCON circuit. The TCON circuit, the source driver circuit, and the Gate driver circuit may be implemented by using integrated circuit boards, and the Gate driver circuit may also be implemented by using a shift register, that is, a Gate On Array (GOA) On the display panel, that is, a shift register unit (GOA unit) On the display panel is used as the Gate driver circuit.

Fig. 1 is a partial schematic diagram of a driving circuit, which mainly shows a TCON circuit portion related to gate driving, and does not show a TCON circuit portion related to source driving (such as a Gamma circuit). Referring to fig. 1, the driving circuit includes a Power Management IC (PMIC) 10, a Level Shift (L/S) circuit 20, and a TCON IC 30 (hereinafter, referred to as TCON), and the L/S circuit 20 is electrically connected to the PMIC10 and the TCON 30, respectively. The PMIC10 is configured to output a digital power signal (DVDD), an analog power signal (AVDD), a half-analog power signal (HAVDD), a gate high level (VGH), a gate low level (VGL), and the like according to the input signal Vin. The TCON 30 is internally integrated with a crystal oscillator, and is capable of generating a clock signal CLKT (low level 0V, high level 3.3V), the L/S circuit 20 is used for generating signals such as STV, CLK, VSS, VDDO, VDDE, VGL, VGH, etc. according to the signals output by the PMIC and the TCON IC and providing the signals to the gate driving circuit 40, the gate driving circuit 40 outputs a Gout signal to the gate line under the control of the signal output by the L/S circuit 20, and the Gout signal is VGL or VGH in the operation stage. Here, VGL and VGH output by the L/S circuit 20 to the gate driving circuit 40 are VGL and VGH output by the PMIC10 to the L/S circuit 20, and the gate driving circuit 40 determines to which gate line of the display panel VGH is output and which gate line outputs VGL according to the level of the CLK signal.

The TCON 30 usually outputs multiple CLKT signals at the same time, for example, 10 channels, and the multiple CLK signals are processed by the L/S circuit 20 to obtain multiple CLK signals, when the display panel works, only one channel of the multiple CLK signals (or multiple CLKT signals) is at an active level (usually, a high level) at any time, so that it can be ensured that the gate driving circuit 40 only outputs a gate-on level to one row of pixel units at any time when it works. However, in the actual operation of the display panel, when the display panel is turned on or operates at a low temperature, the TCON 30 may be in an uncontrollable (un kown) state, at this time, multiple signals may occur in multiple CLKT signals and be at a high level at the same time, which may cause the gate driving circuit 40 to output a gate-on level to multiple rows of pixel units at the same time, and the multiple rows of pixel units operate at the same time, at this time, the driving circuit needs to charge the multiple rows of pixel units at the same time, which greatly increases the load of the data line, and finally causes the PMIC10 to trigger load protection, cut off the power supply of the entire display panel, and cause a black screen phenomenon at the turn on (or in the low temperature state).

Fig. 2 is a block diagram of a black-screen prevention circuit according to an embodiment of the present invention. Referring to fig. 2, the black screen prevention circuit 50 is applied to the driving circuit of the aforementioned display, and the black screen prevention circuit 50 includes:

a determination sub-circuit 51 configured to determine whether or not there are more than two clock signals among the plurality of clock signals output from the TCON 30 at the same time as an active level;

and a control sub-circuit 52 configured to cut off the VGH and VGL signals output from the PMIC10 to the L/S circuit 20 when the determination sub-circuit 51 determines that there are two or more clock signals simultaneously being active levels.

The switching off of the VGH and VGL signals output by the PMIC10 means that the VGH and VGL signals output by the PMIC10 cannot be transmitted to the L/S circuit 20.

In the embodiment of the present invention, by determining whether two or more clock signals are simultaneously at an effective level in the multiple clock signals output by the TCON 30, and when two or more clock signals are simultaneously at an effective level, the VGH and VGL signals output by the PMIC10 are cut off, so that when two or more clock signals are simultaneously at an effective level, the L/S circuit cannot receive the VGH and VGL, and cannot output the VGH and VGL to the gate driving circuit, which makes the gate driving circuit not output the gate on level to the multiple rows of pixel units at the same time when two or more clock signals are simultaneously at an effective level, and further drives the multiple rows of pixel units to work at the same time, thereby avoiding triggering overload protection by the PMIC10 and avoiding a black screen phenomenon at startup (or in a low temperature state).

It should be noted that the black screen at power-on (or in low temperature state) referred to in this application refers to the black screen state that the display is in the unpowered state when the display is at power-on (or in low temperature state), and does not include the state when the display displays the black screen in the powered state. The non-powered state means that the display panel of the display is not driven by an electric signal.

The clock signal CLKT is usually a square wave signal, usually, the low level of the clock signal CLKT is 0V, the high level is 3.3V, usually, the high level is an effective level, and in the multi-path clock signal CLKT simultaneously output by the TCON 30, the effective level does not appear simultaneously, so that it can be ensured that the subsequent gate driving circuit does not drive the pixel units of the display panel to work simultaneously when controlling the pixel units. However, as mentioned above, TCON 30 is not controlled during the boot-up phase, and it is easy to have multiple clock signals CLKT at the active level at the same time. How the anti-blank screen circuit 50 detects whether the plurality of clock signals CLKT are simultaneously at the active level according to the embodiment of the present invention is described below with reference to fig. 3.

Fig. 3 is a schematic structural diagram of a detailed anti-black screen circuit according to an embodiment of the present invention. Referring to fig. 3, the determination sub-circuit 51 includes:

the multiple analog-to-digital converters 511 (only one is shown in the figure as an example), the multiple analog-to-digital converters 511 are arranged in one-to-one correspondence with the multiple clock signals, and are configured to convert the multiple clock signals from analog signals to digital signals;

and the processing device 512 is configured to determine whether more than two clock signals are simultaneously active levels according to the digital signals converted from the multiple clock signals.

In the embodiment of the present invention, in order to detect whether there are more than two clock signals that are valid levels at the same time, an analog-to-digital converter 511 converts an analog signal output by the TCON into a digital signal, after analog-to-digital conversion, the high and low levels of the analog signal are converted into binary values 1 and 0, and by comparing the values of the digital signal, it can be determined whether there are more than two clock signals that are valid levels at the same time. For example, when the high level is the active level, when the binary values converted by the two or more clock signals are all 1, it indicates that the two or more clock signals are active levels at the same time.

It should be noted that, since the analog signal is a continuous signal, and the digital signal is a discrete signal, and is obtained by sampling and converting the analog signal by the analog-to-digital converter 511, in order to ensure the synchronization of the multiple digital signals, the processing device 512 may be further configured to provide the same signal as the clock signal for the multiple analog-to-digital converter 511, and the multiple analog-to-digital converter 511 performs sampling under the control of the clock signal. In this way, the same bit of the digital signal output by the multi-channel analog-to-digital converter 511 indicates the level of the multi-channel clock signal at the same time, and the processing device 512 only needs to determine whether more than two bits of the same bit of the multi-channel digital signal are 1 (high level valid) or 0 (low level valid). Here, the processing device 512 may implement the above determination through a logical operation. Taking the high level (bit 1) as an example, for example, any two paths of digital signals are subjected to and operation, if the result of the and operation is 1, it indicates that more than two paths of clock signals are simultaneously active levels, and if the results of all the and operations are 0, it indicates that more than two paths of clock signals are not simultaneously active levels. If the low level is valid, performing or operation, for example, performing or operation on any two paths of digital signals, if the result of the or operation is 0, it indicates that more than two paths of clock signals are valid levels at the same time, and if the results of all or operation are 1, it indicates that more than two paths of clock signals are not valid levels at the same time.

The method is used for detecting whether the multiple clock signals CLKT are at the effective level at the same time, the method is simple and accurate, and a foundation is provided for subsequent control.

It should be noted that the control sub-circuit 52 of the present application may not only cut off the VGH and VGL signals output from the PMIC10 to the L/S circuit 20 when more than two clock signals are active at the same time, but also cut off the VGH and VGL signals output from the PMIC10 to the L/S circuit 20 when no clock signal is active. In this case, although the display panel does not operate finally, the VGH and VGL signals are cut off, so that the gate driver circuit does not need to drive the TFT of the display panel with a gate-off level, thereby reducing power consumption.

Referring again to fig. 3, the control sub-circuit 52 includes:

the first switch 521, the first switch 521 includes a VGH input terminal, an output terminal and a control terminal; the control terminal of the first switch 521 is electrically connected with the output terminal of the determination sub-circuit 51, and the output terminal of the first switch 521 is electrically connected with the L/S circuit 20;

a second switch 522, the second switch 522 including a VGL input terminal, an output terminal, and a control terminal; a control terminal of the second switch 522 is electrically connected to the output terminal of the determination sub-circuit 51, and an output terminal of the second switch 522 is electrically connected to the L/S circuit 20.

Accordingly, the processing device 512 is configured to output a first control signal to the first switch 521 and the second switch 522 when there are more than two clock signals being active at the same time, and the first control signal is used for controlling the first switch 521 and the second switch 522 to be turned off.

The control sub-circuit 52 is realized in the above manner, and on one hand, the circuit is simple, and on the other hand, the control manner is simple.

Fig. 4 is a detailed structural schematic diagram of a control sub-circuit according to an embodiment of the present invention. Referring to fig. 4, the first switch 521 and the second switch 522 may be Thin Film Transistors (TFTs), such as NMOS Thin Film transistors or PMOS Thin Film transistors. The first control signal here is different according to the type of the thin film transistor, for example, when the thin film transistor is an NMOS thin film transistor, the first control signal is a low level signal, and when the thin film transistor is a PMOS thin film transistor, the first control signal is a high level signal.

The first switch 521 and the second switch 522 may be implemented by using other types of switches besides TFTs as the first switch and the second switch, which is not limited in this application.

As shown in fig. 4, the gates of the first switch 521 and the second switch 522 are control terminals, and are electrically connected to the output terminal of the determination sub-circuit 51; the sources of the first switch 521 and the second switch 522 are VGH (or VGL) input terminals, and are electrically connected with the output terminal of the PM IC 10; the drains of the first switch 521 and the second switch 522 are output terminals and are electrically connected to the input terminals of the L/S circuit 20.

In order to implement the adjustment function of impedance matching, etc. of the circuit, the anti-shadow circuit may further include an impedance matching sub-circuit 53, and the impedance matching sub-circuit 53 is electrically connected to the control sub-circuit 52, the determination sub-circuit 51, the PMIC10 and the L/S circuit 20 respectively, for implementing impedance matching between the circuits.

The impedance matching sub-circuit 53 may include two resistors R1, two resistors R2, and two resistors R3, the two resistors R1 are respectively connected between the output terminal of the determination sub-circuit 51 and the gate of the first switch 521, and between the output terminal of the determination sub-circuit 51 and the gate of the second switch 522, the two resistors R2 are respectively connected between the gate and the source of the first switch 521, and between the gate and the source of the second switch 522, and the two resistors R3 are respectively connected between the drain of the first switch 521 and the ground, and between the drain of the second switch 522 and the ground.

In the embodiment of the present invention, the control sub-circuit 52 is further configured to control the VGH and VGL signals output by the PMIC10 to be output to the L/S circuit 20 when there are no more than two clock signals that are active at the same time.

That is, the processing device 512 is configured to output a second control signal to the first switch 521 and the second switch 522 when there are no more than two clock signals and the clock signals are active level at the same time, and the second control signal is used to control the first switch 521 and the second switch 522 to be turned on.

Illustratively, the second control signal is a high level signal when the thin film transistors used by the first switch 521 and the second switch 522 are NMOS thin film transistors, and the second control signal is a low level signal when the thin film transistors are PMOS thin film transistors.

Further, the analog-to-digital converter 511 in the determination sub-circuit 51 may also be configured to operate only in the power-on stage or when the detected ambient temperature is lower than the temperature threshold, because at the normal operation stage of the liquid crystal display, more than two paths of clock signals CLKT output by the TCON do not occur and are at the active level at the same time, there is no need to perform analog-to-digital conversion of signals at this time, so as to save the power consumption caused by the analog-to-digital converter 511. Here, the boot phase refers to a phase before the TCON Download Reset (Download Reset) is completed, i.e., an initialization phase. In the Download Reset process, the TCON reads program codes required for the TCON to operate from an external memory (Flash), and then loads and operates.

Accordingly, in the normal operation stage, the processing device 512 does not need to process the digital signal, that is, does not need to determine whether more than two bits of the same bit of the multi-path digital signal are 1 (active high) or 0 (active low). At this time, the processing device 512 only needs to control the first switch 521 and the second switch 522 to be in the conducting state all the time, so as to save the electric energy to the maximum extent.

In the embodiment of the present invention, the processing device 512 may be implemented by a circuit or a chip capable of performing logic operation processing of a digital signal and generation of a control signal, such as a processor chip or an integrated circuit.

The embodiment of the invention also provides a driving circuit which comprises the black screen prevention circuit shown in fig. 2 or fig. 3.

The driving circuit provided by the embodiment of the invention has the same technical characteristics as any one of the anti-black screen circuits, so that the same technical problems can be solved, and the same technical effects can be produced.

The embodiment of the invention also provides a display device which comprises the driving circuit.

In the embodiment of the present disclosure, the display device provided in the embodiment of the present disclosure may be any product or component having a display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, and a navigator.

The display device provided by the embodiment of the invention has the same technical characteristics as any one of the driving circuits, so that the same technical problems can be solved, and the same technical effects can be produced.

Fig. 5 is a flowchart of a method for preventing a black screen, which is implemented by using the black screen preventing circuit shown in any one of fig. 2 to fig. 4 and is applied to a driving circuit of a display, according to an embodiment of the present invention, and referring to fig. 5, the method includes:

step 301: and determining whether more than two clock signals are simultaneously in the effective level in the multi-path clock signals output by the TCON.

This step may be implemented by a deterministic sub-circuit 51 in the anti-shadow circuit.

Step 302: and when the fact that more than two clock signals are simultaneously in the effective level is determined, the VGH signal and the VGL signal output by the PMIC to the L/S circuit are cut off.

This step may be implemented by the control sub-circuit 52 in the anti-blank screen circuit.

In the embodiment of the present invention, by determining whether two or more clock signals are simultaneously active levels in the multiple clock signals output by the TCON 30, and cutting off the VGH and VGL signals output by the PMIC10 when two or more clock signals are simultaneously active levels, the L/S circuit cannot output the VGH and VGL to the gate driving circuit, and further the gate driving circuit cannot output the gate-on level to multiple rows of pixel units at the same time when two or more clock signals are simultaneously active levels, so as to drive the multiple rows of pixel units to work at the same time, thereby avoiding triggering overload protection by the PMIC10 and avoiding the black screen phenomenon during startup.

Optionally, determining whether there are more than two clock signals in the multiple clock signals output by the TCON that are active levels at the same time may include:

converting the multi-channel clock signals from analog signals into digital signals;

and determining whether more than two paths of clock signals are simultaneously effective electrical levels according to the digital signals converted from the multiple paths of clock signals.

In the embodiment of the invention, in order to detect whether more than two clock signals are simultaneously at the effective level, the analog signal output by the TCON is converted into the digital signal, after analog-to-digital conversion, the high and low levels of the analog signal are converted into binary values 1 and 0, and whether more than two clock signals are simultaneously at the effective level can be determined by comparing the values of the digital signal.

It should be noted that, since the analog signal is a continuous signal, and the digital signal is a discrete signal, which is obtained by sampling and converting the analog signal, the same clock signal is used for the multiple analog signals during the analog conversion process in order to ensure the synchronism of the multiple digital signals. In this way, the same bit of the converted multi-path digital signal indicates the level of the multi-path clock signal at the same time, and it is only necessary to determine whether two or more bits of the same bit of the multi-path digital signal are 1 (high level valid) or 0 (low level valid).

Optionally, when it is determined that there are two or more clock signals that are active simultaneously, cutting off VGH and VGL signals output by the PMIC to the L/S circuit includes:

outputting a first control signal to the first switch and the second switch, wherein the first control signal is used for controlling the first switch and the second switch to be switched off;

the first switch comprises a VGH input end, an output end and a control end, the second switch comprises a VGL input end, an output end and a control end, the control ends of the first switch and the second switch are used for receiving control signals, and the output end of the first switch and the output end of the second switch are electrically connected with the L/S circuit.

Illustratively, the first switch 521 and the second switch 522 may be Thin Film Transistors (TFTs), such as NMOS Thin Film transistors or PMOS Thin Film transistors. The first control signal here is different according to the type of the thin film transistor, for example, when the thin film transistor is an NMOS thin film transistor, the first control signal is a low level signal, and when the thin film transistor is a PMOS thin film transistor, the first control signal is a high level signal.

Optionally, the method may further include:

and when more than two clock signals are not at the effective level at the same time, controlling the VGH and VGL signals output by the PMIC to be output to the L/S circuit.

Illustratively, when there are no more than two clock signals and the two clock signals are active level at the same time, the control signal is a second control signal for controlling the first switch 521 and the second switch 522 to be turned on.

Further, the foregoing analog-to-digital conversion step may also be configured to operate only in a power-on stage or when it is detected that the ambient temperature is lower than the temperature threshold, because in a normal operation stage of the liquid crystal display, more than two paths of the clock signal CLKT output by the TCON do not occur and are at an active level at the same time, there is no need to perform analog-to-digital conversion of the signal at this time, so as to save power consumption caused by the analog-to-digital converter 511.

Accordingly, in the normal operation stage, it is also not necessary to process the digital signal, i.e., it is not necessary to determine whether more than two bits of the same bit of the multi-path digital signal are 1 (active high) or 0 (active low). At this time, the control signal is always the first control signal, and it is sufficient to control the first switch 521 and the second switch 522 to be in the conducting state, so that the electric energy is saved to the maximum extent.

The above description is only for the purpose of illustrating the preferred embodiments of the present invention and should not be taken as limiting the scope of the present invention, which is intended to cover any modifications, equivalents, improvements, etc. within the spirit and scope of the present invention.

Claims

1. A black screen prevention circuit, which is applied to a driving circuit of a display, the driving circuit comprising an integrated power management circuit (10), a level conversion circuit (20) and a counter control register (30), wherein the level conversion circuit (20) is electrically connected with the integrated power management circuit (10) and the counter control register (30), respectively, and the black screen prevention circuit comprises:

a determination sub-circuit (51) configured to determine whether or not there are more than two clock signals simultaneously at an active level among the plurality of clock signals output from the counter control register (30);

a control sub-circuit (52) configured to cut off the gate high level and gate low level signals output from the integrated power management circuit (10) to the level shift circuit (20) when the determination sub-circuit (51) determines that there are two or more clock signals simultaneously at an active level.

2. The black screen prevention circuit according to claim 1, wherein the determination sub-circuit (51) comprises:

the multi-channel analog-to-digital converters (511) are arranged in one-to-one correspondence with the multi-channel clock signals and are configured to convert the multi-channel clock signals from analog signals to digital signals;

and the processing device (512) is configured to determine whether more than two clock signals are simultaneously in an active level according to the digital signals converted by the multi-path clock signals.

3. The black screen prevention circuit according to claim 1 or 2, wherein the control sub-circuit (52) comprises:

a first switch (521), the first switch (521) comprising a gate high level input terminal, an output terminal and a control terminal; a control terminal of the first switch (521) is electrically connected with an output terminal of the determination sub-circuit (51), and an output terminal of the first switch (521) is electrically connected with the level conversion circuit (20);

a second switch (522), the second switch (522) comprising a gate low input terminal, an output terminal and a control terminal; the control terminal of the second switch (522) is electrically connected with the output terminal of the determining sub-circuit (51), and the output terminal of the second switch (522) is electrically connected with the level converting circuit (20).

4. The black screen prevention circuit according to claim 1 or 2, wherein the control sub-circuit (52) is further configured to control the integrated power management circuit (10) to output a gate high level and a gate low level signal to the level conversion circuit (20) when the determination sub-circuit (51) determines that there are not more than two clock signals simultaneously at an active level.

5. The black screen prevention circuit according to claim 1 or 2, further comprising an impedance matching sub-circuit (53), the impedance matching sub-circuit (53) being electrically connected to the control sub-circuit (52), the determination sub-circuit (51), the integrated power management circuit (10) and the level shifting circuit (20), respectively.

6. A driving circuit characterized by comprising the black-screen prevention circuit as claimed in any one of claims 1 to 5.

7. A display device characterized in that the display device comprises the drive circuit according to claim 6.

8. A black screen prevention method is applied to a driving circuit of a display, the driving circuit comprises an integrated power management circuit, a level conversion circuit and a counter control register, the level conversion circuit is respectively and electrically connected with the integrated power management circuit and the counter control register, and the method comprises the following steps:

determining whether more than two paths of clock signals exist in the multi-path clock signals output by the counter control register and are simultaneously effective levels;

and when the condition that more than two paths of clock signals are simultaneously at effective levels is determined, the grid high level and the grid low level signals output by the integrated power management circuit to the level conversion circuit are cut off.

9. The method of claim 8, wherein the determining whether more than two clock signals are active at the same time in the plurality of clock signals output from the counter control register comprises:

converting the multi-path clock signals from analog signals to digital signals;

10. The method according to claim 8 or 9, wherein said cutting off the gate high level and gate low level signals output from the integrated power management circuit to the level conversion circuit when it is determined that there are more than two clock signals simultaneously active level comprises:

the first switch comprises a grid high level input end, an output end and a control end, the second switch comprises a grid low level input end, an output end and a control end, the control ends of the first switch and the second switch are used for receiving the control signals, and the output end of the first switch and the output end of the second switch are electrically connected with the level conversion circuit.