CN111710274B - Clock signal judging circuit and display panel - Google Patents
Clock signal judging circuit and display panel Download PDFInfo
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- CN111710274B CN111710274B CN202010534474.XA CN202010534474A CN111710274B CN 111710274 B CN111710274 B CN 111710274B CN 202010534474 A CN202010534474 A CN 202010534474A CN 111710274 B CN111710274 B CN 111710274B
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
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- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Liquid Crystal Display Device Control (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
Abstract
The invention provides a clock signal judging circuit and a display panel, wherein the clock signal judging circuit comprises a switch, a voltage converting circuit, a latch and a switch control circuit, wherein the switch control circuit is connected with the switch and is connected with a plurality of clock signals, and the switch control circuit outputs low level when the clock signals are continuously transmitted, and the switch is disconnected at the moment; when the continuous transmission is finished, the switch control circuit outputs high level, and the switch is closed at the moment. That is, when any clock signal is at high level, the LC does not turn over, and when all clock signals are at low level, the switch is closed, and then the LC input signal condition at this time is detected.
Description
Technical Field
The invention relates to the technical field of display, in particular to a clock signal judging circuit and a display panel.
Background
In general, in a GOA circuit, an inversion signal (LC signal) is controlled to be a voltage signal of Q point (gate) and GN (output of the GOA circuit of this stage) in the pull-down GOA circuit, and during use, the LC signal is divided into two signals LC1/LC2, which are in opposite states, i.e., one is at a high level and one is at a low level. This signal is controlled by LC Input output by TCON (array substrate chip), where the signal of LC1 is the same as LC Input and the signal of LC2 is the opposite of LC Input.
In the actual use process, if the LC is interfered or the TCON timing sequence is abnormal, LC signal switching will be caused in the display area, that is, CK (clock signal) will still occur under the condition of continuous transmission, at this time, the pull-down circuit of the in-plane GOA line will be caused to switch in the display stage, which will affect continuous transmission and turn-off of Gate (Gate), and cause panel flicker or different pictures.
Therefore, it is highly desirable to provide a new clock signal judgment circuit, which can solve the problem that in the prior art, abnormal overturn occurs in the LC signal during CK continuous transmission.
Disclosure of Invention
In order to solve the problems, the invention provides a clock signal judging circuit which comprises a switch, a latch, a first switch and a second switch, wherein one end of the switch is connected with an LC input signal, and the other end of the switch is connected with the latch; one end of the voltage conversion circuit is connected with the latch, and the other end of the voltage conversion circuit outputs a first signal and a second signal; the switch control circuit is connected with the switch and is connected with a plurality of clock signals; the switch control circuit outputs a low level when the clock signals are continuously transmitted, and the switch is disconnected at the moment; when the continuous transmission is finished, the switch control circuit outputs high level, and the switch is closed at the moment.
Further, the latch includes a determiner; when the switch is disconnected, the latch outputs the state of the display picture of the previous frame, and the time sequence is not switched; when the switch is closed, judging whether the LC input signal is abnormal or not by the judging device, and confirming the output states of the first signal and the second signal.
Further, the switch control circuit includes a nand gate.
Further, the LC input signal is provided by an array substrate driving chip.
Further, the first signal is the same as the LC input signal; the second signal is opposite to the LC input signal.
Further, the second signal is the same as the LC input signal; the first signal is opposite to the LC input signal.
Further, the first signal and the second signal are respectively connected to a GOA circuit.
The invention also provides a display panel which comprises a driving chip, wherein the driving chip is integrated with the clock signal judging circuit.
Further, the display panel further includes: the array substrate comprises an array substrate driving chip, and the array substrate driving chip generates LC input signals and provides the LC input signals for the clock signal judging circuit.
Further, the display panel further includes: and the GOA circuit is connected with the clock signal judging circuit.
The beneficial effects of the invention are as follows: the invention provides a clock signal judging circuit and a display panel, wherein a switch control circuit is arranged, the switch control circuit is connected with a switch and is connected with a plurality of clock signals, and the switch control circuit outputs a low level when the clock signals are transmitted continuously, so that the switch is disconnected; when the continuous transmission is finished, the switch control circuit outputs high level, and the switch is closed at the moment. That is, when any clock signal is at high level, the LC does not turn over, and when all clock signals are at low level, the switch is closed, and then the LC input signal condition at this time is detected.
Drawings
The invention is further described below with reference to the drawings and examples.
Fig. 1 is a functional block diagram of a clock signal judging circuit according to the present invention.
A clock signal judgment circuit 100;
a switch 101; a voltage conversion circuit 104; a latch 103;
a switch control circuit 102.
Detailed Description
The invention will be further illustrated by the following specific examples for a better understanding of the content of the invention, but the practice and the scope of the invention are not limited thereto.
The following description of the embodiments refers to the accompanying drawings, which illustrate specific embodiments in which the invention may be practiced. The directional terms referred to in the present invention are, for example, "up", "down", "front", "rear
Left, right, top, bottom, etc., are merely references to the directions of the attached drawings. Accordingly, directional terminology is used to describe and understand the invention and is not limiting of the invention.
As shown in fig. 1, the present invention provides a clock signal judging circuit 100, which includes a switch 101, a voltage converting circuit 104, a latch 103, and a switch control circuit 102.
One end of the switch 101 is connected to an LC Input signal (LC Input), and the other end is connected to the latch 103. The LC input signal is provided by the array substrate driving chip.
The LC input signal is a low frequency inversion signal, which is used to pull down the voltages of the components, and needs to be used alternately to prevent the occurrence of anomalies.
The voltage conversion circuit 104 has one end connected to the latch 103, and the other end outputting a first signal (LC out 1) and a second signal (LC out 2).
In an embodiment, the first signal is the same as the LC input signal; the second signal is opposite to the LC input signal.
The first signal and the second signal are respectively connected to a GOA circuit.
In another embodiment, the second signal is the same as the LC input signal; the first signal is opposite to the LC input signal.
The switch control circuit 102 is connected to the switch 101 and receives a plurality of clock signals (CK 1 to CK 6). The switch control circuit 102 includes a nand gate.
Wherein, during continuous transmission of the clock signals, the switch control circuit 102 outputs a low level, and the switch 101 is turned off; when the transfer is completed, the switch control circuit 102 outputs a high level, and the switch 101 is closed.
Further, the latch 103 includes a arbiter. When the switch 101 is turned off, the latch 103 outputs the state of the display screen of the previous frame, and the timing is not switched; when the switch 101 is closed, whether the LC input signal is abnormal is judged by the judging unit, and the output states of the first signal and the second signal are confirmed. When the LC input signal is prevented from being interfered, the CK signal is still in the condition of continuous transmission, and at the moment, a pull-down circuit of a GOA line in the panel can be switched in a display stage, so that the continuous transmission and the turn-off of a grid are influenced, and the problems of flickering or heterodrawing are caused.
The invention provides a clock signal judging circuit 100, by setting a switch control circuit 102, the switch control circuit 102 is connected with the switch 101 and is accessed with a plurality of clock signals, the switch control circuit 102 outputs a low level when the clock signals are transmitted continuously, and the switch 101 is disconnected at the moment; when the transfer is completed, the switch control circuit 102 outputs a high level, and the switch 101 is closed. That is, when any clock signal is at a high level, LC does not flip, and when all clock signals are at a low level, switch 101 is closed, and then the LC input signal condition at that time is detected.
The invention provides a display panel, which comprises a driving chip, wherein the driving chip is integrated with the clock signal judging circuit 100.
The display panel further includes: an array substrate and a GOA circuit.
An array substrate including an array substrate driving chip that generates LC input signals and supplies the LC input signals to the clock signal judging circuit 100.
The GOA circuit is connected to the clock signal judgment circuit 100.
The clock signal judging circuit 100 includes a switch 101, a voltage converting circuit 104, a latch 103, and a switch control circuit 102.
One end of the switch 101 is connected with an LC input signal, and the other end is connected with the latch 103. The LC input signal is provided by the array substrate driving chip.
The LC input signal is a low frequency inversion signal, which is used to pull down the voltages of the components, and needs to be used alternately to prevent the occurrence of anomalies.
One end of the voltage conversion circuit 104 is connected to the latch 103, and the other end outputs a first signal and a second signal.
In an embodiment, the first signal is the same as the LC input signal; the second signal is opposite to the LC input signal.
The first signal and the second signal are respectively connected to a GOA circuit.
In another embodiment, the second signal is the same as the LC input signal; the first signal is opposite to the LC input signal.
The switch control circuit 102 is connected to the switch 101 and receives a plurality of clock signals (CK 1 to CK 6). The switch control circuit 102 includes a nand gate.
Wherein, during continuous transmission of the clock signals, the switch control circuit 102 outputs a low level, and the switch 101 is turned off; when the transfer is completed, the switch control circuit 102 outputs a high level, and the switch 101 is closed.
Further, the latch 103 includes a arbiter. When the switch 101 is turned off, the latch 103 outputs the state of the display screen of the previous frame, and the timing is not switched; when the switch 101 is closed, whether the LC input signal is abnormal is judged by the judging unit, and the output states of the first signal and the second signal are confirmed. When the LC input signal is prevented from being interfered, the CK signal is still in the condition of continuous transmission, and at the moment, a pull-down circuit of a GOA line in the panel can be switched in a display stage, so that the continuous transmission and the turn-off of a grid are influenced, and the problems of flickering or heterodrawing are caused.
It should be noted that numerous variations and modifications are possible in light of the fully described invention, and are not limited to the specific examples of implementation described above. The above-described embodiments are merely illustrative of the present invention and are not intended to be limiting. In general, the scope of the present invention should include those variations or alternatives and modifications apparent to those skilled in the art.
Claims (10)
1. A clock signal judgment circuit, comprising:
one end of the switch is connected with the LC input signal, and the other end of the switch is connected with the latch;
one end of the voltage conversion circuit is connected with the latch, and the other end of the voltage conversion circuit outputs a first signal and a second signal; and
the switch control circuit is connected with the switch and is connected with a plurality of clock signals;
the switch control circuit outputs a low level when the plurality of clock signals are continuously transmitted, the switch is turned off, the latch does not receive the LC input signal, and the first signal and the second signal do not switch time sequences; when the continuous transmission is finished, the switch control circuit outputs high level, at the moment, the switch is closed, and the LC input signal is detected to confirm the output states of the first signal and the second signal.
2. The clock signal judgment circuit according to claim 1, wherein,
the latch includes a determiner;
when the switch is disconnected, the latch outputs the state of the display picture of the previous frame, and the time sequence is not switched; when the switch is closed, judging whether the LC input signal is abnormal or not by the judging device, and confirming the output states of the first signal and the second signal.
3. The clock signal judgment circuit according to claim 1, wherein,
the switch control circuit includes a NAND gate circuit.
4. The clock signal judgment circuit according to claim 1, wherein,
the LC input signal is provided by the array substrate driving chip.
5. The clock signal judgment circuit according to claim 1, wherein,
the first signal is the same as the LC input signal;
the second signal is opposite to the LC input signal.
6. The clock signal judgment circuit according to claim 1, wherein,
the second signal is the same as the LC input signal;
the first signal is opposite to the LC input signal.
7. The clock signal judgment circuit according to claim 1, wherein,
the first signal and the second signal are respectively connected to a GOA circuit.
8. A display panel comprising a driver chip having the clock signal judging circuit of any one of claims 1 to 7 integrated thereon.
9. The display panel of claim 8, further comprising:
the array substrate comprises an array substrate driving chip, and the array substrate driving chip generates LC input signals and provides the LC input signals for the clock signal judging circuit.
10. The display panel of claim 8, further comprising:
and the GOA circuit is connected with the clock signal judging circuit.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010534474.XA CN111710274B (en) | 2020-06-12 | 2020-06-12 | Clock signal judging circuit and display panel |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202010534474.XA CN111710274B (en) | 2020-06-12 | 2020-06-12 | Clock signal judging circuit and display panel |
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| CN111710274A CN111710274A (en) | 2020-09-25 |
| CN111710274B true CN111710274B (en) | 2023-06-27 |
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2020
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| CN111710274A (en) | 2020-09-25 |
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