CN101853643A - Control system and method of liquid crystal display - Google Patents
Control system and method of liquid crystal display Download PDFInfo
- Publication number
- CN101853643A CN101853643A CN201010199003A CN201010199003A CN101853643A CN 101853643 A CN101853643 A CN 101853643A CN 201010199003 A CN201010199003 A CN 201010199003A CN 201010199003 A CN201010199003 A CN 201010199003A CN 101853643 A CN101853643 A CN 101853643A
- Authority
- CN
- China
- Prior art keywords
- clock signal
- pulse
- signal
- lcd
- time
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Abstract
The invention relates to a control system of a liquid crystal display, which is used in the liquid crystal display, and comprises a timing controller, a level shifter and an array substrate column driver, wherein the timing controller is connected with the liquid crystal display and is used for outputting first clock signals and pulse signals, receiving feedback signals of pixels, and judging whether second clock signals are output or not according to the feedback signals, and the level shifter is connected with the timing controller and providing the liquid crystal display with charging signals according to the first clock signals and the second clock signals respectively; and the array substrate column driver is connected with the liquid crystal display and the level shifter, and is used for transmitting driving signals according to the charging signals respectively to control the charging of the pixels of the liquid crystal display. The invention also provides a control method of the liquid crystal display, which can solve the problems of charging error of the pixels caused by signal transmission delay in the liquid crystal display.
Description
Technical field
The present invention relates to a kind of LCD, and be particularly related to a kind of control system of LCD.
Background technology
At present, LCD manufacturer begins to develop the capable driving of array base palte (Gate Driver on Array in order to reduce the manufacturing cost of LCD; GOA) technology promptly directly is produced on gate driver circuit (Gate driverICs) on array (Array) substrate, to replace the chip for driving by external silicon wafer to manufacture.This The Application of Technology can reduce the production technology program, reduces product technology cost, improves the integrated level of display panels.
Yet, in the GOA technology, transfer to the clock drive signal of LCD device grid line, through each grade shift register the time, the capital is subjected to the influence of stray capacitance, and cause the delay of clock drive signal on bus thus, and and cause the progressively distortion of described signal waveform, especially on away from the grid impulse of GOA, produce the most serious distortion phenomenon.As shown in Figure 1, transfer to signal, compare the signal that transfers to nearer pixel 1, the distortion of its waveform from GOA pixel 2 farthest.When the width of clock signal is pulled longly, this makes that just the pixel charging of LCD is uneven, perhaps produces the problem of bright concealed wire because of the mistake of charging.As shown in Figure 2, when time value is pulled when long, then fill to pixel 2 for the charging voltage of pixel 1 easily; Also promptly, the clock signal that should arrive pixel 1 can arrive in the data line S1 of reverse, causes pixel 1 forfeiture brightness.Thus, will make the brightness of LCD become inhomogeneous.And when GOA was aging, described delay phenomenon can be more serious, and the life-span of LCD then shortens greatly.
Therefore, how to improve the pulse width traction phenomena of above-mentioned clock signal, thereby avoid described pixel charging mistake, just become problem demanding prompt solution.
Summary of the invention
In view of this, be necessary to provide a kind of control method of LCD, can improve described time value traction phenomena, and solve the wrong problem of pixel charging.
According to one embodiment of present invention, provide a kind of control system of LCD, having comprised: time schedule controller (Timing Controller; TCON), the capable driving of level shifter and array base palte (GateDriver on Array; GOA).Time schedule controller is connected with described LCD, be used to export first clock signal and a pulse signal, and receive a feedback signal of a pixel of described LCD, and judge whether to export the second clock signal according to described feedback signal, at least comprise: timing module, first clock signal and the described pulse signal that are used for sending according to described time schedule controller are preset a time value, and calculate the back coupling time value of described liquid crystal display pixel point feedback signal; And comparison module, be connected with described timing module, whether the back coupling time value that is used for more described pixel feedback signal greater than described Preset Time value, and when the back coupling time value of the feedback signal of described pixel during greater than described Preset Time value, output second clock signal.Level shifter is connected with described time schedule controller, is used for providing charging signals according to described first clock signal and second clock signal to described LCD respectively.The capable driving of array base palte connects described LCD and described level shifter, is used for respectively according to described charging signals transmission drive signal, with the charging of the described pixel of controlling described LCD.
According to one embodiment of present invention, provide a kind of control method of LCD, may further comprise the steps: exported first clock signal and a pulse signal, be used to control charging a pixel of described LCD; Set a Preset Time value according to described first clock signal and described pulse signal; Receive a feedback signal of described pixel and calculate the back coupling time value of described feedback signal; Whether the back coupling time value of more described feedback signal is greater than described Preset Time value; And when the back coupling time value of described feedback signal whether during, output second clock signal greater than described Preset Time value.
By LCD control method shown in the present, can effectively solve the clock signal latency issue, and avoid the wrong problem of data line charging, and the serviceable life of improving LCD thus.
Description of drawings
For above-mentioned purpose of the present invention and further feature, advantage and embodiment can be become apparent, being described in detail as follows of appended accompanying drawing:
Fig. 1 is in the available liquid crystal display, the oscillogram of different pixels point signal;
Fig. 2 is in the available liquid crystal display, because of signal delay causes charge wrong signal and oscillogram thereof;
Fig. 3 a and Fig. 3 b are the LCD control system applied environment synoptic diagram and the block diagrams of one embodiment of the invention;
Fig. 4 is the waveform of each signal in the system shown in Fig. 3 a and the 3b; And
Fig. 5 is the LCD control method process flow diagram of further embodiment of this invention.
[primary clustering symbol description]
30: LCD CK1: first clock signal
32: time schedule controller CK2: the second clock signal
320: computing module XSTB: pulse signal
322: timing module
324: comparison module
34: level shifter
36: the capable driving of array base palte
Gate?Driver?on?Array；GOA
500～504: step
Embodiment
Fig. 3 a and 3b are the LCD control method applied environment synoptic diagram of one embodiment of the invention.Wherein, time schedule controller 32 is connected with level shifter 34, and level shifter 34 drives (Gate Driver on Array with the array basal plate row; GOA) 36 connect, and GOA 36 is connected with LCD 30, and LCD 30 also connects described time schedule controller 32.
In the present embodiment, time schedule controller 32 is used to export first clock signal and a pulse signal, and receives the feedback signal of a pixel B of described LCD, and judges whether to export the second clock signal according to described feedback signal.In the present embodiment, time schedule controller 32 is used for producing and transmits extremely described level shifter 34 of first clock signal and pulse signal.Level shifter 34 is connected with described time schedule controller 32, is used for providing charging signals according to described first clock signal and second clock signal to the pixel B of described LCD 30 respectively.GOA 36 connects described LCD 30 and described level shifter 34, is used for respectively according to described charging signals transmission drive signal, with the charging of the pixel B that controls described LCD 30.LCD 30 is connected with described GOA 36 and described time schedule controller 32, is used for lighting pixel B according to described drive signal, and the signal of described pixel B is feedback to described time schedule controller 32.
Please consult Fig. 3 b simultaneously, be depicted as the module block diagram of Fig. 3 a.Wherein, time schedule controller 32 also comprises a timing module 322, connect described computing module 320, first clock signal and the described pulse signal that are used for sending according to described time schedule controller 32 are preset a time value, and calculate the back coupling time value of described LCD 30 pixel B feedback signals.
Normally, the waveform of first clock signal and pulse signal is square wave, have corresponding rise time and pulse fall time respectively, in the present embodiment, be the Preset Time value with the pulsewidth distance definition between the rise time of second pulse of pulse fall time of first pulse of described first clock signal and described pulse signal.When described time schedule controller 32 produced and transmits first clock signal and pulse signal, the Preset Time value should be fixed value.In the present embodiment, setting the Preset Time value is 3.5 microseconds (us).In other embodiments, described Preset Time value can be provided with according to the concrete specification of above-mentioned LCD 30 and described GOA 36.Do not repeat them here.
In the present embodiment, time schedule controller 32 also comprises a computing module 320, connects described LCD 30, is used to receive the signal that LCD 30 pixel B feedback, and carry out computing, thereby export a magnitude of voltage according to the feedback signal of described pixel B.In the present embodiment, the magnitude of voltage of described computing module 320 outputs comprises a high-voltage value and a low voltage value.Wherein, described timing module 322 connects described computing module 320, and determines whether to stop timing according to the magnitude of voltage of described computing module 320 outputs.In the present embodiment, when described computing module 320 output HIGH voltages, described timing module 322 continues timing; When described computing module 320 output LOW voltages, described timing module 322 stops timing.
In the present embodiment, after described time schedule controller 32 output first clock signal C K1 and pulse signal, described timing module 322 picked up counting in the pulse fall time of the first clock signal C K1.
GOA 36 is connected with described level shifter 34, is used for respectively according to described charging signals transmission drive signal, with the charging of the pixel B that controls described LCD 30.When the drive signal of sending as GOA 36 did not postpone in transmission, the drive signal that transfers to the pixel B of LCD 30 then can distortion.In the present embodiment, the drive signal of sending as GOA 36 has delay in actual transmissions, causes transferring to the drive signal distortion of pixel B.In the present embodiment, when the drive signal distortion of pixel B, described GOA 36 also is used to receive the second clock signal that described level shifter 34 is transmitted, and exports second drive signal according to described second clock signal.The principle of work of GOA 36 transmission drive signals for the common technology in this area, will not be discussed at this.
See also Fig. 4, be depicted as the waveform synoptic diagram of the LCD control system output signal shown in Fig. 3 a and the 3b.From Fig. 4 as seen, the first clock signal C K1 of time schedule controller 32 outputs is a square wave, and its pulse has a rise time and a fall time, the distance between this rise time and fall time, that is the pulse width of the described first clock signal C K1 is PW1.The pulse signal XSTB of time schedule controller 32 outputs also is a square wave, and it also has a rise time and a decline time.In the present embodiment, be Preset Time value T with the pulsewidth distance definition between the rise time of second pulse of fall time of first pulse of the described first clock signal C K1 and described pulse signal XSTB
1, its value is 3.5us.And behind the described time schedule controller 32 outputs first clock signal C K1, pick up counting in the pulse fall time of the first clock signal C K1.
When the feedback signal of pixel B transferred to computing module 320,320 pairs of these feedback signals of computing module were carried out computing, and export a magnitude of voltage according to operation result.In the present embodiment, this magnitude of voltage comprises a high-voltage value and a low voltage value.When computing module 320 output HIGH voltage values, timing module 322 continues timing; When computing module 320 output LOW voltage values, timing module 322 stops timing.In the present embodiment,, obtain timing time value TB, also be the back coupling time value of the feedback signal of described pixel B when timing module 322 stops timing.
See also Fig. 4, when timing module 322 stops timing, that is as described timing time value T
BDuring for 4us, 324 of comparison modules are judged described timing time value T
BGreater than described Preset Time value T1.This kind situation, relative first clock signal of expression charging signals produces and postpones, and this will cause the charging of pixel B is made a mistake.Therefore, comparison module 324 output second clock signal CK2 are to described level shifter 34, and in the present embodiment, described second clock signal CK2 also is a square wave, and pulse width is PW2.As seen from Figure 4, PW1 is greater than PW2, that is the relative first clock signal C K1 of the waveform of described second clock signal CK2, and the pulse rise time of second clock signal CK2 is constant, and has shifted to an earlier date a value pulse fall time.In the present embodiment, second clock signal CK2 has shifted to an earlier date 0.6us decline than the first clock signal C K1, in other embodiments, should time value in advance can be set by software, circuit or programmable logic device (PLD) according to concrete situation.
Thus, as can be seen from Figure 4, from second feedback signal that pixel B is feedback, be consistent the pulse fall time of its pulse fall time and second clock signal CK2.Pulsewidth distance between the pulse fall time of described second clock signal CK2 and the rise time of described pulse signal is 3.5us+0.6us=41.us, greater than described back coupling time value 4.0us.Thereby prevent the phenomenon that the charging signals mistake is filled.
See also Fig. 5, be depicted as in further embodiment of this invention, LCD control method process flow diagram.In the present embodiment, in step 500, by time schedule controller 32 output first clock signal C K1 and pulse signal XSTB, so that a level shifter 34 and array basal plate row drive (Gate Driveron Array; GOA) 36 are convenient to control pixel B charging to a LCD 30 according to the described first clock signal C K1 and pulse signal XSTB.In the present embodiment, the described first clock signal C K1 is a square wave, and each pulse has a rise time and a pulse fall time, the distance between this rise time and fall time, that is the pulsewidth of the described first clock signal C K1 is PW1.
In step 502, time schedule controller 32 is set a Preset Time value according to described first clock signal C K1 and pulse signal XSTB.In the present embodiment, described pulse signal XSTB also is a square wave, and its each pulse has a rise time and a pulse fall time.In the present embodiment, be Preset Time value T with the pulsewidth distance definition between the rise time of second pulse of fall time of first pulse of the described first clock signal C K1 and described pulse signal XSTB
1In the present embodiment, the T1 value is 3.5 milliseconds (us), and in other embodiments, described Preset Time value can be set according to practical situation.
In step 504, time schedule controller 32 picked up counting from the pulse fall time of the first clock signal C K1, in the present embodiment, time schedule controller 32 also comprises a timing module 322, is used to calculate back coupling time of feedback signal of a pixel B of described LCD.And in step 506; Time schedule controller 32 receives the feedback signal of transmission from described liquid crystal display pixel point B.In the present embodiment, the feedback signal of pixel B causes waveform distortion because of the delay of signal transmission, and its waveform sees also Fig. 4, does not repeat them here.
In step 508, time schedule controller 32 judges whether to stop timing.Sequence controller 32 also comprises a computing module 320, connects described LCD 30, is used to receive the signal that LCD 30 pixel B feedback, and carries out computing according to the feedback signal of described pixel B, thereby export a magnitude of voltage.In the present embodiment, the magnitude of voltage of described computing module 320 outputs comprises a high-voltage value and a low voltage value.Wherein, described timing module 322 connects described computing module 320, and determines whether to stop timing according to the magnitude of voltage of described computing module 320 outputs.In the present embodiment, when described computing module 320 output HIGH voltages, described timing module 322 continues timing; When described computing module 320 output LOW voltages, described timing module 322 stops timing.In the present embodiment, when described magnitude of voltage is high voltage, then return step 504, continue timing; When described magnitude of voltage was low-voltage, then in step 510,322 of the timers of described time schedule controller 32 stopped timing, and calculated the back coupling time T of the feedback signal of described pixel B
B
In step 512, the back coupling time value of time schedule controller 32 more described feedback signals and Preset Time value size.When feedback signal time value during greater than the Preset Time value, in step 514, described time schedule controller 32 output second clock signal CK2, the waveform of described first clock signal C K1 and second clock signal CK2 is square wave, and the pulse rise time of described second clock signal CK2 is identical with the pulse rise time of the described first clock signal C K1; The pulse fall time of described second clock signal CK2 is than the pulse fall time of the described first clock signal C K1 of a value in advance.
Thus,, can effectively improve the pulse width traction phenomena of signal, thereby avoid described pixel charging mistake in LCD by the control system and the control method of above-mentioned LCD.
Though content of the present invention discloses as above with embodiment; right its is not in order to limit content of the present invention; any those skilled in the art; in the spirit and scope that do not break away from content of the present invention; when can doing various changes and modification, so the protection domain of content of the present invention should be as the criterion with the scope that claim was defined.
Claims (10)
1. a LCD control system is used for LCD, it is characterized in that, described LCD control system comprises:
Time schedule controller is connected with described LCD, is used to export first clock signal and a pulse signal, and receives a feedback signal of described pixel, and judges whether to export the second clock signal according to described feedback signal, comprises at least:
Timing module, first clock signal and the described pulse signal that are used for sending according to described time schedule controller are preset a time value, and calculate the back coupling time value of described liquid crystal display pixel point feedback signal; And
Comparison module, be connected with described timing module, whether the back coupling time value that is used for more described pixel feedback signal greater than described Preset Time value, and when the back coupling time value of the feedback signal of described pixel during greater than described Preset Time value, output second clock signal; And
Level shifter is connected with described time schedule controller, is used for providing charging signals according to described first clock signal and second clock signal to described LCD respectively; And
The capable driving of array base palte connects described LCD and described level shifter, is used for respectively according to described charging signals transmission drive signal, with the charging of the described pixel of controlling described LCD.
2. LCD control system according to claim 1, it is characterized in that, the waveform of described first clock signal and described pulse signal is square wave, and described Preset Time value is the distance value between rise time of second pulse of pulse fall time of first pulse of described first clock signal and described pulse signal.
3. LCD control system according to claim 2, it is characterized in that, described time schedule controller also comprises a computing module, is used to receive the feedback signal of the described pixel of described LCD, and exports a magnitude of voltage according to the feedback signal of described pixel; The magnitude of voltage of described computing module output comprises a high-voltage value and a low voltage value.
4. LCD control system according to claim 3, it is characterized in that, described timing module more connects described computing module, be used for picking up counting from the pulse fall time of first clock signal, magnitude of voltage according to the output of described computing module judges whether to stop timing, and stops timing when described computing module output LOW voltage value.
5. LCD control system according to claim 1, it is characterized in that, the waveform of described first clock signal and second clock signal is square wave, and the pulse rise time of described second clock signal is identical with the pulse rise time of described first clock signal; The pulse fall time of described second clock signal is than the pulse fall time of described first clock signal of a value in advance.
6. a LCD control method is applied in the LCD, is used to control the pixel charging to described LCD, it is characterized in that the control method of described LCD comprises:
Export first clock signal and a pulse signal, be used to control charging a pixel of described LCD;
Set a Preset Time value according to described first clock signal and described pulse signal;
Receive a feedback signal of described pixel and calculate the back coupling time value of described feedback signal;
Whether the back coupling time value of more described feedback signal is greater than described Preset Time value; And
When the back coupling time value of described feedback signal whether during greater than described Preset Time value, output second clock signal.
7. LCD control method according to claim 6, it is characterized in that, the waveform of described first clock signal and described pulse signal is square wave, and described Preset Time value is the distance between rise time of second pulse of pulse fall time of first pulse of described first clock signal and described pulse signal.
8. LCD control method according to claim 7 is characterized in that, also comprises from the pulse fall time of first clock signal picking up counting.
9. LCD control method according to claim 8 is characterized in that, also comprises according to the feedback signal that is received and calculating, and export a magnitude of voltage according to result of calculation; Described magnitude of voltage comprises a high-voltage value and a low voltage value, when described magnitude of voltage is low voltage value, stops timing.
10. LCD control method according to claim 9, it is characterized in that, the waveform of described first clock signal and second clock signal is square wave, and the pulse rise time of described second clock signal is identical with the pulse rise time of described first clock signal; The pulse fall time of described second clock signal is than the pulse fall time of described first clock signal of a value in advance.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201010199003A CN101853643A (en) | 2010-06-04 | 2010-06-04 | Control system and method of liquid crystal display |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201010199003A CN101853643A (en) | 2010-06-04 | 2010-06-04 | Control system and method of liquid crystal display |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN101853643A true CN101853643A (en) | 2010-10-06 |
Family
ID=42805102
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201010199003A Pending CN101853643A (en) | 2010-06-04 | 2010-06-04 | Control system and method of liquid crystal display |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN101853643A (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102622953A (en) * | 2011-02-01 | 2012-08-01 | 联阳半导体股份有限公司 | Driving device of display |
| CN103531169A (en) * | 2013-10-30 | 2014-01-22 | 京东方科技集团股份有限公司 | Display drive circuit, drive method thereof as well as display device |
| WO2015192478A1 (en) * | 2014-06-18 | 2015-12-23 | 京东方科技集团股份有限公司 | Gate driving circuit, array substrate, display device, and driving method |
| CN106228944A (en) * | 2016-10-12 | 2016-12-14 | 深圳市华星光电技术有限公司 | Level shift circuit and display panels |
| CN108986757A (en) * | 2018-07-17 | 2018-12-11 | 深圳市华星光电技术有限公司 | The driving method of GOA circuit and the driving device of GOA circuit |
| WO2019080304A1 (en) * | 2017-10-25 | 2019-05-02 | 深圳市华星光电半导体显示技术有限公司 | Goa circuit |
-
2010
- 2010-06-04 CN CN201010199003A patent/CN101853643A/en active Pending
Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102622953A (en) * | 2011-02-01 | 2012-08-01 | 联阳半导体股份有限公司 | Driving device of display |
| CN103531169A (en) * | 2013-10-30 | 2014-01-22 | 京东方科技集团股份有限公司 | Display drive circuit, drive method thereof as well as display device |
| WO2015192478A1 (en) * | 2014-06-18 | 2015-12-23 | 京东方科技集团股份有限公司 | Gate driving circuit, array substrate, display device, and driving method |
| US9519377B2 (en) | 2014-06-18 | 2016-12-13 | Boe Technology Group Co., Ltd. | Gate driving circuit, array substrate, display device and driving method |
| CN106228944A (en) * | 2016-10-12 | 2016-12-14 | 深圳市华星光电技术有限公司 | Level shift circuit and display panels |
| CN106228944B (en) * | 2016-10-12 | 2019-02-01 | 深圳市华星光电技术有限公司 | Level shift circuit and liquid crystal display panel |
| WO2019080304A1 (en) * | 2017-10-25 | 2019-05-02 | 深圳市华星光电半导体显示技术有限公司 | Goa circuit |
| CN108986757A (en) * | 2018-07-17 | 2018-12-11 | 深圳市华星光电技术有限公司 | The driving method of GOA circuit and the driving device of GOA circuit |
| CN108986757B (en) * | 2018-07-17 | 2019-12-24 | 深圳市华星光电技术有限公司 | GOA circuit driving method and GOA circuit driving device |
| WO2020015179A1 (en) * | 2018-07-17 | 2020-01-23 | 深圳市华星光电技术有限公司 | Driving method for goa circuit and driving device for goa circuit |
| US11011128B1 (en) | 2018-07-17 | 2021-05-18 | Shenzhen China Star Optoelectronics Technology Co., Ltd. | GOA circuit driving method and driving device |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN101853643A (en) | Control system and method of liquid crystal display | |
| CN105390116B (en) | Gate driving circuit | |
| KR101817027B1 (en) | Goa circuit for liquid crystal display and display device | |
| CN103703507B (en) | Liquid crystal indicator and driving method thereof | |
| CN101644867B (en) | Driving device of gate line of liquid crystal display | |
| EP3511925B1 (en) | Flat display device and scanning drive circuit thereof | |
| CN103531169B (en) | A kind of display driver circuit and driving method, display device | |
| CN103985361B (en) | Gate driver circuit and control method thereof and liquid crystal display | |
| WO2017024627A1 (en) | Liquid crystal display drive system and drive method | |
| CN102968970A (en) | Driving device and driving method for display panel | |
| US20210407449A1 (en) | Liquid crystal display panel and driving method thereof | |
| CN104464667A (en) | GOA type display panel and driving circuit structure and driving method of GOA type display panel | |
| CN103971642A (en) | Led display screen driving method and led power supply control circuit | |
| CN105374337A (en) | Liquid crystal display device and operation method thereof | |
| CN108877634A (en) | Isochronous controller, display device and its control method | |
| CN102890923A (en) | Scanning drive circuit of liquid crystal panel, liquid crystal display device and driving method | |
| CN105679225A (en) | Method of driving display panel and display apparatus for performing same | |
| CN103345897A (en) | Active matrix display device, scanning drive circuit and scanning drive method thereof | |
| CN105976778A (en) | Data driving system of liquid crystal display panel | |
| CN102760410B (en) | Scanning driving device and driving signal generating method thereof | |
| WO2021082756A1 (en) | Electronic substrate and driving method therefor, and display apparatus | |
| CN102376254A (en) | Gate line driving device and restoration method thereof | |
| CN102237061A (en) | Angle cutting system of display and timing sequence angle cutting control method thereof | |
| CN106710544A (en) | Shift register circuit, gate drive circuit and display device | |
| US20130009917A1 (en) | Source Driver Array and Driving Method, Timing Controller and Timing Controlling Method, and LCD Driving Device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C02 | Deemed withdrawal of patent application after publication (patent law 2001) | ||
| WD01 | Invention patent application deemed withdrawn after publication |
Application publication date: 20101006 |