CN111157879B - Layer deviation detection method and layer deviation detection structure of printed circuit board - Google Patents
Layer deviation detection method and layer deviation detection structure of printed circuit board Download PDFInfo
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- CN111157879B CN111157879B CN202010006126.5A CN202010006126A CN111157879B CN 111157879 B CN111157879 B CN 111157879B CN 202010006126 A CN202010006126 A CN 202010006126A CN 111157879 B CN111157879 B CN 111157879B
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2801—Testing of printed circuits, backplanes, motherboards, hybrid circuits or carriers for multichip packages [MCP]
- G01R31/2806—Apparatus therefor, e.g. test stations, drivers, analysers, conveyors
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2801—Testing of printed circuits, backplanes, motherboards, hybrid circuits or carriers for multichip packages [MCP]
- G01R31/281—Specific types of tests or tests for a specific type of fault, e.g. thermal mapping, shorts testing
- G01R31/2813—Checking the presence, location, orientation or value, e.g. resistance, of components or conductors
Abstract
The application provides a layer deviation detection method and a layer deviation detection structure of a printed circuit board, a layer of conducting strip is respectively arranged between every two layers of daughter boards, a first through hole and a second through hole are arranged on the conducting strip, a first metalized hole with the radius equal to that of the first through hole and a second metalized hole with the radius smaller than that of the second through hole are arranged on each layer of daughter board, then a test needle of a test device is in conductive connection with a metal layer of the first metalized hole of the outermost layer daughter board, another test needle is in conductive connection with the metal layer of the second metalized hole of the outermost layer daughter board, and finally whether a circuit between the two test needles is conducted or not is judged, so that whether the layer deviation of the printed circuit board meets the requirements of customers can be conveniently and effectively detected.
Description
Technical Field
The application belongs to the technical field of printed circuit boards, and particularly relates to a layer deviation detection method and a layer deviation detection structure of a printed circuit board.
Background
At present, because a multilayer structure PCB (printed circuit board) is formed by combining a plurality of core plates and prepregs (preprags) at high temperature and high pressure during lamination, layer deviation can be generated after lamination, and the on-off of the finished PCB can only be detected by electrical measurement, but the electrical measurement cannot quantitatively detect the layer deviation. Some products in the market have high requirements on signal transmission, so the requirements on the layer deviation control degree of a PCB (printed circuit board) are very high, and the PCB needs to be controlled within a certain range.
Content of application
The application aims to provide a layer deviation detection method and a layer deviation detection structure of a printed circuit board, so as to solve the technical problem that whether the layer deviation of the printed circuit board meets the requirements of customers or not can not be conveniently and effectively detected by the conventional printed circuit board.
In order to achieve the purpose, the technical scheme adopted by the application is as follows: a layer deviation detection method of a printed circuit board comprises the following steps:
obtaining a plurality of daughter boards and a plurality of conducting strips, wherein the conducting strips are provided with a first through hole and at least one second through hole;
the daughter boards and the conducting strips are overlapped alternately, so that each conducting strip is positioned between every two adjacent daughter boards;
arranging a first mark point and at least one second mark point on the surface of the daughter board at the outermost layer, wherein the first mark point is positioned on the axis of the first through hole, and the second mark point is positioned on the axis of the second through hole;
pressing the daughter board and the conducting strip into a printed circuit board;
aligning the first mark point on the surface of the daughter board at the outermost layer and drilling along the thickness direction of the printed circuit board, and aligning the second mark point on the surface of the daughter board at the outermost layer and drilling along the thickness direction of the printed circuit board;
arranging a metal layer on the wall of the drilled hole to enable each layer of the daughter board to form a first metalized hole with the radius equal to that of the first through hole and a second metalized hole with the radius smaller than that of the second through hole; and
and one test needle of the test device is in conductive connection with the metal layer of the first metalized hole of the outermost daughter board, the other test needle is in conductive connection with the metal layer of the second metalized hole of the outermost daughter board, and whether the circuit between the two test needles is conducted or not is judged.
Further, after the step of forming a first metalized hole with a radius equal to that of the first through hole and a second metalized hole with a radius smaller than that of the second through hole in each layer of the daughter boards by arranging a metal layer on the hole wall of the drilled hole, a first conductive part for connecting one test pin of the test device and a second conductive part for connecting the other test pin of the test device are arranged on the surface of the outermost daughter board.
Further, the first conductive part comprises a first conductive ring, a first connecting block and a first contact block which are arranged on the surface of the outermost daughter board and electrically connected in sequence, and the first conductive ring is arranged around the periphery of the first metalized hole of the outermost daughter board and electrically connected with the metal layer on the hole wall of the first metalized hole of the outermost daughter board; the second conductive part comprises a second conductive ring, a second connecting block and a second contact block, the second conductive ring, the second connecting block and the second contact block are arranged on the surface of the outermost daughter board and are electrically connected in sequence, and the second conductive ring is arranged on the periphery of a second metalized hole of the outermost daughter board in a surrounding mode and is electrically connected with a metal layer on the hole wall of the second metalized hole of the outermost daughter board.
Furthermore, a first detection channel is formed by the first metalized holes of each layer of the daughter board and the first through holes of each layer of the conducting strips, a second detection channel is formed by the second metalized holes of each layer of the daughter board and the second through holes of each layer of the conducting strips, the second detection channels are provided with M groups, and in the M groups of second detection channels, the radius of the second metalized hole of the Nth group of second detection channels is smaller than that of the second through hole by Nmil; wherein M is a positive integer, and N is any one of positive integers between 1 and M.
Further, the second detection channel is provided with 8 groups, group 1 the radius of the second metallization hole of the second detection channel is smaller than the radius of the second through hole by 1mil, group 2 the radius of the second metallization hole of the second detection channel is smaller than the radius of the second through hole by 2 mils, group 3 the radius of the second metallization hole of the second detection channel is smaller than the radius of the second through hole by 3 mils, group 4 the radius of the second metallization hole of the second detection channel is smaller than the radius of the second through hole by 4 mils, group 5 the radius of the second metallization hole of the second detection channel is smaller than the radius of the second through hole by 5 mils, group 6 the radius of the second metallization hole of the second detection channel is smaller than the radius of the second through hole by 6 mils, group 7 the radius of the second metallization hole of the second detection channel is smaller than the radius of the second through hole by 7 mils, and group 8 the radius of the second metallization hole of the second detection channel is smaller than the radius of the second through hole by 8 mils.
The application also provides a layer deviation detection structure of the printed circuit board, which comprises a plurality of layers of sub-boards and a conducting strip arranged between every two adjacent sub-boards, wherein the sub-boards are provided with a first metalized hole and a second metalized hole in a penetrating manner along the thickness direction of the sub-boards, and the conducting strip is provided with a first through hole and a second through hole in a penetrating manner along the thickness direction of the conducting strip; the radius of the first metalized hole is equal to the radius of the first through hole, and the radius of the second metalized hole is smaller than the radius of the second through hole.
Furthermore, the first metalized hole of each layer of the daughter board and the first through hole of each layer of the conducting strip form a first detection channel, and the second metalized hole of each layer of the daughter board and the second through hole of each layer of the conducting strip form a second detection channel; the end part of the first detection channel is provided with a first conductive part used for being connected with a test needle, and the end part of the second detection channel is provided with a second conductive part used for being connected with the test needle.
Further, the first conductive part comprises a first conductive ring, a first connecting block and a first contact block which are arranged on the surface of the daughter board on the outermost layer and electrically connected in sequence, and the first conductive ring is arranged around the periphery of the first metalized hole and is electrically connected with the hole wall of the first metalized hole on the outermost layer in a metal manner; the second conductive part comprises a second conductive ring, a second connecting block and a second contact block, the second conductive ring is arranged on the surface of the outermost daughter board and is electrically connected with the surface of the outermost daughter board in sequence, and the second conductive ring is arranged around the periphery of the second metalized hole and is electrically connected with the hole wall of the outermost second metalized hole in a metal mode.
Furthermore, the second detection channels are provided with M groups, and in the M groups of second detection channels, the radius of the second metalized hole of the Nth group of second detection channels is smaller than the radius of the second through hole by Nmil; wherein M is a positive integer, and N is any one of positive integers between 1 and M.
Furthermore, four groups of layer deviation detection structures are arranged, and the four groups of layer deviation detection structures are arranged at four corners of the square printed circuit board in a one-to-one correspondence mode.
The beneficial effects of this application lie in, through the metal level electrically conductive connection with a test needle of testing arrangement and the first metallization hole of outermost daughter board, another test needle is electrically conductive connected with the metal level in the second metallization hole of outermost daughter board, then judges whether the circuit between two test needles switches on, can conveniently detect out printed circuit board's layer offset effectively whether satisfies customer's demand.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required to be used in the embodiments or the prior art description will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and for those skilled in the art, other drawings may be obtained according to these drawings without inventive labor.
FIG. 1 is a cross-sectional view of a layer offset detection structure in an embodiment of the present application, where the layer offset of a printed circuit board is zero;
FIG. 2 is a schematic view of the structure of the surface of the outermost daughter board in the embodiment of the present application;
FIG. 3 is a cross-sectional view taken along line A-A of FIG. 1;
fig. 4 is a schematic diagram of the position of the layer offset detection structure on the printed circuit board.
Wherein, each mark in the figure is:
1. a daughter board; 2. a conductive sheet; 3. a first through hole; 4. a second through hole; 5. a first metalized hole; 6. a second metalized hole; 7. a first conductive portion; 8. a first conductive ring; 9. a first connection block; 10. a first contact block; 11. a second conductive portion; 12. a second conductive ring; 13. a second connecting block; 14. a second contact block; 15. a first detection channel; 16. a second detection channel.
Detailed Description
In order to make the technical problems, technical solutions and advantageous effects to be solved by the present application clearer, the present application is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present application and are not intended to limit the present application.
It will be understood that when an element is referred to as being "secured to" or "disposed on" another element, it can be directly on the other element or be indirectly on the other element. When an element is referred to as being "connected to" another element, it can be directly or indirectly connected to the other element. The terms "upper", "lower", "left", "right", and the like, indicate orientations or positional relationships based on those shown in the drawings, are merely for convenience of description, and do not indicate or imply that the referred devices or elements must have a specific orientation, be constructed in a specific orientation, and operate, and thus are not to be construed as limiting the patent, and the specific meanings of the above terms will be understood by those skilled in the art according to specific situations. The terms "first", "second" and "first" are used merely for descriptive purposes and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features. The meaning of "plurality" is two or more unless specifically limited otherwise.
As shown in fig. 1 to fig. 3, the method for detecting layer deviation of a printed circuit board according to the present embodiment includes the following steps:
the method comprises the steps that a plurality of daughter boards and a plurality of conducting strips are obtained, and a first through hole and at least one second through hole penetrate through the conducting strips along the thickness direction of the conducting strips;
the daughter boards and the conducting strips are overlapped alternately, so that each conducting strip is positioned between every two adjacent daughter boards;
arranging a first marking point and a second marking point on the surface of the daughter board at the outermost layer, wherein the first marking point is positioned on the axis of the first through hole, and the second marking point is positioned on the axis of the second through hole;
pressing the sub-boards and the conducting strips which are overlapped alternately into a printed circuit board;
aligning the first mark point on the surface of the daughter board at the outermost layer and drilling along the thickness direction of the printed circuit board, and aligning the second mark point on the surface of the daughter board at the outermost layer and drilling along the thickness direction of the printed circuit board;
arranging a metal layer (a copper deposition process can be carried out) on the hole wall of the drilled hole, so that each daughter board forms a first metalized hole with the radius equal to that of the first through hole and a second metalized hole with the radius smaller than that of the second through hole (at the moment, the metal layers with the same thickness can be formed on the hole wall of the first through hole and the hole wall of the second through hole), and forming a layer deviation detection structure; and
and one test needle of the test device is in conductive connection with the metal layer of the first metalized hole of the outermost daughter board, the other test needle is in conductive connection with the metal layer of the second metalized hole of the outermost daughter board, and whether the circuit between the two test needles is conducted or not is judged.
In the above steps, the daughter board is a single layer structure constituting the printed circuit board, and a corresponding circuit structure is provided on the daughter board; the first and second metallized holes are conductive structures having metal layers on Hole walls formed by a Hole metallization process (i.e., PTH). The conducting strip is a copper sheet and is arranged between every two layers of daughter boards in a pressing mode; the first via hole and the second via hole may be formed on the conductive sheet by etching, respectively.
In the above steps, since the first mark point is arranged on the axis of the first through hole, the second mark point is arranged on the axis of the second through hole, and the first metalized hole and the second metalized hole are formed by drilling holes respectively by aligning the drill bit with the first mark point and the second mark point, under ideal conditions (the layer offset of the printed circuit board is zero), the first metalized hole and the first through hole are coaxially arranged, the metal layer of the hole wall of the first metalized hole is in contact with the conductive sheet and can conduct electricity, and the second metalized hole and the second through hole are also coaxially arranged, but the metal layer of the hole wall of the first metalized hole is not in contact with the conductive sheet and can not conduct electricity.
In actual production, each daughter board of the printed circuit board can generate layer deviation in the laminating process, and whether the layer deviation of the printed circuit board meets the requirements of customers can be conveniently and effectively detected by adopting the layer deviation detection method. If the circuit between the two test needles is conducted, it is indicated that the metal layer of the hole wall of the second metalized hole is in contact with the conducting sheet, and the offset generated by the conducting sheet and the daughter board during pressing exceeds the difference value between the radius of the second through hole and the radius of the second metalized hole, so that the layer offset of the printed circuit board can be judged to be out of the difference value between the radius of the second through hole and the radius of the second metalized hole; if the circuit between the two test needles is not conducted, it is indicated that the metal layer of the hole wall of the second metalized hole is not in contact with the conducting sheet, and the offset generated by the conducting sheet and the daughter board during pressing does not exceed the difference value between the radius of the second through hole and the radius of the second metalized hole, so that the layer offset of the printed circuit board can be judged to be within the difference value between the radius of the second through hole and the radius of the second metalized hole.
For example, if a customer requests to produce a batch of printed circuit boards with layer offsets within 5 mils (1mil is equal to 0.025mm), in the layer offset detection method, the radius of the second metalized hole is smaller than the radius of the second through hole by 5 mils, and if the circuit between the two test pins is not conducted, the layer offset of the produced printed circuit board is within 5 mils, so as to meet the customer requirements; if the circuit between the two testing pins is conducted, the layer deviation of the produced printed circuit board is beyond 5mil, and the requirement of a customer is not met.
Preferably, after the step of forming the metal layer on the hole wall of the drilled hole and forming the first metalized hole having a radius equal to the radius of the first through hole and the second metalized hole having a radius smaller than the radius of the second through hole in each of the daughter boards, a first conductive portion for connecting one test pin of the test device and a second conductive portion for connecting the other test pin of the test device are provided on the surface of the outermost daughter board. In the layer deviation detection method, the two test needles of the test device do not need to be respectively inserted into the first metal hole and the second metal hole of the daughter board, can be directly contacted with the first conductive part and the second conductive part on the surface of the outermost layer of the daughter board, and can be in conductive connection with the first metal hole and the second metal hole.
Specifically, the first conductive part comprises a first conductive ring, a first connecting block and a first contact block, wherein the first conductive ring, the first connecting block and the first contact block are arranged on the surface of the outermost daughter board and are electrically connected in sequence, and the first conductive ring surrounds the periphery of the first metallization hole of the outermost daughter board and is electrically connected with the metal layer of the hole wall of the first metallization hole of the outermost daughter board. The second conductive part comprises a second conductive ring, a second connecting block and a second contact block which are arranged on the surface of the outermost daughter board and electrically connected in sequence, and the second conductive ring surrounds the periphery of the second metalized hole in the outermost daughter board and is electrically connected with the metal layer of the hole wall of the second metalized hole in the outermost daughter board. When the layer is inclined to one side to detect, two test needles contact with first contact piece and second contact piece respectively, and first contact piece can be drawn forth to suitable position through first connecting block from the tip in first metallization hole, and the second contact piece can be drawn forth to suitable position through the second connecting block from the tip in second metallization hole, makes the testing process more convenient.
As a further optimization, the surface of the first contact block is provided with a first groove for accommodating the end of the test pin, and the surface of the second contact block is provided with a second groove for accommodating the end of the test pin. When in test, the end parts of the two test pins are respectively accommodated in the first groove and the second groove, so that the test pins can be prevented from sliding off the surface of the first contact block or the second contact block.
For further optimization, the first metalized holes of each layer of daughter board and the first through holes of each layer of conducting strip form a first detection channel, the second metalized holes of each layer of daughter board and the second through holes of each layer of conducting strip form a second detection channel, the second detection channel is provided with M groups, and in the M groups of second detection channels, the radius of the second metalized hole of the Nth group of second detection channels is smaller than the radius of the second through hole by Nmil; wherein M is a positive integer, and N is any one of positive integers between 1 and M. The range of printed circuit board layer offsets can be determined.
In one embodiment, the second detection channels are arranged in 8 groups, the radius of the second metallization hole of the second detection channel in group 1 is 1mil smaller than the radius of the second through hole, the radius of the second metallization hole of the second detection channel in group 2 is 2mil smaller than the radius of the second through hole, the radius of the second metallization hole of the second detection channel in group 3 is 3mil smaller than the radius of the second through hole, the radius of the second metallization hole of the second detection channel in group 4 is 4mil smaller than the radius of the second through hole, the radius of the second metallization hole of the second detection channel in group 5 is 5mil smaller than the radius of the second through hole, the radius of the second metallization hole of the second detection channel in group 6 is 6mil smaller than the radius of the second through hole, the radius of the second metallization hole of the second detection channel in group 7 is 7mil smaller than the radius of the second through hole, and the radius of the second metallization hole of the second detection channel in group 8 is 8mil smaller than the radius of the second through hole. In fig. 1 and 2, a first detection channel, a 1 st group of second detection channels, a 2 nd group of second detection channels, a 3 rd group of second detection channels, a 4 th group of second detection channels, a 5 th group of second detection channels, a 6 th group of second detection channels, a 7 th group of second detection channels, and an 8 th group of second detection channels are arranged from left to right in sequence.
During detection, the step of electrically connecting one test pin of the test device with the metal layer of the first metalized hole of the outermost daughter board, electrically connecting the other test pin with the metal layer of the second metalized hole of the outermost daughter board, and judging whether a circuit between the two test pins is conducted specifically includes the following substeps:
s1, electrically connecting a first test needle of the test device with a metal layer of a first metalized hole of a first detection channel, electrically connecting a second test needle with a metal layer of a second metalized hole of a second detection channel of the 1 st group, judging whether a circuit between the two test needles is conducted, if the circuit between the two test needles is not conducted, indicating that the layer offset range of the printed circuit board is 0-1 mil, and if the circuit between the two test needles is conducted, entering the next substep S2.
S2, a first test needle of the test device is in conductive connection with a metal layer of a first metallized hole of a first detection channel, a second test needle is in conductive connection with a metal layer of a second metallized hole of a second detection channel of the 2 nd group, whether a circuit between the two test needles is conducted or not is judged, if the circuit between the two test needles is not conducted, the layer offset range of the printed circuit board is 1-2 mil, and if the circuit between the two test needles is conducted, the next substep S3 is entered.
S3, electrically connecting a first test needle of the test device with a metal layer of a first metalized hole of a first detection channel, electrically connecting a second test needle with a metal layer of a second metalized hole of a second detection channel of the 3 rd group, judging whether a circuit between the two test needles is conducted, if the circuit between the two test needles is not conducted, indicating that the layer offset range of the printed circuit board is 2-3 mil, and if the circuit between the two test needles is conducted, entering the next substep S4.
S4, a first test needle of the test device is in conductive connection with a metal layer of a first metallized hole of a first detection channel, a second test needle is in conductive connection with a metal layer of a second metallized hole of a second detection channel of the 4 th group, whether a circuit between the two test needles is conducted or not is judged, if the circuit between the two test needles is not conducted, the layer offset range of the printed circuit board is 3-4 mil, and if the circuit between the two test needles is conducted, the next substep S5 is entered.
S5, a first test pin of the test device is in conductive connection with the metal layer of the first metalized hole of the first detection channel, a second test pin is in conductive connection with the metal layer of the second metalized hole of the second detection channel of the 5 th group, whether a circuit between the two test pins is conducted or not is judged, if the circuit between the two test pins is not conducted, the layer offset range of the printed circuit board is 4-5 mil, and if the circuit between the two test pins is conducted, the next substep S6 is entered.
S6, a first test needle of the test device is in conductive connection with a metal layer of a first metallized hole of a first detection channel, a second test needle is in conductive connection with a metal layer of a second metallized hole of a second detection channel of the 6 th group, whether a circuit between the two test needles is conducted or not is judged, if the circuit between the two test needles is not conducted, the layer offset range of the printed circuit board is 5-6 mil, and if the circuit between the two test needles is conducted, the next substep S7 is entered.
S7, a first test needle of the test device is in conductive connection with a metal layer of a first metalized hole of a first detection channel, a second test needle is in conductive connection with a metal layer of a second metalized hole of a second detection channel of the 7 th group, whether a circuit between the two test needles is conducted or not is judged, if the circuit between the two test needles is not conducted, the layer offset range of the printed circuit board is 6-7 mil, and if the circuit between the two test needles is conducted, the next substep S8 is entered.
S8, electrically connecting a first test needle of the test device with a metal layer of a first metalized hole of a first detection channel, electrically connecting a second test needle with a metal layer of a second metalized hole of a second detection channel of the 8 th group, judging whether a circuit between the two test needles is conducted, if the circuit between the two test needles is not conducted, indicating that the layer offset range of the printed circuit board is 7-8 mil, and if the circuit between the two test needles is conducted, indicating that the layer offset range of the printed circuit board exceeds 8 mil.
Through the substep, can conveniently detect printed circuit board's the scope that the layer is inclined to the bright (accurate to 1mil) effectively, through setting up different M values and different N values, can also satisfy the layer offset detection of various different printed circuit boards, satisfy the different requirements of customer to printed circuit board's layer offset.
As shown in fig. 1 to fig. 3, the layer deviation detecting structure of the printed circuit board provided in this embodiment includes multiple sub-boards and a conductive sheet disposed between every two adjacent sub-boards, where the sub-boards are provided with a first plated-through hole and a second plated-through hole along a thickness direction thereof, and the conductive sheet is provided with a first through hole and a second through hole along the thickness direction thereof; the radius of the first metallization hole is equal to the radius of the first through hole, and the radius of the second metallization hole is smaller than the radius of the second through hole. The first metallized holes of each layer of daughter boards and the first through holes of each layer of conducting strips form a first detection channel, and the second metallized holes of each layer of daughter boards and the second through holes of each layer of conducting strips form a second detection channel.
The layer deviation detection structure is formed on the printed circuit board through the steps in the layer deviation detection method, one test needle of the test device is in conductive connection with the metal layer of the first metalized hole of the outermost daughter board, the other test needle is in conductive connection with the metal layer of the second metalized hole of the outermost daughter board, and whether the layer deviation of the printed circuit board meets the customer requirements or not can be conveniently and effectively detected by judging whether a circuit between the two test needles is conducted or not.
As further optimization, a first conductive part used for connecting a test needle is arranged at the end part of the first detection channel, the first conductive part comprises a first conductive ring, a first connecting block and a first contact block which are arranged on the surface of the outermost layer of the sub-board and electrically connected in sequence, and the first conductive ring is arranged around the periphery of the first metalized hole and is electrically connected with the hole wall of the outermost layer of the first metalized hole in a metal mode; the end part of the second detection channel is provided with a second conductive part used for being connected with the test needle, the second conductive part comprises a second conductive ring, a second connecting block and a second contact block, the second conductive ring is arranged on the surface of the outermost layer of sub-board and is sequentially and electrically connected with the second connecting block, and the second conductive ring is arranged on the periphery of the second metalized hole in a surrounding mode and is electrically connected with the hole wall metal of the outermost layer of second metalized hole. When the layer is inclined to one side to detect, two test needles contact with first contact piece and second contact piece respectively, and first contact piece can be drawn forth to suitable position through first connecting block from the tip in first metallization hole, and the second contact piece can be drawn forth to suitable position through the second connecting block from the tip in second metallization hole, makes the testing process more convenient.
For further optimization, the second detection channels are provided with M groups, and in the M groups of second detection channels, the radius of the second metalized hole of the Nth group of second detection channels is smaller than the radius of the second through hole by Nmil; m is a positive integer, and N is any one of positive integers between 1 and M.
In one embodiment, the second detection channels are provided with 8 groups, the radius of the second metalized hole of the 1 st group of second detection channels is 1mil smaller than that of the second through hole, the radius of the second metalized hole of the 2 nd group of second detection channels is 2mil smaller than that of the second through hole, the radius of the second metalized hole of the 3 rd group of second detection channels is 3mil smaller than that of the second through hole, the radius of the second metalized hole of the 4 th group of second detection channels is 4mil smaller than that of the second through hole, the radius of the second metalized hole of the 5 th group of second detection channels is 5mil smaller than that of the second through hole, the radius of the second metalized hole of the 6 th group of second detection channels is 6mil smaller than that of the second through hole, the radius of the second metalized hole of the 7 th group of second detection channels is 7mil smaller than that of the second through hole, and the radius of the second metalized hole of the 8 th group of second detection channels is 8mil smaller than that of the second through hole.
As shown in fig. 4, as a further optimization, four sets of the layer deviation detecting structures are provided, and the four sets of the layer deviation detecting structures are arranged at four corners of the square printed circuit board in a one-to-one correspondence manner. Specifically, the square printed circuit board is provided with two SET process edges which are arranged oppositely, two groups of layer deviation detection structures are positioned at two ends of one SET process edge, and the other two groups of layer deviation detection structures are positioned at two ends of the other SET process edge. During the layer deviation test, each unit (PCS) in the printed circuit board is positioned in a frame formed by the four groups of layer deviation detection structures, and the layer deviation test is respectively carried out on the four groups of layer deviation detection structures, so that the layer deviation quality of each unit in the printed circuit board can be ensured.
The above description is only exemplary of the present application and should not be taken as limiting the present application, as any modification, equivalent replacement, or improvement made within the spirit and principle of the present application should be included in the protection scope of the present application.
Claims (4)
1. A layer deviation detection method of a printed circuit board is characterized by comprising the following steps:
obtaining a plurality of daughter boards and a plurality of conducting strips, wherein the conducting strips are provided with a first through hole and at least one second through hole;
the daughter boards and the conducting strips are overlapped alternately, so that each conducting strip is positioned between every two adjacent daughter boards;
arranging a first mark point and at least one second mark point on the surface of the daughter board at the outermost layer, wherein the first mark point is positioned on the axis of the first through hole, and the second mark point is positioned on the axis of the second through hole;
pressing the daughter board and the conducting strip into a printed circuit board;
aligning the first mark point on the surface of the daughter board at the outermost layer and drilling along the thickness direction of the printed circuit board, and aligning the second mark point on the surface of the daughter board at the outermost layer and drilling along the thickness direction of the printed circuit board;
arranging a metal layer on the wall of the drilled hole to form a first metalized hole with the radius equal to that of the first through hole and a second metalized hole with the radius smaller than that of the second through hole on each layer of the daughter board, a first conductive portion for connecting one test pin of a test device and a second conductive portion for connecting the other test pin of the test device are provided on the surface of the daughter board on the outermost layer, the first conductive part comprises a first conductive ring, a first connecting block and a first contact block which are arranged on the surface of the daughter board at the outermost layer and are electrically connected in sequence, the surface of the first contact block is provided with a first groove used for accommodating the end part of a test needle, and the first conducting ring is arranged around the periphery of the first metalized hole of the sub-board on the outermost layer and is electrically connected with the metal layer on the hole wall of the first metalized hole of the sub-board on the outermost layer; the second conductive part comprises a second conductive ring, a second connecting block and a second contact block which are arranged on the surface of the outermost daughter board and are electrically connected in sequence, a second groove used for containing the end part of the test pin is formed in the surface of the second contact block, and the second conductive ring is arranged around the periphery of a second metalized hole of the outermost daughter board and is electrically connected with a metal layer on the hole wall of the second metalized hole of the outermost daughter board; and
one test needle of the test device is in conductive connection with the metal layer of the first metalized hole of the outermost daughter board, the other test needle is in conductive connection with the metal layer of the second metalized hole of the outermost daughter board, and whether a circuit between the two test needles is conducted or not is judged;
the first metalized holes of each layer of the daughter board and the first through holes of each layer of the conducting strips form a first detection channel, the second metalized holes of each layer of the daughter board and the second through holes of each layer of the conducting strips form a second detection channel, the second detection channels are provided with M groups, and in the M groups of the second detection channels, the radius of the second metalized holes of the Nth group of the second detection channels is smaller than the radius of the second through holes by Nmil; wherein M is a positive integer, and N is any one of positive integers between 1 and M.
2. The method according to claim 1, wherein the second detection channels are provided in 8 groups, the radius of the second metallization hole of the second detection channel in group 1 is 1mil smaller than the radius of the second through hole, the radius of the second metallization hole of the second detection channel in group 2 is 2mil smaller than the radius of the second through hole, the radius of the second metallization hole of the second detection channel in group 3 is 3mil smaller than the radius of the second through hole, the radius of the second metallization hole of the second detection channel in group 4 is 4mil smaller than the radius of the second through hole, the radius of the second metallization hole of the second detection channel in group 5 is 5mil smaller than the radius of the second through hole, the radius of the second metallization hole of the second detection channel in group 6 is 6mil smaller than the radius of the second through hole, and the radius of the second metallization hole of the second detection channel in group 7 is 7mil smaller than the radius of the second through hole, and the radius of the second metalized hole of the 8 th group of second detection channels is 8 mils smaller than that of the second through hole.
3. The layer deviation detection structure of the printed circuit board is characterized by comprising a plurality of layers of sub-boards and a conducting strip arranged between every two adjacent sub-boards, wherein the sub-boards are provided with a first metalized hole and a second metalized hole in a penetrating manner along the thickness direction of the sub-boards, and the conducting strip is provided with a first through hole and a second through hole in a penetrating manner along the thickness direction of the conducting strip; the radius of the first metalized hole is equal to that of the first through hole, and the radius of the second metalized hole is smaller than that of the second through hole; the first metallized holes of each layer of the daughter board and the first through holes of each layer of the conducting strips form a first detection channel, and the second metallized holes of each layer of the daughter board and the second through holes of each layer of the conducting strips form a second detection channel; the end part of the first detection channel is provided with a first conductive part used for being connected with a test needle, the end part of the second detection channel is provided with a second conductive part used for being connected with the test needle, the first conductive part comprises a first conductive ring, a first connecting block and a first contact block, the first conductive ring, the first connecting block and the first contact block are arranged on the surface of the outermost daughter board and are sequentially and electrically connected, a first groove used for containing the end part of the test needle is formed in the surface of the first contact block, and the first conductive ring is arranged on the periphery of a first metalized hole of the outermost daughter board in a surrounding mode and is electrically connected with a metal layer on the hole wall of the first metalized hole of the outermost daughter board; the second conductive part comprises a second conductive ring, a second connecting block and a second contact block which are arranged on the surface of the outermost daughter board and are electrically connected in sequence, a second groove used for containing the end part of the test pin is formed in the surface of the second contact block, and the second conductive ring is arranged around the periphery of a second metalized hole of the outermost daughter board and is electrically connected with a metal layer on the hole wall of the second metalized hole of the outermost daughter board;
the second detection channels are provided with M groups, and in the M groups of second detection channels, the radius of a second metalized hole of the Nth group of second detection channels is smaller than the radius of a second through hole by Nmil; wherein M is a positive integer, and N is any one of positive integers between 1 and M.
4. The structure of claim 3, wherein four sets of the layer deviation detecting structures are provided, and the four sets of the layer deviation detecting structures are provided at four corners of the square printed circuit board in a one-to-one correspondence.
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| CN112911791B (en) * | 2021-01-29 | 2022-12-06 | 南通强达电路科技有限公司 | Printed circuit board for detecting deviation of drilling hole |
| CN114585166B (en) * | 2022-04-29 | 2022-08-16 | 苏州东山精密制造股份有限公司 | Layer deviation detection method for flexible antenna multilayer board |
| CN115135000A (en) * | 2022-08-09 | 2022-09-30 | 生益电子股份有限公司 | Printed circuit board and preparation method |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1159001A (en) * | 1996-02-13 | 1997-09-10 | 日本电子材料株式会社 | Probe, manufacture of same, and vertically operative type probe card assembly employing same |
| TW407799U (en) * | 1999-01-13 | 2000-10-01 | Acer Neweb Corp | Feed source wave concentrating device |
| TW201131890A (en) * | 2009-03-24 | 2011-09-16 | Raytheon Co | Panel array |
| CN102665541A (en) * | 2009-09-29 | 2012-09-12 | C·R·巴德股份有限公司 | Stylets for use with apparatus for intravascular placement of a catheter |
| CN103513069A (en) * | 2012-06-21 | 2014-01-15 | 深圳麦逊电子有限公司 | Test probe device |
| CN105916314A (en) * | 2016-06-03 | 2016-08-31 | 深圳市景旺电子股份有限公司 | Multilayer soft plate manufacturing method capable of avoiding interlayer dislocation and multilayer soft plate |
| CN108925066A (en) * | 2018-08-28 | 2018-11-30 | 深圳市景旺电子股份有限公司 | A kind of multi-layer board interlayer bias detecting method and detection system |
Family Cites Families (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100525228B1 (en) * | 2003-11-22 | 2005-10-28 | 삼성전기주식회사 | Fabricating method of printed circuit board equipping optical waveguide |
| CN101697001B (en) * | 2009-01-22 | 2011-07-13 | 依利安达(广州)电子有限公司 | Method for detecting positional deviation among layers of multilayer printed circuit board |
| KR101173863B1 (en) * | 2010-06-10 | 2012-08-14 | 삼성에스디아이 주식회사 | Electrode assembly and rechargeable battery using thereof |
| CN201715996U (en) * | 2010-07-06 | 2011-01-19 | 瀚宇博德股份有限公司 | Interlayer offset measuring device |
| TWI417549B (en) * | 2010-07-12 | 2013-12-01 | Mpi Corp | The method of making the probe head of the vertical probe card and its composite board |
| CN102539996A (en) * | 2011-12-08 | 2012-07-04 | 东莞市五株电子科技有限公司 | Detection method and system for layers of multilayer circuit board |
| CN103363885B (en) * | 2012-03-31 | 2016-12-14 | 北大方正集团有限公司 | Measure the method for side-play amount between PCB layer and PCB in making sheet |
| KR101309479B1 (en) * | 2012-05-30 | 2013-09-23 | 삼성전기주식회사 | Laminated chip electronic component, board for mounting the same, packing unit thereof |
| CN105716512A (en) * | 2014-12-03 | 2016-06-29 | 北大方正集团有限公司 | Interlayer alignment prompt module and method |
| CN104582331B (en) * | 2014-12-31 | 2017-10-17 | 广州兴森快捷电路科技有限公司 | The internal layer off normal detection method of multilayer circuit board |
| CN109526156B (en) * | 2018-11-05 | 2021-04-06 | 深圳崇达多层线路板有限公司 | Detection module and detection method for detecting deviation degree of drilling hole |
| CN109982520A (en) * | 2019-03-22 | 2019-07-05 | 泉州齐美电子科技有限公司 | A kind of printed circuit board structure and preparation method thereof |
-
2020
- 2020-01-03 CN CN202010006126.5A patent/CN111157879B/en active Active
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1159001A (en) * | 1996-02-13 | 1997-09-10 | 日本电子材料株式会社 | Probe, manufacture of same, and vertically operative type probe card assembly employing same |
| US6300783B1 (en) * | 1996-02-13 | 2001-10-09 | Nihon Denshizairyo Kabushiki Kaisha | Probe, manufacture of same, and vertically operative type probe card assembly employing same |
| TW407799U (en) * | 1999-01-13 | 2000-10-01 | Acer Neweb Corp | Feed source wave concentrating device |
| TW201131890A (en) * | 2009-03-24 | 2011-09-16 | Raytheon Co | Panel array |
| CN102665541A (en) * | 2009-09-29 | 2012-09-12 | C·R·巴德股份有限公司 | Stylets for use with apparatus for intravascular placement of a catheter |
| CN103513069A (en) * | 2012-06-21 | 2014-01-15 | 深圳麦逊电子有限公司 | Test probe device |
| CN105916314A (en) * | 2016-06-03 | 2016-08-31 | 深圳市景旺电子股份有限公司 | Multilayer soft plate manufacturing method capable of avoiding interlayer dislocation and multilayer soft plate |
| CN108925066A (en) * | 2018-08-28 | 2018-11-30 | 深圳市景旺电子股份有限公司 | A kind of multi-layer board interlayer bias detecting method and detection system |
Non-Patent Citations (2)
| Title |
|---|
| Layer assignment for printed circuit boards and integrated circuits;D.A. Joy 等;《 Proceedings of the IEEE》;19920228;第80卷(第2期);311 - 331 * |
| PCB板自动检测装置机械手的改进设计研究;郑宇航 等;《青岛大学学报(工程技术版)》;20190515;第34卷(第2期);63-67，77 * |
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