CN111129119B - 一种碳化硅mos的单粒子加固器件结构及其制备方法 - Google Patents
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Abstract
本发明涉及一种碳化硅MOS的单粒子加固器件结构及其制备方法，属于半导体器件技术领域。本发明在双沟道MOS(DT‑MOS)器件基础上，提出了一种倒锤型的槽栅结构及其实现方法，可以抑制寄生NPN晶体管的闩锁效应，提高碳化硅MOSFET的单粒子烧毁阈值电压，有效解决现有碳化硅MOSFET技术的抗单粒子烧毁能力低的技术难题，还可提升器件短路能力和雪崩能力。本发明可应用于工作在航天器、核电站等高能带电粒子环境下的器件的设计和制造，有效提升设备系统的可靠性和安全性。
Description
技术领域：
本发明涉及一种单粒子加固器件结构及其制备方法，特别涉及一种倒锤型的槽栅结构双沟道MOS器件及其制备方法，属于半导体功率器件技术领域。这种器件适用于有高能带电粒子存在的空间工作环境，可提高功率MOSFET在空间工作环境下抗单粒子烧毁能力、抗短路电流能力和关断性能。
背景技术：
随着航天技术的不断发展，特别是宇宙空间大功率电源系统、高温电推进处理单元，以及太空探测器等极端环境和工作条件，对大功率耐高温的器件需求日益明显。
碳化硅(SiC)半导体材料与常用的第一代半导体材料硅(Si)相比，在多个方面具有明显的优势。碳化硅(SiC)具有宽禁带(Si的2～3倍)、高击穿场强(Si的10倍)、高的热导率(Si的3倍)和强的抗辐射能力。在传统的硅以及砷化镓器已经不能满足系统安全性以及可靠性的要求的情况下，碳化硅器件具有耐高温，抗辐射等优点，因而在航天大功率、高频、高温系统中有很好的应用前景。
目前航空航天影响器件可靠性的辐射效应主要有两种，一种是总剂量电离辐射效应(TID)，对于低轨卫星，经过长时间的积累，会有超过10krad(Si)的总剂量水平，高轨卫星甚至可以累计超过1Mrad(Si)的总剂量，使得器件性能不断退化。另一种是单粒子效应(SEE)，单粒子效应是指单个高能粒子穿过微电子器件的灵敏区时造成器件状态的非正常改变的一种辐射效应，其中单粒子烧毁(SEB)是场效应管漏极-源极局部烧毁，属于破坏性效应。入射粒子产生的瞬态电流导致敏感的寄生双极结晶体管导通，双极结晶体管的再生反馈机制造成集电极电流不断增大，直至产生二次击穿，造成漏极-源极永久短路，引起电路烧毁，研究表明现有的SIC器件具有很强的抗TID的能力，但是抗SEB能力普遍很差。现有硅基抗辐射MOS器件可以通过100％额定电压下的单粒子考核，而现有SIC的MOSFET只能通过10～15％额定电压下的单粒子考核。因此，SIC的SEB能力很差，严重制约了SIC器件宇航应用，本发明专门解决SIC的单粒子加固问题。
发明内容：
本发明主要针对传统双沟道MOSFET器件在空间工作环境中容易发生单粒子烧毁的问题进行改进，以及其在高功率工作时寄生晶体管导通引起烧毁的问题。
常规的沟道MOS(TMOS)结构如图1(a)所示，其栅下方会存在固有NPN寄生晶体管，导致抗单粒子能力差。在太空中的高能粒子入射处，栅下方结处电场强度增加，寄生BJT发射结正偏程度增强，触发晶体管误导通，导致高能量粒子入射处产生电流局部集中，造成芯片局部过热，直至器件烧毁，即发生单粒子烧毁SEB(single event burnout)。SEB会引起器件不可恢复的损伤，这会直接导致电子系统的功能失效，影响航天器在轨的安全性和可靠性。因此我们需要优化现有TMOS结构，增强其抗单粒子能力。
为实现上述目的，本发明的一种倒锤型的槽栅结构的槽栅功率MOS器件(Double-trench MOSFETs with Source-Recessed，以下称为SR-DT-MOS)结构如图1(b)所示，可以看出构成寄生晶体管发射区和基区的n+区与p阱区不再直接相连，而是被倒锤形槽栅的宽槽底结构阻隔。因此，垂直方向上不再形成npn晶体管的寄生结构，这就抑制了功率MOS的闩锁效应，改善栅下端的高电场，改变寄生晶体管结构使其不容易在高的工作功率下导通引起烧毁，防止二次击穿从而使其有更强的抗单粒子烧毁能力。
有益效果
1、提升抗单粒子烧毁的能力。单粒子烧毁(SEB)是由于高能粒子入射到半导体器件后，产生的电子空穴对在电场的作用下发生雪崩倍增效应，在粒子的行迹上聚集的电荷量超越临界值，导致寄生NPN晶体管被激活，在局部产生非常高的瞬态电流导致热烧毁，图2显示了两种结构在失效电压下，漏电流随时间的变化，可以看出SR-DT-MOS失效电压为150V而DT-MOS为91V提高了67％，而图3的t＝4ps时的电场分布也可以看出寄生NPN晶体管的导通受到了抑制，阻止了雪崩倍增效应的发生，从而提高了抗单粒子烧毁效应的能力。
2、提升了抗短路电流能力。所述槽栅结构的倒锤型结构以及N型源区的特殊位置分布的主要作用是改善槽栅附近的电场分布，减弱寄生晶体管的影响使其难以导通，增强其短路特性。高功率工作状态下的器件漏电流随着功率的上升，直到寄生NPN寄生晶体管导通的临界点，寄生晶体管导通会导致漏电流迅速增大，对比传统的双沟道MOS和改良后的本发明结构，图4是接受相同应力条件下同一时间时两种结构的晶格温度变化情况，图5是两种结构的短路特性曲线。可以看出SR-DT-MOS的短路电流明显低于DT-MOS，使得最高晶格温度降低了近50K。由曲线可以看出，在40μs时SR-DT-MOS的拖尾电流相比DT-MOS减小了近8倍，最后结果SR-DT-MOS仍然可以正常工作而DT-MOS失效。
3、优化的关断性能。此发明的雪崩特性也优于传统DT-MOS，雪崩电流Iav由
附图说明：
一个或多个实例通过与之对应的附图中的图片进行示例性说明，这些示例性说明并不构成对实例的限定，附图中具有相同参考数字标号的元件表示为类似的元件，除非有特别申明，附图中的图不构成比例限制。
图1a SIC DT-MOS截面示意图
图1b SIC SR-DT-MOS截面示意图
图2 SiC DT-MOS和SiC SR-DT-MOS两种器件在重离子入射情况时，在失效电压下漏电流随时间的变化
图3a SiC DT-MOS在t＝4ps时的电场分布
图3b SiC SR-DT-MOS在t＝4ps时的电场分布
图4a SiC DT-MOS在接受相同应力条件下同一时间时两种结构的晶格温度变化情况
图4b SiC SR-DT-MOS在接受相同应力条件下同一时间时两种结构的晶格温度变化情况
图5 SiC DT-MOS和SiC SR-DT-MOS的失效时的短路特性
图6 SiC DT-MOS和SiC SR-DT-MOS两种器件失效时的UIS曲线
图7 SiC DT-MOS和SiC SR-DT-MOS两种器件在L＝23μH时放大后的UIS曲线
图8a SiC DT-MOS在T＝90μs时电子电流密度的分布
图8b SiC SR-DT-MOS在T＝90μs时电子电流密度的分布
图9发明所提出的栅结构的工艺流程，其中，(a)沉积Si3N4作为阻挡层，(b)蚀刻Si3N4和SiC(各向异性)，(c)蚀刻SiC(各向同性)，(d)牺牲氧化(湿法)，(e)剥离Si3N4和氧化物，(f)栅极氧化(湿)
图10-图19 SiC SR-DT-MOS的制备工艺流程
具体实施方式
以下通过特定的具体实例说明本发明的实施方式，本领域技术人员可由本说明书所揭露的内容轻易地了解本发明的其他优点与功效。本发明还可以通过另外不同的具体实施方式加以实施或应用，本说明书中的各项细节也可以基于不同观点与应用，在没有背离本发明的精神下进行各种修饰或改变。
下面通过实施例以及附图对本发明进行进一步说明
本发明的单粒子加固倒锤型的槽栅结构1200V碳化硅功率MOS器件结构如图1(b)所示，具体包括：
在衬底2下方的漏极金属1，位于衬底上的N型漂移区3，其掺杂浓度为1.2×1016cm-3，厚度为10μm，元胞宽度为3μm，在N型漂移区3上方扩散形成的P阱区6，其结深为0.5μm，在P阱区6中间的槽型多晶硅栅以及其表面的氧化层4、5栅槽底宽度为1μm，槽顶窄部宽度为0.5μm，P阱区6上表面的左右内侧的N+源区7，其掺杂浓度为2.5×1017cm-3，紧靠P阱区6上表面的左右外侧重掺杂形成的P+区8，其掺杂浓度为8×1017cm-3，在P型N型漂移区上以及重掺杂P+区中间的P型源区9，以及在其上方的源极金属电极10。
具体包括以下步骤：
a、首先提供一个高掺杂衬底，此衬底为图1(b)中的2，此衬底为高掺杂N型单晶硅衬底，衬底厚度为100μm。
b、在所述衬底2上方外延一个低掺杂外延层，形成厚度约为8μm的N型漂移区3。
c、在所述N型漂移区上方进行2～5次能量为100keV～300keV的铝离子注入，形成P区，如图11，然后在P区上刻蚀形成一次凹槽，形成最终的L型P型源区(9)，如图12；
d、在所述N型漂移区3上方整个有源区进行2～5次能量为100keV～600keV的铝离子注入，形成P阱区6。
e、在P阱区6和P型源区9上方分别注入两次，分别掺入氮和铝，形成N+区7和P+区8。
f、在7处刻蚀深约0.3μm的凹槽用于接下来的倒锤型的槽栅结构工艺的实施，如图15；
j、此发明结构在工艺上的实施难点是SR-DT-MOS的倒锤型的槽栅结构。图9展示了所提出的栅结构的改进流程，图9详细说明了从图15到图18的工艺流程，可以根据由Si3N4层筛选的各向同性蚀刻工艺来对栅极沟槽的下部进行处理。通过腐蚀氧化层去除尖刺，并且还进一步加宽了沟槽的弯曲部分。最后，采用湿式氧化形成栅氧化膜，具体尺寸参考图1(b)的标注。其具体步骤为：
(1)在上述7、8上方沉积Si3N4作为阻挡层，如图9(a)所示
(2)各向异性蚀刻Si3N4贯穿6、7直到3的上方，形成如图9(b)所示的竖直凹槽；
(3)利用各向同性蚀刻，刻蚀竖直凹槽部分，形成如图9(c)中所示栅的形状；
(4)利用湿法氧化，在槽内测进行牺牲氧化，如图9(d)所示；
(5)剥离Si3N4和氧化物，如图9(e)所示；
(6)利用湿法氧化栅极氧化，如图9(f)所示。
后续工艺采用常规SIC的多晶和介质淀积、刻蚀和金属化等常规工艺，不做论述。
本发明与传统的DT-MOS工艺MOS器件相比，改善变了有源区结构，使得源区重掺杂P+区更好的跟源极金属接触。凹形槽栅结构也易于制造，它可以抑制寄生NPN晶体管的闩锁效应，提高器件二次击穿水平，从而提高碳化硅MOSFET的单粒子烧毁阈值电压，进一步提高了器件抗单粒子烧毁的能力，结构紧凑，可靠性也更好。
Claims (6)
1.一种单粒子加固倒锤型的槽栅结构功率MOS器件，包括：
硅衬底(2)，
漏极金属电极(1)位于衬底(2)下方，
N型漂移区(3)位于衬底(2)上方，
左右两个P阱区(6)位于N型漂移区(3)上方，
重掺杂形成的P+区(8)紧靠P阱区(6)上表面的左右两端，
N+源区(7)紧靠(8)左右内侧以及P阱区(6)上表面，
槽型多晶硅栅(4)以及环绕其表面的氧化层(5)位于P阱区(6)、N+源区(7)的中间，并贯穿P阱区(6)、N+源区(7)及部分N型漂移区(3)，
P型源区(9)为L型，位于在N型漂移区(3)以及重掺杂P+区(8)之间，
源极金属电极10位于N+源区(7)、重掺杂P+区(8)、P型源区(9)外表面。
2.根据权利要求1所述的一种单粒子加固倒锤型的槽栅结构功率MOS器件，其特征在于：所述的衬底(2)是高掺杂N型单晶碳化硅或硅衬底。
3.根据权利要求1所述的一种单粒子加固倒锤型的槽栅结构功率MOS器件结构，其特征是：所述的N型漂移区（3）为一个低掺杂外延层，厚度约为10～100μm。
4.根据权利要求1所述的一种单粒子加固倒锤型的槽栅结构功率MOS器件结构，其特征是：在P阱区(6)和N型漂移区(3)中制备的倒锤型的槽栅结构，槽底宽处的宽度为0.6～1.0μm，槽顶窄处的宽度为0.3～0.5μm。
5.根据权利要求1所述的一种单粒子加固倒锤型的槽栅结构功率MOS器件结构，其特征是：在P阱区和N型漂移区中制备倒锤型的槽栅结构，其槽深为0.5μm～1.5μm。
6.一种碳化硅MOS的单粒子加固器件结构的制备方法，基于权利要求1所述的一种单粒子加固倒锤型的槽栅结构功率MOS器件结构，其特征在于：制备槽栅的工艺步骤为：
1)在N+源区(7)处刻蚀凹槽；
2)在上述N+源区(7)、重掺杂P+区(8)上方沉积Si3N4作为阻挡层；
3)各向异性蚀刻Si3N4贯穿P阱区(6)、N+源区(7)直到N型漂移区(3)的上方，形成竖直凹槽；
4)利用各向同性蚀刻，刻蚀竖直凹槽部分；
5)利用湿法氧化，在槽内侧进行牺牲氧化；
6)剥离Si3N4和氧化物；
7)利用湿法氧化栅极氧化。
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