CN111124032B

CN111124032B - Filter circuit for suppressing noise interference and micro control system

Info

Publication number: CN111124032B
Application number: CN201911328064.3A
Authority: CN
Inventors: 萧经华; 孙劲锋
Original assignee: Ruixing Technology Nanjing Co ltd
Current assignee: Ruixing Technology Nanjing Co ltd
Priority date: 2019-12-20
Filing date: 2019-12-20
Publication date: 2021-11-05
Anticipated expiration: 2039-12-20
Also published as: CN111124032A

Abstract

The invention provides a filter circuit for inhibiting noise interference and a micro control system, comprising: a bias module for generating a bias signal; the first time delay module is connected with the bias module, receives a synchronous signal and a reverse signal of an input signal and is used for generating a first time delay signal in the same direction as the input signal; and the second time delay module is used for receiving the synchronous signal and the reverse signal of the input signal and generating a second time delay signal reverse to the input signal. And the filter circuit for suppressing noise interference is connected to the input end of the microcontroller, and is used for suppressing the interference of the signal entering the microcontroller. The filter circuit for inhibiting noise interference and the micro control system ensure that noise on signals can be effectively filtered, and have good inhibiting effect on power supply noise; the output signal is stable.

Description

Filter circuit for suppressing noise interference and micro control system

Technical Field

The invention relates to the field of circuit control, in particular to a filter circuit for inhibiting noise interference and a micro-control system.

Background

In the application field of Micro Control Systems (MCUs), more and more peripheral components are used, so that the peripheral environment of the MCUs is complex and various: a plurality of components interconnect, a plurality of mains operated and a plurality of ground interconnect, MCU has high frequency clock and low frequency clock to use simultaneously, leads to MCU's operational environment to have very big noise and various interference.

There are two typical types of interference to signals in an MCU system: the signal is disturbed on the transmission path and the signal is disturbed by the power supply. As shown in fig. 1, the principle diagram of the interference of the signal on the transmission path is shown, the signal on the signal transmission path is subjected to coupling, crosstalk, etc., and the useful signal is interfered to generate jitter, glitch, etc. If the interference part of the signal is not filtered, misoperation of the signal can be caused, and the MCU system is disabled. As shown in fig. 2, which is a schematic diagram illustrating the interference of a signal by a power supply, when the signal is processed by a previous stage, if the power supply of the previous stage processing circuit has noise or jitter, the noise or jitter is directly reflected on the signal. If the signal interference caused by the power supply noise is not filtered, the signal is also influenced to generate misoperation, and the MCU system is caused to be invalid.

Therefore, how to suppress the interference of the signal and improve the stability of the micro control system has become one of the problems to be solved by those skilled in the art.

Disclosure of Invention

In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a filter circuit and a micro control system for suppressing noise interference, which are used to solve the problems of signal interference from transmission path and power supply, resulting in malfunction and system failure.

To achieve the above and other related objects, the present invention provides a filter circuit for suppressing noise interference, including at least:

a bias module for generating a bias signal;

the first time delay module is connected with the bias module, receives a synchronous signal and a reverse signal of an input signal and is used for generating a first time delay signal in the same direction as the input signal;

and the second time delay module is used for receiving the synchronous signal and the reverse signal of the input signal and generating a second time delay signal reverse to the input signal.

Optionally, the bias module receives a reference current, and generates a first bias voltage and a second bias voltage after mirroring the reference current.

More optionally, the bias module includes a first PMOS transistor, a second PMOS transistor, and a first NMOS transistor; the drain electrode of the first PMOS tube is connected with the reference current, the grid electrode of the first PMOS tube is connected with the drain electrode of the first PMOS tube and outputs a first bias voltage, and the source electrode of the first PMOS tube is connected with a power supply voltage; the source electrode of the second PMOS tube is connected with the power supply voltage, the grid electrode of the second PMOS tube is connected with the first bias voltage, and the drain electrode of the second PMOS tube is connected with the drain electrode of the first NMOS tube; and the grid electrode of the first NMOS tube is connected with the drain electrode and outputs a second bias voltage, and the source electrode is grounded.

More optionally, the first delay module includes a first switch, a second switch, a third switch, a fourth switch, a second NMOS transistor, a third NMOS transistor, a first capacitor, a third PMOS transistor, and a fourth PMOS transistor;

one end of the first switch is connected with a power supply voltage, and the other end of the first switch is connected with the grid electrode of the third PMOS tube; one end of the second switch is connected with the first bias voltage, and the other end of the second switch is connected with the grid electrode of the third PMOS tube;

one end of the third switch is connected with the second bias voltage, and the other end of the third switch is connected with the grid electrode of the second NMOS tube; one end of the fourth switch is grounded, and the other end of the fourth switch is connected with the grid electrode of the second NMOS tube;

the source electrode of the third PMOS tube is connected with the power supply voltage, and the drain electrode of the third PMOS tube is connected with the drain electrode of the second NMOS tube; the source electrode of the second NMOS tube is grounded; the first end of the first capacitor is connected with the drain electrodes of the third PMOS tube and the second NMOS tube, and the second end of the first capacitor is grounded;

the source electrode of the fourth PMOS tube is connected with the power supply voltage, the grid electrode of the fourth PMOS tube is connected with the first bias voltage, and the drain electrode of the fourth PMOS tube is connected with the drain electrode of the third NMOS tube; the grid electrode of the third NMOS tube is connected with the first end of the first capacitor, and the source electrode of the third NMOS tube is grounded; the drain electrodes of the fourth PMOS tube and the third NMOS tube output the first delay signal;

the control ends of the first switch, the second switch, the third switch and the fourth switch are respectively connected with a synchronous signal and a reverse signal of the input signal, the first switch and the third switch are conducted when the input signal is at a high level, and the second switch and the fourth switch are conducted when the input signal is at a low level.

More optionally, the second delay module includes a fifth switch, a sixth switch, a seventh switch, an eighth switch, a fourth NMOS transistor, a fifth NMOS transistor, a second capacitor, a fifth PMOS transistor, and a sixth PMOS transistor;

one end of the fifth switch is connected with a power supply voltage, and the other end of the fifth switch is connected with the grid electrode of the fifth PMOS tube; one end of the sixth switch is connected with the first bias voltage, and the other end of the sixth switch is connected with the grid electrode of the fifth PMOS tube;

one end of the seventh switch is connected with the second bias voltage, and the other end of the seventh switch is connected with the grid electrode of the fourth NMOS tube; one end of the eighth switch is grounded, and the other end of the eighth switch is connected with the grid electrode of the fourth NMOS tube;

the source electrode of the fifth PMOS tube is connected with the power supply voltage, and the drain electrode of the fifth PMOS tube is connected with the drain electrode of the fourth NMOS tube; the source electrode of the fourth NMOS tube is grounded; the first end of the second capacitor is connected with the drain electrodes of the fifth PMOS tube and the fourth NMOS tube, and the second end of the second capacitor is grounded;

the source electrode of the sixth PMOS tube is connected with the power supply voltage, the grid electrode of the sixth PMOS tube is connected with the first bias voltage, and the drain electrode of the sixth PMOS tube is connected with the drain electrode of the fifth NMOS tube; the grid electrode of the fifth NMOS tube is connected with the first end of the second capacitor, and the source electrode of the fifth NMOS tube is grounded; the drain electrodes of the sixth PMOS tube and the fifth NMOS tube output the second delay signal;

the control ends of the fifth switch, the sixth switch, the seventh switch and the eighth switch are respectively connected with a synchronous signal and an inverted signal of the input signal, the fifth switch and the seventh switch are switched on when the input signal is at a low level, and the sixth switch and the eighth switch are switched on when the input signal is at a high level.

More optionally, the filter circuit for suppressing noise interference further includes an output module, where the output module is connected to the output ends of the first delay module and the second delay module, and latches and outputs the first delay signal and the second delay signal.

More optionally, the output module comprises an RS latch.

More optionally, the filter circuit for suppressing noise interference further includes an input module, where the input module receives the input signal and is configured to generate a synchronization signal and an inversion signal of the input signal.

More optionally, the input module includes a first inverter and a second inverter connected in series.

To achieve the above and other related objects, the present invention also provides a micro control system, comprising at least:

microcontroller and the above-mentioned filter circuit which inhibits the noise interference;

the filter circuit for suppressing noise interference is connected to the input end of the microcontroller, and is used for suppressing interference of signals entering the microcontroller.

As described above, the filter circuit and the micro control system for suppressing noise interference according to the present invention have the following advantages:

1. the filter circuit for inhibiting noise interference and the micro-control system utilize the reference current to charge and discharge the capacitor, realize time-delay filtering, ensure the noise on a filtering signal effectively and have good inhibiting effect on power supply noise.

2. The filter circuit for inhibiting noise interference and the micro-control system utilize the symmetrical circuit to generate positive and negative signal delay, and ensure the stability of output signals.

3. The filter circuit for inhibiting noise interference and the micro control system output the positive and negative delay signals through latching, thereby further improving the stability of the output signals.

Drawings

Fig. 1 shows a schematic diagram of a principle of a signal being interfered on a transmission path.

Fig. 2 shows a schematic diagram of the principle of signal interference by a power supply.

Fig. 3 is a schematic diagram of a filter circuit for suppressing noise interference according to the present invention.

FIG. 4 is a schematic diagram of the micro control system of the present invention.

Description of the element reference numerals

1 filter circuit for suppressing noise interference

11 biasing module

12 first time delay module

13 second delay module

14 input module

15 output module

2 microcontroller

Detailed Description

The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.

Please refer to fig. 3-4. It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the components related to the present invention are only shown in the drawings rather than drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of the components in actual implementation may be changed freely, and the layout of the components may be more complicated.

Example one

As shown in fig. 3, the present embodiment provides a filter circuit 1 for suppressing noise interference, where the filter circuit 1 for suppressing noise interference includes:

the device comprises a bias module 11, a first delay module 12 and a second delay module 13.

As shown in fig. 3, the bias module 11 generates a bias signal.

In particular, the biasing module 11 receives a reference current I_biasThe reference current I is measured_biasGenerating a first bias voltage V after mirroring_bpAnd a second bias voltage V_bn。

More specifically, in the present embodiment, the bias module 11 includes a first PMOS transistor MP1, a second PMOS transistor MP2, and a first NMOS transistor MN 1. The drain electrode of the first PMOS tube MP1 is connected with the reference current I_bias(ii) a The grid electrode of the first PMOS pipe MP1 is connected with the drain electrode, and the first bias voltage V is output_bp(ii) a The source of the first PMOS transistor MP1 is connected to the power supply voltage VDD. The source electrode of the second PMOS pipe MP2 is connected with the power supply voltage VDD; the grid electrode of the second PMOS pipe MP2 is connected with the first bias voltage V_bp(ii) a The drain electrode of the second PMOS tube MP2 is connected with the drain electrode of the first NMOS tube MN 1. The grid electrode and the drain electrode of the first NMOS transistor MN1 are connected and output the second bias voltage V_bn(ii) a The source electrode of the first NMOS transistor MN1 is grounded VSS.

It should be noted that the circuit structure of the bias module 11 includes, but is not limited to, the manner listed in this embodiment, and any circuit structure capable of obtaining a bias signal is suitable for the present invention, which is not described herein again.

As shown in fig. 3, as an implementation manner of this embodiment, the filter circuit 1 for suppressing noise interference further includes an input module 14, where the input module 14 receives an input signal V_inFor generating said input signal V_inOf the synchronization signal V_{in_b}And a reverse signal

As an example, the input module 14 includes a first inverter INV1 and a second inverter INV2 connected in series; the first inverter INV1 receives the input signal V_inOutputting the input signal V_inIs a reverse signal of

The second inverter INV2 receives the input signal V_inIs a reverse signal of

Outputting the input signal V_inOf the synchronization signal V_{in_b}. In practical use, any of them may be based on the input signal V_inObtaining said input signal V_inOf the synchronization signal V_{in_b}And a reverse signal

The circuit structures described above are all suitable for the present invention, and are not repeated herein.

In addition, the input signal V_inOf the synchronization signal V_{in_b}May be said input signal V_inIn itself, the input signal V may be_inThe output signals after passing through any even level of inverters; the input signal V_inIs a reverse signal of

May be said input signal V_inThe output signal after passing through any odd-numbered stage inverter is not limited in this embodiment.

As shown in fig. 3, the first delay module 12 is connected to the bias module 11 and receives an input signal V_inOf the synchronization signal V_{in_b}And a reverse signal

For generating and said input signal V_inEquidirectional first delay signal V_{out_R}。

Specifically, the first delay module 12 includes a first switch SW1, a second switch SW2, a third switch SW3, a fourth switch SW4, a second NMOS transistor MN2, a third NMOS transistor MN3, a first capacitor C1, a third PMOS transistor MP3, and a fourth PMOS transistor MP 4. One end of the first switch SW1 is connected to the power voltage VDD, and the other end is connected to the gate of the third PMOS transistor MP 3. One end of the second switch SW2 is connected to the first bias voltage V_bpAnd the other end of the third PMOS tube MP3 is connected with the grid electrode of the third PMOS tube MP 3. One end of the third switch SW3 is connected to the second bias voltage V_bnAnd the other end of the second NMOS tube MN2 is connected with the grid electrode of the second NMOS tube MN 2. One end of the fourth switch SW4 is grounded VSS, and the other end is connected to the gate of the second NMOS transistor MN 2. The source electrode of the third PMOS transistor MP3 is connected to the power supply voltage VDD; the drain electrode of the third PMOS pipe MP3 is connected with the drain electrode of the second NMOS pipe MN 2; the source electrode of the second NMOS transistor MN2 is grounded VSS. The first end of the first capacitor C1 is connected to the drains of the third PMOS transistor MP3 and the second NMOS transistor MN2, and the second end is grounded VSS. The source electrode of the fourth PMOS pipe MP4 is connected with the power supply voltage VDD; the grid electrode of the fourth PMOS pipe MP4 is connected with the first bias voltage V_bp(ii) a The drain electrode of the fourth PMOS pipe MP4 is connected with the drain electrode of the third NMOS pipe MN 3; the gate of the third NMOS transistor MN3 is connected to the first end of the first capacitor C1; the source electrode of the third NMOS transistor MN3 is grounded VSS; the drains of the fourth PMOS transistor MP4 and the third NMOS transistor MN3 output the first delay signal V_{out_R}。

The first switch SW1 and the second switch SW1Control ends of the second switch SW2, the third switch SW3 and the fourth switch SW4 are respectively connected with the input signal V_inOf the synchronization signal V_{in_b}And a reverse signal

The first switch SW1 and the third switch SW3 are used for receiving the input signal V_inIs turned on when it is high, the second switch SW2 and the fourth switch SW4 are turned on when the input signal V is high_inAnd is turned on when the voltage is low. For example, in this embodiment, the first switch SW1, the second switch SW2, the third switch SW3 and the fourth switch SW4 are implemented by NMOS switch tubes, and the control terminal of the first switch SW1 is connected to the input signal V_inOf the synchronization signal V_{in_b}A control terminal of the second switch SW2 is connected to the input signal V_inIs a reverse signal of

The control end of the third switch SW3 is connected with the input signal V_inOf the synchronization signal V_{in_b}The control end of the fourth switch SW4 is connected with the input signal V_inIs a reverse signal of

As shown in fig. 3, the second delay module 13 receives the input signal V_inOf the synchronization signal V_{in_b}And a reverse signal

For generating and said input signal V_inInverted second delay signal V_{out_S}。

Specifically, the second delay module 13 is symmetrical to the first delay module 12. The second delay module 13 includes a fifth switch SW5, a sixth switch SW6, a seventh switch SW7, an eighth switch SW8, a fourth NMOS transistor MN4, a fifth NMOS transistor MN5, a second capacitor C2, a fifth PMOS transistor MP5, and a fifth PMOS transistor MP5Six PMOS transistors MP 6. One end of the fifth switch SW5 is connected to the power voltage VDD, and the other end is connected to the gate of the fifth PMOS transistor MP 5. One end of the sixth switch SW6 is connected to the first bias voltage V_bpAnd the other end of the second PMOS tube MP5 is connected with the grid electrode of the fifth PMOS tube MP 5. One end of the seventh switch SW7 is connected to the second bias voltage V_bnAnd the other end of the second NMOS transistor MN4 is connected with the grid electrode of the fourth NMOS transistor MN 4. One end of the eighth switch SW8 is grounded VSS, and the other end is connected to the gate of the fourth NMOS transistor MN 4. The source electrode of the fifth PMOS pipe MP5 is connected with the power supply voltage VDD; the drain electrode of the fifth PMOS pipe MP5 is connected with the drain electrode of the fourth NMOS pipe MN 4; the source electrode of the fourth NMOS transistor MN4 is grounded VSS; a first end of the second capacitor C2 is connected to the drains of the fifth PMOS transistor MP5 and the fourth NMOS transistor MN4, and a second end thereof is grounded to VSS. The source electrode of the sixth PMOS transistor MP6 is connected to the power supply voltage VDD; the grid electrode of the sixth PMOS pipe MP6 is connected with the first bias voltage V_bp(ii) a The drain electrode of the sixth PMOS tube MP6 is connected with the drain electrode of the fifth NMOS tube MN 5; the gate of the fifth NMOS transistor MN5 is connected to the first end of the second capacitor C2; the source electrode of the fifth NMOS transistor MN5 is grounded VSS; the drains of the sixth PMOS transistor MP6 and the fifth NMOS transistor MN5 output the second delay signal V_{out_S}。

Similarly, the control terminals of the fifth switch SW5, the sixth switch SW6, the seventh switch SW7 and the eighth switch SW8 are respectively connected to the input signal V_inOf the synchronization signal V_{in_b}And a reverse signal

The fifth switch SW5 and the seventh switch SW7 are in the input signal V_inIs turned on when it is low, the sixth switch SW6 and the eighth switch SW8 are turned on when the input signal V is_inAnd is turned on when it is at a high level. For example, in this embodiment, the fifth switch SW5, the sixth switch SW6, the seventh switch SW7 and the eighth switch SW8 are implemented by NMOS switching tubes, and the control end of the fifth switch SW5 is connected to the input signal V_inIs a reverse signal of

The control end of the sixth switch SW6 is connected with the input signal V_inOf the synchronization signal V_{in_b}A control terminal of the seventh switch SW7 is connected to the input signal V_inIs a reverse signal of

The control end of the eighth switch SW8 is connected with the input signal V_inOf the synchronization signal V_{in_b}。

As shown in fig. 3, as an implementation manner of this embodiment, the filter circuit 1 for suppressing noise interference further includes an output module 15, where the output module 15 is connected to output ends of the first delay module 12 and the second delay module 13, and is used for processing the first delay signal V_{out_R}And said second delay signal V_{out_S}And latching and outputting. As an example, in the present embodiment, the output module 15 includes an RS latch. The RS latch is composed of a first NAND gate NAND1 and a second NAND gate NAND 2; a first input end of the first NAND gate NAND1 is connected with the first delay signal V_{out_R}(ii) a A second input terminal of the first NAND gate NAND1 is connected to the output terminal of the second NAND gate NAND2 and serves as the output terminal of the output module 15; a first input end of the second NAND gate NAND2 is connected with an output end of the first NAND gate NAND 1; a second input end of the second NAND gate NAND2 is connected with the second delay signal V_{out_S}。

The filter circuit 1 for suppressing noise interference operates according to the following principle:

input signal V_inThrough an input module 14, a signal V is generated and input_inSynchronized V_{in_b}And input signal V_inIn the reverse direction

Reference current I_biasThe first bias current flows through the first PMOS transistor MP1, the second PMOS transistor MP2 and the first NMOS transistor MN1 through the current mirror to generate the first bias currentPressure V_bpAnd a second bias voltage V_bnWherein the first bias voltage V_bpMirror the current to the PMOS devices of the first delay module 12 and the second delay module 13, and a second bias voltage V_bnThe current is mirrored to the NMOS devices of the first delay block 12 and the second delay block 13.

A first bias voltage V_bpThe third PMOS transistor MP3 and the fourth PMOS transistor MP4 mirror the reference current I_bias(or with a reference current I_biasHaving a set proportional relationship), a second bias voltage V_bnThe Current (Current Sink) of the first NMOS transistor MN1 is mirrored by the second NMOS transistor MN 2. Each switch is used for switching on and off the first bias voltage V_bpAnd a second bias voltage V_bn. The switch is turned on when the control voltage of the switch is high, and is turned off when the control voltage is low.

When inputting signal V_inAt high voltage, the input signal V_inOf the synchronization signal V_{in_b}Also at high voltage, input signal V_inIs a reverse signal of

Is at a low voltage. At this time, the gate of the third PMOS transistor MP3 is biased by the first bias voltage V_bpAnd is disconnected and connected to the power voltage VDD, and the third PMOS transistor MP3 is in an off state. The gate of the second NMOS transistor MN2 and a second bias voltage V_bnWhen the second NMOS transistor MN2 is turned on, a mirror current flows through the second NMOS transistor MN2, the first capacitor C1 discharges to zero voltage through the second NMOS transistor MN2, and the discharge time of the first capacitor C1 is t ═ V_th1·C1/I_biasWherein V is_th1Is the threshold of the third NMOS transistor MN 3. When the voltage on the first capacitor C1 is reduced to be less than the threshold value V of the third NMOS transistor MN3_th1When the third NMOS transistor MN3 is turned off, the first delay signal V is generated_{out_R}And outputting the high voltage.

When inputting signal V_inAt low voltage, the input signal V_inOf the synchronization signal V_{in_b}Also at low voltage, input signal V_inIs a reverse signal of

Is a high voltage. At this time, the gate of the third PMOS transistor MP3 is biased by the first bias voltage V_bpAnd conducting. The gate of the second NMOS transistor MN2 and a second bias voltage V_bnThe NMOS transistor MN2 is turned off, and the gate of the NMOS transistor MN2 is connected to ground VSS. The third PMOS transistor MP3 flows the mirror current to charge the first capacitor C1, and the charging time of the first capacitor C1 is t ═ V_th1·C1/I_bias. When the voltage on the first capacitor C1 is charged to be greater than the threshold value V of the third NMOS transistor MN3_th1When the third NMOS transistor MN3 is turned on, the first delay signal V_{out_R}And outputting the low voltage.

A first bias voltage V_bpThe fifth PMOS transistor MP5 and the sixth PMOS transistor MP6 mirror the reference current I_bias(or with a reference current I_biasHaving a set proportional relationship), a second bias voltage V_bnThe Current (Current Sink) of the first NMOS transistor MN1 is mirrored by the fourth NMOS transistor MN 4.

Is at a low voltage. At this time, the gate of the fifth PMOS transistor MP5 is biased by the first bias voltage V_bpAnd conducting. The gate of the fourth NMOS transistor MN4 and a second bias voltage V_bnAnd the gate of the fourth NMOS transistor MN4 is connected to the ground VSS, and the fourth NMOS transistor MN4 is in an off state. The fifth PMOS transistor MP5 flows the mirror current to charge the second capacitor C2, and the charging time of the second capacitor C2 is t ═ V_th2·C2/I_biasWherein V is_th2Is the threshold of the fifth NMOS transistor MN 5. When the voltage on the second capacitor C2 is charged to be greater than the threshold value V of the fifth NMOS transistor MN5_th2When the fifth NMOS transistor MN5 is turned on, the second delay signal V_{out_S}And outputting the low voltage.

Is a high voltage. At this time, the gate of the fifth PMOS transistor MP5 is biased by the first bias voltage V_bpAnd is disconnected and connected to the power voltage VDD, and the fifth PMOS transistor MP5 is in an off state. The gate of the fourth NMOS transistor MN4 and a second bias voltage V_bnWhen the second capacitor C2 is turned on, the mirror current flows through the fourth NMOS transistor MN4, the second capacitor C2 discharges to zero voltage through the fourth NMOS transistor MN4, and the discharge time t of the second capacitor C2 is V ═ V_th2·C2/I_bias. When the voltage on the capacitor second C2 is reduced to be less than the threshold value V of the fifth NMOS transistor MN5_th5When the fifth NMOS transistor MN5 is turned off, the second delay signal V is generated_{out_S}And outputting the high voltage.

Delayed first delay signal V_{out_R}And a second delay signal V_{out_S}Latch with latch and then output voltage V_outAnd the data is provided for a processing module at the next stage. At a first delay signal V_{out_R}Or a second delay signal V_{out_S}When the state changes, the latch can ensure the output voltage V_outNot influenced, further promote the stability of output signal.

The filter circuit for inhibiting noise interference utilizes the reference current to charge and discharge the capacitor, realizes time-delay filtering, ensures that noise on a signal can be effectively filtered, and has good inhibiting effect on power supply noise; positive and negative signal delay is generated by using a symmetrical circuit, so that the stability of an output signal is ensured; the positive and negative delay signals are latched and output, and the stability of the output signals is further improved.

Example two

As shown in fig. 4, the present embodiment provides a micro control system, which includes:

microcontroller 2 and filter circuit 1 that suppresses noise interference.

As shown in fig. 4, the filter circuit 1 for suppressing noise interference is connected to an input end of the microcontroller 2, and performs interference suppression on a signal entering the microcontroller 2.

Specifically, the structure and principle of the filter circuit 1 for suppressing noise interference are as described in the first embodiment, and are not repeated here.

Specifically, the Microcontroller 2 (MCU) is used for controlling different applications, which is not described herein again.

In summary, the present invention provides a filter circuit and a micro control system for suppressing noise interference, including: a bias module for generating a bias signal; the first time delay module is connected with the bias module, receives a synchronous signal and a reverse signal of an input signal and is used for generating a first time delay signal in the same direction as the input signal; and the second time delay module is used for receiving the synchronous signal and the reverse signal of the input signal and generating a second time delay signal reverse to the input signal. And the filter circuit for suppressing noise interference is connected to the input end of the microcontroller, and is used for suppressing the interference of the signal entering the microcontroller. The filter circuit for inhibiting noise interference and the micro control system ensure that noise on signals can be effectively filtered, and have good inhibiting effect on power supply noise; the output signal is stable. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.

The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.

Claims

1. A filter circuit for suppressing noise interference, the filter circuit for suppressing noise interference comprising at least:

the bias module receives a reference current, and generates a first bias voltage and a second bias voltage after mirroring the reference current;

the first time delay module is connected with the bias module, receives a synchronous signal and a reverse signal of an input signal and is used for generating a first time delay signal in the same direction as the input signal; the first delay module comprises a first switch, a second switch, a third switch, a fourth switch, a second NMOS (N-channel metal oxide semiconductor) tube, a third NMOS tube, a first capacitor, a third PMOS tube and a fourth PMOS tube; one end of the first switch is connected with a power supply voltage, and the other end of the first switch is connected with the grid electrode of the third PMOS tube; one end of the second switch is connected with the first bias voltage, and the other end of the second switch is connected with the grid electrode of the third PMOS tube; one end of the third switch is connected with the second bias voltage, and the other end of the third switch is connected with the grid electrode of the second NMOS tube; one end of the fourth switch is grounded, and the other end of the fourth switch is connected with the grid electrode of the second NMOS tube; the source electrode of the third PMOS tube is connected with the power supply voltage, and the drain electrode of the third PMOS tube is connected with the drain electrode of the second NMOS tube; the source electrode of the second NMOS tube is grounded; the first end of the first capacitor is connected with the drain electrodes of the third PMOS tube and the second NMOS tube, and the second end of the first capacitor is grounded; the source electrode of the fourth PMOS tube is connected with the power supply voltage, the grid electrode of the fourth PMOS tube is connected with the first bias voltage, and the drain electrode of the fourth PMOS tube is connected with the drain electrode of the third NMOS tube; the grid electrode of the third NMOS tube is connected with the first end of the first capacitor, and the source electrode of the third NMOS tube is grounded; the drain electrodes of the fourth PMOS tube and the third NMOS tube output the first delay signal;

the second time delay module is used for receiving a synchronous signal and an inverse signal of the input signal and generating a second time delay signal which is inverse to the input signal; the second delay module comprises a fifth switch, a sixth switch, a seventh switch, an eighth switch, a fourth NMOS tube, a fifth NMOS tube, a second capacitor, a fifth PMOS tube and a sixth PMOS tube; one end of the fifth switch is connected with a power supply voltage, and the other end of the fifth switch is connected with the grid electrode of the fifth PMOS tube; one end of the sixth switch is connected with the first bias voltage, and the other end of the sixth switch is connected with the grid electrode of the fifth PMOS tube; one end of the seventh switch is connected with the second bias voltage, and the other end of the seventh switch is connected with the grid electrode of the fourth NMOS tube; one end of the eighth switch is grounded, and the other end of the eighth switch is connected with the grid electrode of the fourth NMOS tube; the source electrode of the fifth PMOS tube is connected with the power supply voltage, and the drain electrode of the fifth PMOS tube is connected with the drain electrode of the fourth NMOS tube; the source electrode of the fourth NMOS tube is grounded; the first end of the second capacitor is connected with the drain electrodes of the fifth PMOS tube and the fourth NMOS tube, and the second end of the second capacitor is grounded; the source electrode of the sixth PMOS tube is connected with the power supply voltage, the grid electrode of the sixth PMOS tube is connected with the first bias voltage, and the drain electrode of the sixth PMOS tube is connected with the drain electrode of the fifth NMOS tube; the grid electrode of the fifth NMOS tube is connected with the first end of the second capacitor, and the source electrode of the fifth NMOS tube is grounded; the drain electrodes of the sixth PMOS tube and the fifth NMOS tube output the second delay signal;

the control ends of the first, second, third, fourth, fifth, sixth, seventh and eighth switches are respectively connected to the synchronous signal and the inverted signal of the input signal, the first switch, the third switch, the sixth switch and the eighth switch are turned on when the input signal is at a high level, and the second switch, the fourth switch, the fifth switch and the seventh switch are turned on when the input signal is at a low level.

2. The filter circuit for suppressing noise interference according to claim 1, wherein: the bias module comprises a first PMOS tube, a second PMOS tube and a first NMOS tube; the drain electrode of the first PMOS tube is connected with the reference current, the grid electrode of the first PMOS tube is connected with the drain electrode of the first PMOS tube and outputs a first bias voltage, and the source electrode of the first PMOS tube is connected with a power supply voltage; the source electrode of the second PMOS tube is connected with the power supply voltage, the grid electrode of the second PMOS tube is connected with the first bias voltage, and the drain electrode of the second PMOS tube is connected with the drain electrode of the first NMOS tube; and the grid electrode of the first NMOS tube is connected with the drain electrode and outputs a second bias voltage, and the source electrode is grounded.

3. The filter circuit for suppressing noise interference according to any one of claims 1 to 2, wherein: the filter circuit for suppressing noise interference further comprises an output module, wherein the output module is connected with the output ends of the first delay module and the second delay module, and is used for latching and outputting the first delay signal and the second delay signal.

4. The filter circuit for suppressing noise interference according to claim 3, wherein: the output module includes an RS latch.

5. The filter circuit for suppressing noise interference according to claim 3, wherein: the filter circuit for suppressing noise interference further comprises an input module, wherein the input module receives the input signal and is used for generating a synchronous signal and a reverse signal of the input signal.

6. The filter circuit for suppressing noise interference according to claim 5, wherein: the input module comprises a first reverser and a second reverser which are connected in series.

7. A micro-control system, characterized in that it comprises at least:

a microcontroller and a filter circuit for suppressing noise interference according to any one of claims 1 to 6;