CN103647545A - Delay unit circuit - Google Patents
Delay unit circuit Download PDFInfo
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- CN103647545A CN103647545A CN201310633168.1A CN201310633168A CN103647545A CN 103647545 A CN103647545 A CN 103647545A CN 201310633168 A CN201310633168 A CN 201310633168A CN 103647545 A CN103647545 A CN 103647545A
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Abstract
The invention relates to a delay unit circuit. The circuit comprises signal input and output ports, first and second phase inverters, a feedback control module, a node 1, a power supply, a capacitor and a resistor. The input stage of the first phase inverter is connected with the signal input port, the output stage is connected with the node, and the two ends of the intermediate stage are respectively connected with the power supply and the ground. The input stage of the second phase inverter is connected with the node, the output stage is connected with the signal output port, and the two ends of the intermediate stage are respectively connected with the power supply and the ground. The input stage of the feedback control module is connected with the signal input port, the output stage is connected with a signal output end, and the two ends of the intermediate stage are respectively connected with the node and the ground. The capacitor is connected between the node and the ground or between the node and the power supply. After an input-end signal changes from low to high, the signal is pulled down through the first phase inverter, the capacitor discharges electricity to the ground through the resistor to enable the node level to gradually change from high to low, output of an output-end signal is delayed, and until the node voltage is lower than the flip level, the level of the signal output end is immediately flipped to change from low to high, and the feedback module is switched on and quickly pulls down the node level.
Description
Technical field
The invention belongs to integrated circuit (IC) design field, be specifically related to a kind of delay unit circuit.
Background technology
Delay unit circuit, is widely used in various integrated circuits.Delay cell is transient overvoltage and the voltage jump in control circuit effectively, and circuit is played to cushioning effect, and protection device safe operation.Some time, shorter delay cell was not used digital dock timing, and use resistance capacitance to form, postponed, because resistance capacitance is easily subject to noise jamming, caused output abnormality.
The delay unit circuit that for example Fig. 1 is prior art.The first inverter comprises PMOS pipe (MP1) and a NMOS(MN1) pipe, hereinafter to be referred as MP1, MN1, the second inverter comprises the 2nd PMOS pipe (MP2) and the 2nd NMOS(MN2) pipe, hereinafter to be referred as MP2, MN2.IN is digital signal input end mouth, and OUT is for postponing digital signal output end mouth, when digital signal input end mouth input signal uprises level from low level, MP1 cut-off, MN1 opens, and C1 discharges to GND by current-limiting resistance R1, and Fig. 2 is the delay unit circuit oscillogram of prior art.When node node1 level drops to lower than by MN2, during inverter trigging signal that MP2 forms, the upset of digital signal output end mouth level uprises from low.Now digital signal input end mouth signal rising edge has delay between digital signal output end mouth signal rising edge, has postponed the output of digital signal output end mouth signal.When larger noise appears in power supply, node node1 level is interfered near inverter trigging signal, causes digital signal output end mouth signal to occur repeatedly upset, further has influence on output signal low and high level unstable.Fig. 3 is the delay unit circuit oscillogram that is subject to noise jamming.
Cause the basic reason of the problems referred to above to be that node node1 level is unstable near inverter trigging signal.Increasing feedback control module, realize capacitance voltage as early as possible away from the trigging signal of rear class signal amplification circuit, is the effective way addressing the above problem.
Summary of the invention
The object of the invention is for the deficiencies in the prior art, on the basis of delay unit circuit, increase a feedback control module, thereby improve delay unit circuit antijamming capability.
For achieving the above object, the present invention has designed a kind of method that delay unit circuit drive feedback is controlled, and described delay unit circuit comprises: digital signal input end mouth, digital signal output end mouth, the first inverter, the second inverter, feedback control module, node node1, power supply and electric capacity;
The input stage of described the first inverter is connected with digital signal input end mouth, and output stage is connected with node node1;
The input stage of described the second inverter is connected with node node1, and output stage is connected with digital signal output end mouth;
The input stage of the output stage of described the first inverter and described the second inverter is connected by described node node1;
Described feedback control module, two ends input stage is connected with signal input port, signal output port respectively, two links respectively with described node node1, be connected, when described digital signal input end mouth and described digital signal output end mouth are the first level simultaneously, described node node1 is connected with ground, while being the first level when described digital signal input end mouth is different with described digital signal output end mouth, described node node1 and ground are disconnected;
Described electric capacity, is connected between node node1 and ground;
Preferably, described the first inverter comprises resistance, PMOS pipe (MP1) and a NMOS(MN1) pipe;
A NMOS substrate of described MN1 and source electrode join and ground connection (connecing minimum level); The substrate of described MP1 and source electrode join and connect power supply (connecing maximum level), described MN1 grid and described MP1 gate interconnection as the input stage of described the first inverter, the drain electrode of described MN1 is connected with the drain electrode of described MP1 via described resistance, and the drain electrode of described MP1 is connected in described node node1 as the output stage of described the first inverter;
Described the second inverter comprises the 2nd PMOS pipe (MP2) and the 2nd NMOS(MN2) pipe; The substrate of the pipe of described MP2 and source electrode join and connect power supply (connecing maximum level), described the 2nd NMOS substrate and source electrode join and ground connection (connecing minimum level), described MN2 grid and described MP2 gate interconnection are also connected in described node node1 as the input stage of described the first inverter, and the drain electrode of described MN2 is connected as described digital signal output end with the drain electrode of described MP2;
When the input signal of described digital signal input end mouth is from low level uprises level, described MP1 cut-off, described MN1, MN4 conducting, when described node node1 level is during lower than described the second inverter trigging signal, described MP2 conducting, described MN2 cut-off, described digital signal output end mouth is pulled up to described supply voltage high level, described MN3 conducting, described feedback module starts the described deferred telegram discharge capacitor process of controlling.
Preferably, described feedback control module comprises the 3rd NMOS pipe (MN3), the 4th NMOS pipe (MN4), hereinafter to be referred as MN3, MN4, described digital signal input end drives the grid of described the 4th NMOS pipe, described digital signal output end drives the grid of described the 3rd NMOS pipe, the drain electrode of described the 3rd NMOS pipe is connected in described node node1, and the source electrode of described the 3rd NMOS pipe is connected with the drain electrode of described the 4th NMOS pipe, the source ground of described the 4th NMOS pipe;
When described digital signal input end mouth, described digital signal output end mouth are all high level, all conductings of described MN3, MN4, described feedback control module is opened, and drags down described node node1 level.
Preferably, described electric capacity is connected between described node node1 and ground, and when described node node1 level trend step-down, described electric capacity discharges immediately, makes described signal output delay.
When described digital signal input end mouth input signal is from low level uprises level, described signal is pulled to low level through described the first inverter, but described electric capacity discharges to ground by current-limiting resistance, make described node node1 level gradually by high step-down, postponed the described signal output of described digital signal output end mouth, until described node node1 level is during lower than described the second inverter trigging signal, described node node1 place signal uprises from low immediately through described the second inverter, described digital signal output end mouth level overturns at once and uprises from low, when now described digital signal input end mouth and described digital signal output end mouth are the first level simultaneously, described feedback control module is connected described node node1 with ground, the strong pull-down path that described feedback control module forms drags down rapidly described node node1 level.
The invention has the advantages that from digital signal output end mouth negate feedback signal, drive additional passageway, after the upset of digital signal output end mouth inhibit signal, accelerate at once the decline of node node1 signal, make node node1 signal as early as possible away from inverter trigging signal, thereby improve delay cell antijamming capability.
Accompanying drawing explanation
Fig. 1 is the delay unit circuit of prior art;
Fig. 2 is the analog waveform of the delay unit circuit of prior art;
Fig. 3 is the waveform that the delay unit circuit of prior art is subject to noise jamming;
Fig. 4 is the delay unit circuit of increase feedback control module disclosed by the invention;
Fig. 5 is the delay unit circuit waveform of increase feedback control module disclosed by the invention.
Embodiment
Clearer for what the technical scheme of the embodiment of the present invention and advantage were expressed, below by drawings and Examples, technical scheme of the present invention is described in further detail.
Fig. 4 is the schematic diagram of delay unit circuit of the present invention, as shown in the figure, this delay unit circuit specifically comprises: digital signal input end mouth (IN), digital signal output end mouth (OUT), the first inverter (101), the second inverter (102), feedback control module (103), node node1, power supply (VDD), electric capacity (C1) and resistance (R1).
In the embodiment of the present invention, the input stage of the first inverter (101) is connected with digital signal input end mouth IN, and output stage is connected with node node1, intergrade two ends and power vd D, be connected; The input stage of the second inverter (102) is connected with node node1, and output stage is connected with digital signal output end mouth OUT, intergrade two ends and power vd D, be connected; The input stage of the output stage of the first inverter (101) and described the second inverter (102) is connected by described node node1; Described feedback control module (103), two ends input stage is connected with signal input port IN, signal output port OUT respectively, intergrade two ends and node node1, be connected; Described electric capacity, is connected between node node1 and ground.
Further, operation principle is as follows:
The first inverter (101) is managed (MP1) and a NMOS(MN1 by a PMOS) pipe form, its effect is for the input signal of digital input port is realized to not gate logic function, when input signal is high level, the first inverter is pulled to low level, when input signal is low level, the first inverter is pulled to high level.
The second inverter (102) is managed (MP2) and the 2nd NMOS(MN2 by the 2nd PMOS) pipe form, its effect is for the signal at node node1 place is realized to not gate logic function, when the signal at node node1 place is high level, the second inverter is pulled to low level, when the signal at node node1 place is low level, the second inverter is pulled to high level.
Feedback control module (103) is by MN3, and two NMOS pipes of MN4 form, and its effect is to be interfered near inverter trigging signal for fear of node node1 signal.When once node node1 level is lower than inverter trigging signal, feedback control module starts, the electric discharge process of speed-up capacitor, makes the level at node node1 place be fed the strong pull-down path that control module forms and drags down rapidly, in a short period of time away from inverter trigging signal.When digital signal input end mouth and digital signal output end mouth are high level simultaneously, node node1 is connected with ground, while being high level when digital signal input end mouth is different with digital signal output end mouth, by node node1 and ground disconnection.
When digital signal input end mouth input signal is from low level uprises level, the first inverter is realized not gate logic function and is pulled to low level, now digital signal output end mouth is still low level, electric capacity discharges to GND by current-limiting resistance R1, make node node1 level gradually by high step-down, once work as node node1 level lower than the second inverter trigging signal, digital signal output end mouth level overturns at once and is pulled up to supply voltage high level, feedback control module starts, MN3, the strong pull-down path that MN4 forms accelerates to postpone the electric discharge process of electric capacity, node node1 level is dragged down rapidly, make node node1 signal within very short time away from inverter trigging signal, thereby improve delay cell antijamming capability.
As shown in Figure 4, concrete, the first inverter (101) comprises PMOS pipe (MP1) and a NMOS(MN1) pipe.
In the first inverter 101: PMOS pipe (MP1) and a NMOS(MN1) pipe is concatenated and forms the first inverter according to mutual symmetry form, and the substrate of a NMOS and source electrode join and ground connection (connecing minimum level); The substrate of the one PMOS pipe and source electrode join and connect power supply (connecing maximum level), MN1 grid and MP1 gate interconnection as the input stage of the first inverter, the drain electrode of MN1 is connected with the drain electrode of MP1 via resistance, and the drain electrode of MP1 is connected in described node node1 as the output stage of the first inverter.
In the second inverter 102, MP2 and MN2 couple together and form the second inverter according to mutual symmetry form, the substrate of the 2nd PMOS pipe and source electrode join and connect power supply (connecing maximum level), the 2nd NMOS substrate and source electrode join and ground connection (connecing minimum level), MN2 grid and MP2 gate interconnection are also connected in node node1 as the input stage of the first inverter, and the drain electrode of MN2 is connected as digital signal output end with the drain electrode of MP2.
In feedback control module 103, MN3, two NMOS pipes of MN4 form feedback control module, digital signal input end mouth drives the grid of the 4th NMOS pipe, digital signal output end mouth drives the grid of the 3rd NMOS pipe, the drain electrode of the 3rd NMOS pipe is connected in node node1, and the source electrode of the 3rd NMOS pipe is connected with the drain electrode of described the 4th NMOS pipe, the source ground of described the 4th NMOS pipe; Electric discharge process for speed-up capacitor, realizes delay unit circuit antijamming capability.
When digital signal input end mouth input signal is from low level uprises level, MP1 cut-off, MN1, MN4 conducting, the first inverter is realized not gate logic function and is pulled to low level, now digital signal output end mouth is still low level, MN3 remain off, on node node1, draw path to only have R1, electric capacity discharges to GND by current-limiting resistance R1, make node node1 level gradually by high step-down, once work as node node1 level lower than the second inverter trigging signal, MP2 conducting, MN2 cut-off, digital signal output end mouth level overturns at once and is pulled up to supply voltage high level, MN3 conducting, feedback control module starts, MN3, the strong pull-down path that MN4 forms accelerates to postpone the electric discharge process of electric capacity, node node1 level is dragged down rapidly, make node node1 signal within very short time away from inverter trigging signal, thereby improve delay cell antijamming capability.
Fig. 5 is delay unit circuit IN of the present invention, OUT and node1 three's voltage and time relationship (v-t) oscillogram.As shown in Figure 5, when IN is low level, signal becomes high level through the first inverter, then through the second inverter, becomes again low level, and OUT is low level; When IN is from low level uprises level, signal becomes low level through the first inverter, due to capacitor discharge, make node1 level gradually by high step-down, until node1 level is during lower than inverter trigging signal, OUT level overturns at once and uprises from low, and now node1 level is dragged down rapidly.
The delay unit circuit of the FEEDBACK CONTROL that the embodiment of the present invention provides has solved in prior art the inverter unsettled problem of overturning, realized when signal delay is exported, prevent that node node1 is interfered near inverter trigging signal, avoid digital signal output end mouth signal to occur repeatedly upset, cause causing subsequent conditioning circuit operation irregularity, and the delay unit circuit of FEEDBACK CONTROL provided by the invention is simple in structure, reduce costs, compare existing scheme, improved antijamming capability.
Above-described embodiment; object of the present invention, technical scheme and beneficial effect are further described; institute is understood that; the foregoing is only the specific embodiment of the present invention; the protection range being not intended to limit the present invention; within the spirit and principles in the present invention all, any modification of making, be equal to replacement, improvement etc., within all should being included in protection scope of the present invention.
Claims (5)
1. a delay unit circuit, is characterized in that, described delay unit circuit comprises: digital signal input end mouth, digital signal output end mouth, the first inverter, the second inverter, feedback control module, node node1, power supply and electric capacity;
The input stage of described the first inverter is connected with digital signal input end mouth, and output stage is connected with node node1;
The input stage of described the second inverter is connected with node node1, and output stage is connected with digital signal output end mouth;
The input stage of the output stage of described the first inverter and described the second inverter is connected by described node node1;
Described feedback control module, two ends input stage is connected with described digital signal input end mouth, described digital signal output end mouth respectively, two links respectively with described node node1, be connected, when described digital signal input end mouth and described digital signal output end mouth are the first level simultaneously, described node node1 is connected with ground, while being the first level when described digital signal input end mouth is different with described digital signal output end mouth, described node node1 and ground are disconnected;
Described electric capacity, is connected between described node node1 and ground.
2. delay unit circuit according to claim 1, is characterized in that, described the first inverter comprises resistance, a PMOS pipe and NMOS pipe;
The substrate of a described NMOS pipe and source electrode join and ground connection; The substrate of a described PMOS pipe and source electrode join and connect power supply, the gate interconnection of a described NMOS tube grid and a described PMOS pipe as the input stage of described the first inverter, the drain electrode of a described NMOS pipe is connected with the drain electrode of a described PMOS pipe via described resistance, and the drain electrode of a described PMOS pipe is connected in described node node1 as the output stage of described the first inverter;
Described the second inverter comprises the 2nd PMOS pipe and the 2nd NMOS pipe; The substrate of described the 2nd PMOS pipe and source electrode join and connect power supply, described the 2nd NMOS substrate and source electrode join and ground connection, the gate interconnection of described the 2nd NMOS tube grid and described the 2nd PMOS pipe is also connected in described node node1 as the input stage of described the first inverter, and the drain electrode of the drain electrode of described the 2nd NMOS pipe and described the 2nd PMOS pipe is connected as described digital signal output end;
Described the first level is high level;
When the input signal of described digital signal input end mouth is from low level uprises level, a described PMOS pipe cut-off, a described NMOS pipe conducting, when described node node1 level is during lower than described the second inverter trigging signal, described the 2nd PMOS pipe conducting, described the 2nd NMOS pipe cut-off, described digital signal output end mouth is pulled up to described supply voltage high level.
3. delay unit circuit according to claim 1, it is characterized in that, described feedback control module comprises the 3rd NMOS pipe, the 4th NMOS pipe, described digital signal input end drives the grid of described the 4th NMOS pipe, described digital signal output end drives the grid of described the 3rd NMOS pipe, the drain electrode of described the 3rd NMOS pipe is connected in described node node1, and the source electrode of described the 3rd NMOS pipe is connected with the drain electrode of described the 4th NMOS pipe, the source ground of described the 4th NMOS pipe;
When described digital signal input end mouth, described digital signal output end mouth are all high level, described the 3rd NMOS pipe, the 4th NMOS manage conductings, and described feedback control module is connected node node1 with ground, drag down described node node1 level.
4. delay unit circuit according to claim 1, is characterized in that, described electric capacity is connected between described node node1 and ground, and when described node node1 level trend step-down, described electric capacity discharges immediately, makes described signal output delay.
5. delay unit circuit according to claim 1, it is characterized in that, when described digital signal input end mouth input signal is from low level uprises level, described signal is pulled to low level through described the first inverter, but described electric capacity discharges to ground by current-limiting resistance, make described node node1 level gradually by high step-down, postponed the described signal output of described digital signal output end mouth, until described node node1 level is during just lower than described the second inverter trigging signal, described node node1 place signal uprises from low very soon through described the second inverter, described digital signal output end mouth level overturns very soon and uprises from low, when now described digital signal input end mouth and described digital signal output end mouth are the first level simultaneously, described feedback control module is connected described node node1 with ground, drag down described node node1 level, described the first level is high level.
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| CN201310633168.1A CN103647545A (en) | 2013-11-29 | 2013-11-29 | Delay unit circuit |
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| CN201310633168.1A CN103647545A (en) | 2013-11-29 | 2013-11-29 | Delay unit circuit |
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Cited By (15)
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|---|---|---|---|---|
| CN104378102A (en) * | 2014-11-21 | 2015-02-25 | 无锡中星微电子有限公司 | Low-power-consumption logic circuit |
| CN104393868A (en) * | 2014-12-22 | 2015-03-04 | 厦门福齐电子科技有限公司 | Input interface integrated circuit and input interface circuit thereof |
| CN107564449A (en) * | 2017-09-13 | 2018-01-09 | 昆山龙腾光电有限公司 | Gate driving circuit and display device |
| CN107800411A (en) * | 2017-10-19 | 2018-03-13 | 深圳市汇春科技股份有限公司 | A kind of delay circuit |
| CN111030647A (en) * | 2019-12-26 | 2020-04-17 | 普冉半导体（上海）有限公司 | Double-side delay circuit |
| CN111106822A (en) * | 2019-12-03 | 2020-05-05 | 上海集成电路研发中心有限公司 | Power supply power-on module |
| CN111124032A (en) * | 2019-12-20 | 2020-05-08 | 睿兴科技(南京)有限公司 | Filter circuit for suppressing noise interference and micro control system |
| CN113541450A (en) * | 2020-04-15 | 2021-10-22 | 芯好半导体(成都)有限公司 | Drive circuit, switch converter and integrated circuit |
| CN113972908A (en) * | 2021-12-24 | 2022-01-25 | 江苏长晶科技股份有限公司 | Low-power consumption control port capable of preventing misoperation |
| WO2022110696A1 (en) * | 2020-11-25 | 2022-06-02 | 长鑫存储技术有限公司 | Potential generation circuit, inverter, delay circuit, and logic gate circuit |
| CN115173837A (en) * | 2022-08-09 | 2022-10-11 | 无锡飞龙九霄微电子有限公司 | Circuit and device for generating high delay |
| US11528020B2 (en) | 2020-11-25 | 2022-12-13 | Changxin Memory Technologies, Inc. | Control circuit and delay circuit |
| US11550350B2 (en) | 2020-11-25 | 2023-01-10 | Changxin Memory Technologies, Inc. | Potential generating circuit, inverter, delay circuit, and logic gate circuit |
| US11681313B2 (en) | 2020-11-25 | 2023-06-20 | Changxin Memory Technologies, Inc. | Voltage generating circuit, inverter, delay circuit, and logic gate circuit |
| US11887652B2 (en) | 2020-11-25 | 2024-01-30 | Changxin Memory Technologies, Inc. | Control circuit and delay circuit |
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Cited By (19)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104378102A (en) * | 2014-11-21 | 2015-02-25 | 无锡中星微电子有限公司 | Low-power-consumption logic circuit |
| CN104393868A (en) * | 2014-12-22 | 2015-03-04 | 厦门福齐电子科技有限公司 | Input interface integrated circuit and input interface circuit thereof |
| CN107564449A (en) * | 2017-09-13 | 2018-01-09 | 昆山龙腾光电有限公司 | Gate driving circuit and display device |
| CN107800411A (en) * | 2017-10-19 | 2018-03-13 | 深圳市汇春科技股份有限公司 | A kind of delay circuit |
| CN111106822A (en) * | 2019-12-03 | 2020-05-05 | 上海集成电路研发中心有限公司 | Power supply power-on module |
| CN111106822B (en) * | 2019-12-03 | 2023-12-12 | 上海集成电路研发中心有限公司 | Power-on module |
| CN111124032B (en) * | 2019-12-20 | 2021-11-05 | 睿兴科技(南京)有限公司 | Filter circuit for suppressing noise interference and micro control system |
| CN111124032A (en) * | 2019-12-20 | 2020-05-08 | 睿兴科技(南京)有限公司 | Filter circuit for suppressing noise interference and micro control system |
| CN111030647A (en) * | 2019-12-26 | 2020-04-17 | 普冉半导体（上海）有限公司 | Double-side delay circuit |
| CN111030647B (en) * | 2019-12-26 | 2024-03-26 | 普冉半导体(上海)股份有限公司 | Double-sided delay circuit |
| CN113541450A (en) * | 2020-04-15 | 2021-10-22 | 芯好半导体(成都)有限公司 | Drive circuit, switch converter and integrated circuit |
| WO2022110696A1 (en) * | 2020-11-25 | 2022-06-02 | 长鑫存储技术有限公司 | Potential generation circuit, inverter, delay circuit, and logic gate circuit |
| US11528020B2 (en) | 2020-11-25 | 2022-12-13 | Changxin Memory Technologies, Inc. | Control circuit and delay circuit |
| US11550350B2 (en) | 2020-11-25 | 2023-01-10 | Changxin Memory Technologies, Inc. | Potential generating circuit, inverter, delay circuit, and logic gate circuit |
| US11681313B2 (en) | 2020-11-25 | 2023-06-20 | Changxin Memory Technologies, Inc. | Voltage generating circuit, inverter, delay circuit, and logic gate circuit |
| US11887652B2 (en) | 2020-11-25 | 2024-01-30 | Changxin Memory Technologies, Inc. | Control circuit and delay circuit |
| CN113972908A (en) * | 2021-12-24 | 2022-01-25 | 江苏长晶科技股份有限公司 | Low-power consumption control port capable of preventing misoperation |
| CN113972908B (en) * | 2021-12-24 | 2022-03-29 | 江苏长晶科技股份有限公司 | Low-power consumption control port capable of preventing misoperation |
| CN115173837A (en) * | 2022-08-09 | 2022-10-11 | 无锡飞龙九霄微电子有限公司 | Circuit and device for generating high delay |
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Application publication date: 20140319 |