CN107564449A - Gate driving circuit and display device - Google Patents
Gate driving circuit and display device Download PDFInfo
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- CN107564449A CN107564449A CN201710824213.XA CN201710824213A CN107564449A CN 107564449 A CN107564449 A CN 107564449A CN 201710824213 A CN201710824213 A CN 201710824213A CN 107564449 A CN107564449 A CN 107564449A
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Abstract
This application discloses a kind of gate driving circuit, the gate driving circuit includes Postponement module, for being postponed at least one rear class enabling signal with delay start signal corresponding to obtaining；And the drive element of the grid of multiple cascades, the delay start signal corresponding to of drive element of the grid described at least one-level positioned at the end of the drive element of the grid of the multiple cascade produces this grade of gate drive signal, the technical problem that the gate driving circuit of the present invention solves is, by way of producing signal delay before rear class enabling signal enters inside drive element of the grid, reduce electrostatic induced current, so as to reach the purpose for slowing down voltage switching counter plate and impacting.
Description
Technical field
The present invention relates to display technology field, more particularly, to a kind of gate driving circuit and display device.
Background technology
Display device generally comprises display panel, gate driving circuit and source electrode drive circuit.Wherein, display panel includes
The pel array formed by multiple pixel cells, each pixel cell include a thin film transistor (TFT).In the pel array, position
The grid of thin film transistor (TFT) in the pixel cell of same a line is connected by same scan line with gate driving circuit, grid
Drive circuit selects each row pixel cell in pel array by multi-strip scanning line line by line；In the pixel cell of same row
Thin film transistor (TFT) source electrode or drain electrode be connected by same data line with source electrode drive circuit, source electrode drive circuit passes through more
Data line applies gray scale voltage to each row pixel cell, so that image is presented in display panel.
With the development of display device, the application of integrated gate driver technology (Gate Driver In Array, GIA) is got over
Come more extensive, it is that gate driving circuit and display panel are integrated on same substrate, and this technology can not only reduce number
Cabling in the thousands, make display device more symmetrical and compact, moreover it is possible to reduce cost, the resolution ratio for improving display panel and bending
Degree.
However, in the prior art, for the rear class enabling signal of gate driving circuit, there is more serious
Electro-static Driven Comb problem, contrast prime enabling signal find that the load of rear class enabling signal is less than normal with clock signal, are run in circuit
When, there is more serious Electro-static Driven Comb in rear class enabling signal, due to the electrostatic charge accumulated on rear class enabling signal connection end
Lack effective Electro-static Driven Comb path, so as to cause electrostatic induced current excessive, easily burn rear class enabling signal connection end, rear class opens
Dynamic signal could not previously be loaded on corresponding drive element of the grid so that the integrated drive circuit cisco unity malfunction of gate line, enter
And influenceing whole display panel can not normally show.
The content of the invention
The present invention provides a kind of gate driving circuit and display device for the above mentioned problem in the presence of prior art,
Its technical problems to be solved is, signal delay is produced before entering by rear class enabling signal inside drive element of the grid
Mode, electrostatic induced current is reduced, so as to reach slow down voltage switching opposite plate material caused by the purpose impacted.
According to an aspect of the present invention, there is provided a kind of gate driving circuit, the gate driving circuit include Postponement module,
For being postponed to rear class enabling signal with delay start signal corresponding to obtaining；And the raster data model list of multiple cascades
Member, the institute corresponding to of drive element of the grid described at least one-level positioned at the end of the drive element of the grid of the multiple cascade
State delay start signal and produce this grade of gate drive signal.
Preferably, the Postponement module includes at least one delay cell, and each delay cell will not be with respectively will
Same rear class enabling signal delay is the corresponding delay start signal.
Preferably, each delay cell is with including：Input module, for according to rear class enabling signal control the
The voltage of one node, the first node provide the delay start signal；First control module, for being believed according to the first reference
Number produce the first control signal；Second control module, it is connected in section point with first control module, when the rear class
When enabling signal is effective, second control module produces the second control signal according to the second reference signal；And drop-down module,
It is connected in the first node with the input module, when first control signal or second control signal are effective
When, the drop-down module pulls down the delay start signal according to the second reference signal.
Preferably, the input module includes the first transistor, the control terminal of the first transistor, the first path termination
The rear class enabling signal is received, the alternate path end of the first transistor is connected with the first node to control the delay
Enabling signal.
Preferably, first control module includes third transistor, the first path terminal and the control of the third transistor
End processed receives first reference signal, and the alternate path end of the first transistor is connected to provide with the section point
State the first control signal.
Preferably, second control module includes second transistor and first resistor, a termination of the first resistor
The rear class enabling signal is received, between the other end of the first resistor and the control terminal of the second transistor, described in reception
Rear class enabling signal, the first path terminal the second reference signal of reception of the second transistor, the second of the second transistor
Path terminal is connected with the section point and exports second control signal.
Preferably, the drop-down module includes the 4th transistor, the control terminal of the 4th transistor and the described second section
Point is connected, and the first path terminal of the 4th transistor receives second reference signal, and the second of the 4th transistor is logical
Terminal is connected with the first node, and described first is pulled down when first control signal or effective second control signal
The voltage of node.
Preferably, first reference signal is grid high level voltage, and second reference signal is grid low level
Voltage.
Preferably, the transistor in the gate driving circuit is realized by N-channel thin film transistor (TFT).
According to another aspect of the present invention, there is provided a kind of display device, it is characterised in that including at least one as appointed above
Gate driving circuit described in one.
The beneficial effect of the gate driving circuit of the embodiment of the present invention is to enter raster data model list by rear class enabling signal
The mode of signal delay is produced before first internal, electrostatic induced current is reduced, slows down voltage switching counter plate so as to reach and causes to rush
The purpose hit.
Brief description of the drawings
By the description to the embodiment of the present invention referring to the drawings, above-mentioned and other purposes feature of the invention and excellent
Point will be apparent from.
Fig. 1 shows the structural representation of the display device of the embodiment of the present invention.
Fig. 2 shows the structural representation of gate driving circuit in the display device of the embodiment of the present invention.
Fig. 3 shows the schematic block diagram of delay cell in the display device of the embodiment of the present invention.
Fig. 4 shows the structural representation of delay cell in the display device of the embodiment of the present invention.
Fig. 5 shows the time diagram of delay cell in the operational mode in the display device of the embodiment of the present invention.
Embodiment
The present invention is more fully described hereinafter with reference to accompanying drawing.In various figures, identical element is using similar attached
Icon is remembered to represent.For the sake of clarity, the various pieces in accompanying drawing are not necessarily to scale.Furthermore, it is possible to it is not shown some
Known part.
Many specific details of the present invention are describe hereinafter, to be more clearly understood that the present invention.But as this
The technical staff in field it will be appreciated that as, the present invention can not be realized according to these specific details.
Fig. 1 shows the structural representation of the display device of the embodiment of the present invention, and the display device includes sequential control circuit
1100th, source electrode drive circuit 1200, gate driving circuit 1300, display panel 1400, wherein gate driving circuit 1300 can be with
It is integrated in display panel 1400 on same substrate to form integrated gate drive configuration.
Sequential control circuit 1100 is used to provide multiple clocks to source electrode drive circuit 1200 and gate driving circuit 1300
The control signal such as signal and enabling signal (Start Vertical, STV), wherein, enabling signal can be the unlatching of a frame
Signal.
Below in the description of the embodiment of the present invention, unless otherwise instructed, i be more than or equal to 1 and less than or equal to n from
So number.
Fig. 2 shows the structural representation of gate driving circuit in the display device of the embodiment of the present invention, raster data model electricity
Road includes multistage drive element of the grid GIA [1] to GIA [n] and Postponement module 1301.Wherein, drive element of the grid difference at different levels
Export gate drive signal G [1] to G [n] and transmit signal Z [1] to Z [n].Come for every grade of drive element of the grid GIA [i]
Say, the transmission signal Z [i] of this grade is used to substitute the gate drive signal G [i] of this grade to realize between drive element of the grid at different levels
Signal transmission, the gate drive signal G [i] of this grade is mainly used in driving the transistor in pixel cell, so as to avoid this
Level gate drive signal G [i] decay, ensure that the row pixel cell can be driven normally.Therefore, under normal conditions,
Every grade of transmission signal Z [i] is equal with the gate drive signal G [i] that this grade of drive element of the grid GIA [i] exports.
Every grade of drive element of the grid GIA [i] is for example with prime input, rear class input, clock end, drive end, biography
Pass end, reference voltage end.
The prime input of drive element of the grid at different levels receives prime grid and transmits signal Z [i-1], and rear class input receives
Rear class grid transmits signal Z [i+1], and clock end receives clock signal clk corresponding with this grade of drive element of the grid, power supply termination
The second reference signal VGL is received, drive end exports this grade of gate drive signal G [i], transmits end and exports this grade of grid transmission signal Z
[i]。
The gate driving circuit includes two-way clock signal, respectively the first clock signal clk A, second clock signal
CLKB。
In the gate driving circuit of the present invention, first order drive element of the grid GIA [1] clock end clk receives first
Clock signal clk A, prime input receive prime grid transmit signal Z [i-1] be directly provided by sequential control circuit or
The the first enabling signal STV1 provided through source electrode drive circuit, drive end output first order gate drive signal G [1], transmit end
Export first order grid and transmit signal Z [1], it is second level grid that the rear class grid that rear class input receives, which transmits signal Z [i+1],
Driver element circuit GIA [2] second level grid transmits signal Z [2].
Second level drive element of the grid GIA [2] clock end clk receives second clock signal CLKB, prime input termination
It is second for directly being provided by sequential control circuit or being provided through source electrode drive circuit that the prime grid of receipts, which transmits signal Z [i-1],
Enabling signal STV2, drive end output second level gate drive signal G [2], transmit end output second level grid and transmit signal Z
[2], the rear class grid that rear class input receives transmits that signal Z [i+1] is third level gate drive unit circuit GIA [3]
Three-level grid transmits signal Z [3].
In gate driving circuit, first to second grid driver element forms a cycle, subsequent gate driver element
Circulating repetition first will not be repeated here to the annexation of second level element circuit.
Postponement module 1301 is used to respectively start the 3rd enabling signal STV3 and the 4th according to the first reference signal VCOM
The 3rd enabling signal STV3 ' and the 4th enabling signal STV4 ' of delay that signal STV4 enters line delay to be postponed, wherein the
Three enabling signal STV3 and the 4th enabling signal STV4 are directly to be provided by sequential control circuit or provided through source electrode drive circuit
's.It is by Postponement module that the rear class that (n-1)th grid level driver element GIA [n-1] rear class input receives, which transmits signal Z [i+1],
3rd enabling signal STV3 ' of 1301 delays provided, wherein what the n-th grid level driver element GIA [n] rear class input received
Rear class transmits the 3rd enabling signal STV4 ' that signal Z [i+1] is the delay provided by Postponement module 1301.
In this gate driving circuit, the first reference signal VCOM is grid high level voltage, and the second reference signal VGL is
Grid low level voltage, clock end receives respectively directly to be provided by sequential control circuit or is provided through source electrode drive circuit multiple
It is at least one in clock signal.
Fig. 3 shows the schematic block diagram of delay cell in the display device of the embodiment of the present invention.
The Postponement module 1301 of the display device includes at least one delay cell 1310, as shown in figure 3, each delay is single
Member 1310, which is used to realize a rear class enabling signal (the 3rd enabling signal STV3 or the 4th enabling signal SVT4), to be postponed, at this
In embodiment, Postponement module 1301 includes two delay cells 1310, and it is to prolong to be respectively used to the 3rd enabling signal STV3 delays
Slow the 3rd enabling signal STV3 ', the 4th signal STV4 ' by the 4th enabling signal STV4 delays for delay.It is but of the invention
The display device not limited to this of offer, those skilled in the art can be set according to actual circuit demand postpones list in Postponement module
The number of member.
Each delay cell 1310 include input module 1311, the first control module 1312, the second control module 1313 with
And drop-down module 1314.The annexation of each module in delay cell is specifically described with signal relation below.
Input module 1311 is used to receive rear class enabling signal STV (such as the 3rd enabling signal STV3 according to input
Or the 4th enabling signal STV4) first node Q1 voltage is provided, wherein, output end and the first node Q1 of input module 1310
It is connected.
The input of first control module 1312 receives the first reference signal VCOM, the output end of the first control module 1321
It is connected with section point Q2, wherein the first control module 1312 produces the first control according to the first reference signal VCOM in output end
Signal Vctrl1.
The input of second control module 1313 receives rear class enabling signal STV, the output end of the second control module 1313
Be connected with section point Q2, wherein the second control module 1313 according to rear class enabling signal STV and the second reference signal VGL defeated
Go out end and produce the second control signal Vctrl2.
The input of drop-down module 1314 is connected with section point Q2, and output end is connected with first node Q1, pulls down module
1314 pull down first node according to the first control signal Vctrl1 and the second control signal Vctrl2 and the second reference signal VGL
Q1 voltage, and delay start signal STV ' is produced in output end according to first node Q1 voltage.
Fig. 4 shows the structural representation of delay cell in the display device of the embodiment of the present invention.It should be noted that at this
The transistor referred in embodiment is N-type TFT, i.e., the transistor in gate driving circuit is by N-channel film crystal
Pipe is realized, and the first path terminal of each transistor and alternate path end can exchange (i.e. drain electrode and source electrode can exchange).But
Be the present invention be practiced without limitation to this.
Input module 1311 includes transistor T1, and transistor T1 source electrode and grid (i.e. control terminal) are connect with being opened for offer
The input of dynamic signal is connected, for receiving enabling signal (such as the 3rd enabling signal STV3 or the 4th enabling signal STV4),
Transistor T1 drain electrode is connected with first node Q1, control first node Q1 voltage.
First control module 1312 includes transistor T3.Transistor T3 grid, source electrode receives the first reference signal VCOM,
Transistor T1 drain electrodes are connected with section point Q2, produce the first control signal Vctrl1.
Second control module 1313 includes transistor T2 and resistance R1.Resistance R1 is connected on transistor T1 and transistor T2's
For grid to receive enabling signal STV, transistor T2 source electrode receives the second reference signal VGL, transistor T2 drain electrode and second
Node Q2 is connected, and produces the second control signal Vctrl2.
Drop-down module 1314 includes transistor T4, and transistor T4 grid is connected with section point Q2, transistor T4 source
Pole receives the second reference signal VGL, and transistor T4 drain electrode is connected with first node Q1, as the first control signal Vctrl1 or the
First node Q1 voltage is pulled down when two control signal Vctrl2 are effective, and is produced according to first node Q1 voltage in output end
Delay start signal STV '.
Fig. 5 shows the time diagram of delay cell in the operational mode in the display device of the embodiment of the present invention.
As shown in figure 5, when gate driving circuit is in first stage P1, enabling signal STV is low level, therefore crystal
Pipe T1, T2 are turned off, and the first reference voltage VCOM is high level, and now, transistor T3 conductings, the first control signal Vctrl1 has
Effect, section point Q2 voltages are high level, therefore transistor T4 is turned on, and the second reference signal VGL is low level, therefore, first
Node Q1 voltage is low level, and delay start signal STV ' is low level.
When gate driving circuit circuit is in second stage P2, enabling signal STV is high level, therefore transistor T1,
T2 is turned on, and the second control signal Vctrl2 is effective, and the second reference signal VGL is low level, therefore section point Q2 is low level,
Transistor T4 is gradually turned off, and therefore, first node Q1 voltage is gradually raised, and delay start signal STV ' voltage is gentle
Rise.
Contrast enabling signal STV and delay start signal STV ' and understand that delay start signal STV ' ascendant trends are more flat
It is slow, reach carryover effects.
The beneficial effect of the embodiment of the present invention is to devise a kind of gate driving circuit and display device, is opened by rear class
Dynamic signal produces the mode of signal delay before entering inside drive element of the grid, reduce electrostatic induced current, slow down electricity so as to reach
The purpose that crush-cutting impacts caused by changing opposite plate material.
It should be noted that herein, such as first and second or the like relational terms are used merely to a reality
Body or operation make a distinction with another entity or operation, and not necessarily require or imply and deposited between these entities or operation
In any this actual relation or order.Moreover, term " comprising ", "comprising" or its any other variant are intended to
Nonexcludability includes, so that process, method, article or equipment including a series of elements not only will including those
Element, but also the other element including being not expressly set out, or it is this process, method, article or equipment also to include
Intrinsic key element.In the absence of more restrictions, the key element limited by sentence "including a ...", it is not excluded that
Other identical element also be present in process, method, article or equipment including the key element.
According to embodiments of the invention as described above, these embodiments do not have all details of detailed descriptionthe, not yet
It is only described specific embodiment to limit the invention.Obviously, as described above, can make many modifications and variations.This explanation
Book is chosen and specifically describes these embodiments, is in order to preferably explain the principle and practical application of the present invention, so that affiliated
Technical field technical staff can be used using modification of the invention and on the basis of the present invention well.The present invention is only by right
The limitation of claim and its four corner and equivalent.
Claims (10)
1. a kind of gate driving circuit, including Postponement module, the drive element of the grid of multiple cascades, it is characterised in that
The Postponement module, for being postponed to rear class enabling signal with delay start signal corresponding to obtaining；And
The drive element of the grid of the multiple cascade, at least one-level positioned at the end of the drive element of the grid of the multiple cascade
Drive element of the grid delay start signal corresponding to produces this grade of gate drive signal.
2. gate driving circuit according to claim 1, it is characterised in that the Postponement module includes at least one delay
Unit, each delay cell are used to be respectively the corresponding delay start by different rear class enabling signal delays
Signal.
3. gate driving circuit according to claim 2, it is characterised in that each delay cell includes：
Input module, for the voltage according to rear class enabling signal control first node, described in the first node offer
Delay start signal；
First control module, for producing the first control signal according to the first reference signal；
Second control module, it is connected in section point with first control module, when the rear class enabling signal is effective,
Second control module produces the second control signal according to the second reference signal；And
Module is pulled down, it is connected in the first node with the input module, when first control signal or described second
When control signal is effective, the drop-down module pulls down the delay start signal according to second reference signal.
4. gate driving circuit according to claim 3, it is characterised in that the input module includes the first transistor,
The control terminal of the first transistor, the first path terminal receive the rear class enabling signal, and the second of the first transistor is logical
Terminal is connected with the first node to control the delay start signal.
5. gate driving circuit according to claim 3, it is characterised in that first control module includes the 3rd crystal
Pipe, the first path terminal of the third transistor and control terminal receive first reference signal, and the of the first transistor
Two path terminals are connected with the section point to provide first control signal.
6. gate driving circuit according to claim 3, it is characterised in that second control module includes the second crystal
Pipe and first resistor, one end of the first resistor receive the rear class enabling signal, the other end of the first resistor and institute
Between the control terminal for stating second transistor, the rear class enabling signal is received, the first path terminal of the second transistor receives
Second reference signal, the alternate path end of the second transistor, which is connected with the section point and exports described second, to be controlled
Signal processed.
7. gate driving circuit according to claim 3, it is characterised in that the drop-down module includes the 4th transistor,
The control terminal of 4th transistor is connected with the section point, and the first path terminal of the 4th transistor receives described the
Two reference signals, the alternate path end of the 4th transistor are connected with the first node, when first control signal or
Second control signal pulls down the voltage of the first node when effective.
8. gate driving circuit according to claim 3, it is characterised in that first reference signal is grid high level
Voltage, second reference signal are grid low level voltage.
9. gate driving circuit according to claim 1, it is characterised in that transistor in the gate driving circuit by
N-channel thin film transistor (TFT) is realized.
10. a kind of display device, it is characterised in that including at least one raster data model as described in any one of claim 1 to 9
Circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710824213.XA CN107564449B (en) | 2017-09-13 | 2017-09-13 | Gate drive circuit and display device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710824213.XA CN107564449B (en) | 2017-09-13 | 2017-09-13 | Gate drive circuit and display device |
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| Publication Number | Publication Date |
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| CN107564449A true CN107564449A (en) | 2018-01-09 |
| CN107564449B CN107564449B (en) | 2020-12-01 |
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| CN108257569A (en) * | 2018-02-06 | 2018-07-06 | 昆山龙腾光电有限公司 | Gate driving circuit and display device |
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| Publication number | Publication date |
|---|---|
| CN107564449B (en) | 2020-12-01 |
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Address after: 215301, 1, Longteng Road, Kunshan, Jiangsu, Suzhou Applicant after: Kunshan Longteng Au Optronics Co Address before: 215301, 1, Longteng Road, Kunshan, Jiangsu, Suzhou Applicant before: Kunshan Longteng Optronics Co., Ltd. |
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