CN113972908A - Low-power consumption control port capable of preventing misoperation - Google Patents
Low-power consumption control port capable of preventing misoperation Download PDFInfo
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- CN113972908A CN113972908A CN202111592843.1A CN202111592843A CN113972908A CN 113972908 A CN113972908 A CN 113972908A CN 202111592843 A CN202111592843 A CN 202111592843A CN 113972908 A CN113972908 A CN 113972908A
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- control port
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- tube
- nmos transistor
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0175—Coupling arrangements; Interface arrangements
- H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
- H03K19/018507—Interface arrangements
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/003—Modifications for increasing the reliability for protection
- H03K19/00315—Modifications for increasing the reliability for protection in field-effect transistor circuits
Abstract
The invention discloses a low-power consumption control port for preventing misoperation, wherein when the potential of the control port is high, a kiloohm pull-down resistor is disconnected with the control port through a switching tube, so that the power consumption at the moment of normal operation is reduced; when the control port is at a low potential, the switch tube is opened, the kiloohm pull-down resistor is connected with the control port, so that the fast pull-down is realized, the control port is prevented from being started by an interference signal by mistake, meanwhile, the start delay circuit is introduced, the kiloohm pull-down resistor can be kept connected with the control port within a period of tens of us grade when the high potential of the control port is controlled, the internal circuit is prevented from being started by mistake when the control port is at a high level due to the interference of the interference signal to the high-impedance control port, and the internal circuit is closed when the control port is at a low level.
Description
Technical Field
The present invention relates to power management of integrated circuits, and more particularly to a low power control port for preventing malfunctions.
Background
As portable electronic products are widely used in various aspects of work and life, higher requirements are put on power supplies, and whether static current (IQ) can be reduced to a greater extent is a key factor for reducing power consumption and managing battery life. In order to understand the important role of reducing IQ on prolonging the service life of a battery to a greater extent, attention can be paid to low-power-consumption IOT (Internet of things) application, such as an intelligent door lock, and the service life of the battery can be prolonged from two years to more than five years by carefully optimizing a power management module with low static power consumption.
A problem with current products employing one or more dedicated control ports is that once the product becomes fully controllable after initial power-up, current continues to be consumed and therefore wasted by one or more dedicated power-up control circuits. These known control port solutions and architectures require that current flow in the control port circuitry occurs at any time during operation of the associated product. As shown in fig. 1(a) and fig. 1(b), the enabling control port controls the switch of the LDO circuit, and the two products shown in fig. 1(a) and fig. 1(b) respectively use a resistor and a current source as pull-down power, and after the enabling of the LDO circuit is completed, the current at the port is still consumed, which is not favorable for long standby time requirements of low power consumption applications such as the internet of things. Meanwhile, if the pull-down power of the port is removed, the port is easily interfered by the outside in a suspended state and is switched on or off by mistake, so that the current is consumed.
Disclosure of Invention
In order to solve the defects of the prior art, the invention provides the low-power-consumption control port for preventing misoperation, so that the power consumption of the control port is reduced during normal work, and the misoperation influence of an interference signal on a high-impedance control port can be effectively avoided.
In order to achieve the purpose, the invention adopts the following technical scheme: a low-power consumption control port for preventing misoperation is characterized by comprising NMOS transistors N1, N2 and N3, NMOS transistors ND1 and ND2, PMOS transistors P1, P2 and P3, inverters inv1 and inv2, a capacitor C1 and a resistor R1; the Control port Control1 is connected with the input terminal of the inverter inv1 and the drain of the NMOS transistor N1, the output of the inverter inv1 is connected with the gate of the NMOS transistor N3, the source and the substrate of the NMOS transistor N3 are interconnected and grounded, the source and the substrate and the gate of the NMOS transistor ND1, the source and the substrate and the gate of the NMOS transistor ND2 are grounded, the source and the substrate of the NMOS transistor N1 are interconnected and grounded through a resistor R1, the drain of the NMOS transistor ND1 is connected with the drain and the gate of the PMOS transistor P1 and the gate of the PMOS transistor P3, the drain of the NMOS transistor N3 is connected with the drain of the PMOS transistor P3 and one terminal of the capacitor C1 and the gate of the PMOS transistor P1, the source and the substrate of the PMOS transistor P1 and the source and the substrate of the PMOS transistor P1 are connected, the other terminal of the capacitor C1 is grounded, the drain of the PMOS transistor P1 is connected with the drain of the NMOS transistor N1 and the drain of the NMOS transistor N1, the drain of the NMOS transistor ND1 and the drain of the NMOS transistor N1 are connected with the drain of the NMOS transistor N1 and the drain of the NMOS transistor N1, the drain of the NMOS transistor N1 are connected with the drain of the NMOS transistor N1 and the NMOS transistor N1, the output of inverter inv2 connects to internal circuitry that is the target to be controlled by Control port Control 1.
Further, the NMOS ND1 and the NMOS ND2 are Native transistors with a depletion or threshold value close to 0.
Further, a Control port Control11 is used for replacing a Control port Control1, an NMOS tube N11 is used for replacing an NMOS tube N1, a resistor R11 is used for replacing a resistor R1, an inverter inv11 is used for replacing an inverter inv1, an NMOS tube N31 is used for replacing an NMOS tube N3, a PMOS tube PD1 is used for replacing a PMOS tube P3, a capacitor C11 is used for replacing a capacitor C1, an NMOS tube N21 is used for replacing an NMOS tube N2, a PMOS tube P21 is used for replacing a PMOS tube P2, an inverter inv21 is used for replacing an inverter inv2, a PMOS tube PD2 is additionally arranged, and the PMOS tube P1, the NMOS tube ND1 and the NMOS tube ND2 are removed; the Control port Control11 is connected with the input end of the inverter inv11 and the drain of the NMOS tube N11, the source and the substrate of the NMOS tube N11 are connected with each other and grounded through a resistor R11, the output of the inverter inv11 is connected with the gate of the NMOS tube N31, the source and the substrate of the NMOS tube N31 are connected with each other and grounded, the drain of the NMOS tube N31 is connected with the drain of the PMOS tube PD1 and one end of a capacitor C11, the gate of the PMOS tube P21 and the gate of the NMOS tube N21, the source, the substrate and the gate of the PMOS tube PD1 and the source, the substrate and the gate of the PMOS tube PD2 are all connected with VDD, the other end of the capacitor C11 is grounded, the drain of the PMOS tube PD2 is connected with the source and the substrate of the PMOS tube P21, the drain of the PMOS tube P21 is connected with the drain of the NMOS tube N21 and the input end of the inverter inv11, the output of the inverter inv21 is connected with an internal circuit, and the Control port 11 is a target to be controlled.
Further, the PMOS tube PD1 and the PMOS tube PD2 are Native tubes with the depletion or threshold value close to 0.
The invention has the advantages and obvious effects that: the invention has the advantages that the current is not consumed during the period that the control port is connected with the high potential, and the strong pull-down effect is provided when the control port is connected with the low potential, so that the pull-down resistor is used for keeping the control port not suspended until the sequencing of the system is completed. Once the control port is high, the intelligent pull-down resistor (R1 in fig. 2, R11 in fig. 3) is turned off to prevent unnecessary power loss.
Drawings
Fig. 1(a) shows a conventional enable control port controlling the switches of an LDO circuit, using resistors as the power for pull-down.
Fig. 1(b) shows another conventional enabling control port for controlling the switches of an LDO circuit, which employs a current source as the power for pulling down.
FIG. 2 is a circuit diagram of an embodiment of a low power control port for preventing malfunction according to the present invention.
FIG. 3 is a circuit diagram of another embodiment of a low power control port for preventing malfunction according to the present invention.
Detailed Description
Referring to fig. 2, for the implementation circuit of the present invention, N1/N2/N3 is an N-type MOS, P1/P2/P3 is a P-type MOS, ND1 and ND2 are depletion transistors or Native transistors with threshold close to 0, C1 is a capacitor, and inv1 and inv2 are inverters. Control1 is a Control port and the internal circuitry is the target that the Control port is to Control. Control1 connects the input of inverter inv1 and also to the drain of N1. Control2 is the output terminal of inv1 and is connected to the gate of NMOS transistor N3. The source substrates of N3, ND1 and ND2 are connected to ground potential. While the gates of ND1 and ND2 are also connected to ground. The drain of N3 is connected to the drain of PMOS transistor P3, the upper plate of capacitor C1 and the gates of P2 and N2. The source-substrate of P1, P2, P3 is connected to VDD potential. The gate of P3 is connected to the gate drain of P1 and the drain of depletion NMOS transistor ND 1. The lower plate of the capacitor C1 is grounded. The drain of P2 is connected to the drain of N2 and to the gate of N1. The source pad of N2 is connected to the drain of ND 2. The source of N1 is connected to one end of resistor R1. And the other end of R1 is connected to ground.
The working principle of fig. 2: the ND1, P1, P3 and the capacitor C1 form a delay circuit, and the N1 receives the output signal to perform switching operation to form a feedback circuit. The Control port Control1 turns on the internal circuit when high, and turns off the internal circuit when Control1 turns low. The threshold Vth1 of the Control1 voltage is determined by the size of the inverter inv 1. When Control1< Vth1, Control2= VDD, N3 is controlled to be turned on, C1 potential is discharged to 0, P2 is turned on, N2 is turned off, so that N1 gate potential is VDD, N1 is turned on, at this time, R1 is connected to a Control1 port through a switch N1, a pull-down resistance function is realized, and thus, an interference signal is prevented from starting the Control port by mistake. When Control1> Vth1, Control2=0 while controlling N3 to close. Since P3 charges the C1 capacitor, the charging current is proportional to P1, while the P1 current is equal to the ND1 current. When the voltage of the C1 reaches P2 OFF and N2 ON, the gate potential of the N1 is brought to ground. At this time, since N1 is turned off, the Control terminals of the resistors R1 and Control1 are turned off, so that current consumption of the resistor R1 is avoided, and power consumption of the port of Control1 can be reduced. It should be noted that when the capacitor C1 is not charged to the P2 off state, N1 remains in the original on state, which ensures that when the control1 port has a transient spike interference voltage, the system is prevented from being started by mistake, and the control accuracy is achieved.
Referring to fig. 3, in another implementation circuit of the present invention, N11/N21/N31 is an N-type MOS, P21 is a P-type MOS, PD1 and PD2 are depletion transistors or Native transistors with a threshold close to 0, C1 is a capacitor, and inv11 and inv21 are inverters. Control11 is a Control port and the internal circuitry is the target that the Control port is to Control. Control11 connects the input of inverter inv11 and to the drain of N11. Control12 is the output terminal of inv11 and is connected to the gate of NMOS transistor N31. The source substrates of N31 and N21 are connected to ground potential. While the gate, source, and substrate of PD1 and PD2 are also tied together to VDD potential. The drain of N31 is connected to the drain of PD1, the top plate of capacitor C11 and the gates of P21 and N21. The lower plate of the capacitor C11 is grounded. The source of P21 is connected to the drain of PD 2. P21 is connected to the drain of N21, as well as to the gate of N11 and to the input of inverter inv 21. The output of the inverter inv21 controls the internal circuitry. The source of N11 is connected to one end of resistor R11. And the other end of R11 is connected to ground.
The working principle of fig. 3: wherein PD1, N31 and electric capacity C11 constitute delay circuit, and N11 receives the output signal and carries out the switching operation, forms feedback circuit. The internal circuit is activated when the Control port Control11 is high and Inv21 outputs high, and is deactivated when Control11 is low and Inv21 outputs low. The threshold Vth2 of the Control11 voltage is determined by the size of the inverter inv 11. When Control11< Vth2, Control12= VDD, and controls N31 to be on, C11 is 0, P21 is on, and N21 is off, so that N11 is VDD, and N11 is on, and therefore, at this time, R11 is connected to the port of Control11 through the switch N11, and a strong pull-down resistance function is realized. At the same time inv21 outputs a low level, turning off the internal circuitry. When Control11> Vth2, Control12=0 while controlling N31 to close. Since PD1 charges C11, when the C11 voltage reaches P21 off and N21 on, the N11 gate potential is brought to ground. At this time, since N11 is turned off, the Control terminals of the resistors R11 and Control11 are turned off, so that current consumption of the resistor R11 is avoided, and power consumption of the port of Control11 can be reduced. And inv21 outputs high level to turn on the internal circuit. It should be noted that when the capacitor C11 is not charged to P21 and turned off, N11 remains in the original on state, and inv21 outputs a low level to turn off the internal circuit, which can ensure that when the control11 port has a transient spike interference voltage, the internal circuit is prevented from being started by mistake, and the control accuracy is achieved.
The control port principle of the two implementation circuits of fig. 2 and fig. 3 is the same, except that the architecture of the low-power consumption control port is slightly different, mainly the difference of the bias circuit caused by the difference of the devices providing the nA-level low-power consumption reference current source. The specific difference is that in fig. 2, a Native transistor with N-type depletion or threshold close to 0 is used, and a pmos transistor mirror image is needed to provide a pmos current source, so as to be connected in series with N3. In fig. 3, since a P-type depletion tube or a Native tube having a threshold value close to 0 is used, N31 may be directly connected in series.
The invention starts the internal circuit when the control port is at high level, and closes the internal circuit when the control port is at low level. The feedback circuit is introduced, when the potential of the control port is high, the kiloohm pull-down resistor is disconnected with the control port through the switch, and therefore the power consumption at the moment of normal operation is reduced; when the control port is at a low potential, the switch is turned on, and the kiloohm pull-down resistor is connected with the control port, so that the fast pull-down is realized, and the control port is prevented from being started by an interference signal. Meanwhile, a starting delay circuit is introduced, so that when the high potential of the control port is controlled, the kiloohm pull-down resistor can be kept connected with the control port within a period of tens of us, and the false starting caused by the interference of an interference signal to the high-impedance control port is avoided.
Claims (4)
1. A low-power consumption control port for preventing misoperation is characterized by comprising NMOS transistors N1, N2 and N3, NMOS transistors ND1 and ND2, PMOS transistors P1, P2 and P3, inverters inv1 and inv2, a capacitor C1 and a resistor R1; the Control port Control1 is connected with the input end of the inverter inv1 and the drain of the NMOS transistor N1, the output of the inverter inv1 is connected with the gate of the NMOS transistor N3, the source and the substrate of the NMOS transistor N3 are interconnected and grounded, the source and the substrate and the gate of the NMOS transistor ND1, the source and the substrate and the gate of the NMOS transistor ND2 are grounded, the source and the substrate of the NMOS transistor N1 are interconnected and grounded through a resistor R1, the drain of the NMOS transistor ND1 is connected with the drain and the gate of the PMOS transistor P1 and the gate of the PMOS transistor P3, the drain of the NMOS transistor N3 is connected with the drain of the PMOS transistor P3 and one end of a capacitor C1 and the gate of the PMOS transistor P1 and the gate of the NMOS transistor N1, the source and the substrate of the PMOS transistor P1 and the source and the substrate of the PMOS transistor P1 are connected with VDD, the other end of the capacitor C1 is grounded, the drain of the NMOS transistor N1 is connected with the drain of the NMOS transistor N1 and the drain of the NMOS transistor N1, the drain of the NMOS transistor N1 and the drain of the NMOS transistor N1 are connected with the drain of the NMOS transistor N1 and the drain of the NMOS transistor N1, the drain of the NMOS transistor N1 are connected with the NMOS transistor N1 and the NMOS transistor N1, the drain of the NMOS transistor N1 and the drain of the NMOS transistor N1 are connected with the NMOS transistor N1, the output of inverter inv2 connects to internal circuitry that is the target to be controlled by Control port Control 1.
2. The misoperation prevention low-power consumption control port according to claim 1, wherein the NMOS transistor ND1 and the NMOS transistor ND2 are Native transistors with a consumption or threshold value close to 0.
3. The misoperation-preventing low-power-consumption Control port according to claim 1, wherein the Control port Control1 is replaced by a Control port Control11, the NMOS tube N11 is replaced by an NMOS tube N1, the resistor R11 is replaced by a resistor R1, the inverter inv11 is replaced by an inverter inv1, the NMOS tube N31 is replaced by an NMOS tube N3, the PMOS tube PD1 is replaced by a PMOS tube P3, the capacitor C11 is replaced by a capacitor C1, the NMOS tube N21 is replaced by an NMOS tube N2, the PMOS tube P21 is replaced by a PMOS tube P2, the inverter inv21 is replaced by an inverter inv2, the PMOS tube PD2 is added, and the PMOS tube P1, the NMOS tube ND1 and the NMOS tube ND2 are removed; the Control port Control11 is connected with the input end of the inverter inv11 and the drain of the NMOS tube N11, the source and the substrate of the NMOS tube N11 are connected with each other and grounded through a resistor R11, the output of the inverter inv11 is connected with the gate of the NMOS tube N31, the source and the substrate of the NMOS tube N31 are connected with each other and grounded, the drain of the NMOS tube N31 is connected with the drain of the PMOS tube PD1 and one end of a capacitor C11, and the gate of the PMOS tube P21 and the gate of the NMOS tube N21, the source, the substrate and the gate of the PMOS tube PD1 and the source, the substrate and the gate of the PMOS tube PD2 are all connected with VDD, the other end of the capacitor C11 is grounded, the drain of the PMOS tube PD2 is connected with the source and the substrate of the PMOS tube P21, the drain of the PMOS tube P21 is connected with the drain of the NMOS tube N21 and the input end of the inverter inv11, the output of the inverter inv21 is connected with an internal circuit, and the Control port 11.
4. The misoperation-preventing low-power consumption control port according to claim 3, wherein the PMOS transistor PD1 and the PMOS transistor PD2 are Native transistors with a consumption or threshold value close to 0.
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| CN202111592843.1A CN113972908B (en) | 2021-12-24 | 2021-12-24 | Low-power consumption control port capable of preventing misoperation |
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| CN202111592843.1A CN113972908B (en) | 2021-12-24 | 2021-12-24 | Low-power consumption control port capable of preventing misoperation |
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| CN113972908B (en) | 2022-03-29 |
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