JP2019050550A - Level shift circuit - Google Patents

Abstract

To provide a level shift circuit capable of improving a duty.SOLUTION: According to one embodiment, provided is a level shift circuit that has a first PMOS transistor, a first NMOS transistor, a second PMOS transistor, a third PMOS transistor, a second NMOS transistor, a fourth PMOS transistor, and a potential adjustment circuit. In the first PMOS transistor, a first node is electrically connected with its gate, and a second node is electrically connected with its source, and an output terminal in electrically connected its drain. In the first NMOS transistor, the first node is electrically connected with its gate, and the output terminal is electrically connected with its drain. In the second PMOS transistor, a third node is electrically connected with its gate, a second power supply potential is electrically connected with its source, and the second node is electrically connected with its drain. The potential adjustment circuit is at least electrically connected with the second node.SELECTED DRAWING: Figure 1

Description

  The present embodiment relates to a level shift circuit.

  The level shift circuit is used, for example, in a transmission / reception system in which the duty of data or clock to be transmitted is related to the reception performance.

Patent No. 3504172 Patent No. 4724578 gazette Patent No. 5643158 gazette JP, 2009-177280, A

  One embodiment aims to provide a level shift circuit that can improve the duty.

  According to one embodiment, a first PMOS transistor, a first NMOS transistor, a second PMOS transistor, a third PMOS transistor, a second NMOS transistor, a fourth PMOS transistor, and a potential adjustment circuit A level shift circuit is provided. The first PMOS transistor has a first node electrically connected to the gate, a second node electrically connected to the source, and an output terminal electrically connected to the drain. The first node receives a first signal having an amplitude of a first power supply potential. The output terminal outputs a signal having the amplitude of the second power supply potential. The second power supply potential is different from the first power supply potential. In the first NMOS transistor, the first node is electrically connected to the gate, and the output terminal is electrically connected to the drain. The second PMOS transistor has a third node electrically connected to the gate, a second power supply potential electrically connected to the source, and a second node electrically connected to the drain. The third PMOS transistor has a fourth node electrically connected to the gate, a fifth node electrically connected to the source, and a third node electrically connected to the drain. The fourth node has the amplitude of the first power supply potential, and receives the second signal. The second signal is a signal that is logically inverted with respect to the first signal. In the second NMOS transistor, the fourth node is electrically connected to the gate, and the third node is electrically connected to the drain. The fourth PMOS transistor has an output terminal electrically connected to the gate, a second power supply potential electrically connected to the source, and a fifth node electrically connected to the drain. The potential adjustment circuit is electrically connected to at least the second node.

FIG. 1 is a circuit diagram showing a configuration of the level shift circuit according to the first embodiment. FIG. 2 is a circuit diagram showing a configuration example of the switch in the first embodiment. FIG. 3 is a waveform diagram showing an operation example of the level shift circuit according to the first embodiment. FIG. 4 is a circuit diagram showing a configuration of the level shift circuit according to the second embodiment. FIG. 5 is a circuit diagram showing a configuration of a pulse generator in the second embodiment. FIG. 6 is a circuit diagram showing a configuration of a switch in the second embodiment. FIG. 7 is a waveform diagram showing the operation of the level shift circuit according to the second embodiment. FIG. 8 is a circuit diagram showing a configuration of a pulse generator in the third embodiment. FIG. 9 is a circuit diagram showing a configuration of the level shift circuit according to the fourth embodiment. FIG. 10 is a circuit diagram showing a configuration of a control circuit in the fourth embodiment. FIG. 11 is a waveform diagram showing an operation of the level shift circuit according to the fourth embodiment. FIG. 12 is a waveform diagram showing another operation of the level shift circuit according to the fourth embodiment. FIG. 13 is a circuit diagram showing a configuration of the level shift circuit according to the fifth embodiment. FIG. 14 is a circuit diagram showing a configuration of a level shift circuit according to a sixth embodiment. FIG. 15 is a circuit diagram showing a configuration of a level shift circuit according to a seventh embodiment.

  The level shift circuit according to the embodiment will be described in detail below with reference to the accompanying drawings. Note that the present invention is not limited by these embodiments.

First Embodiment
The level shift circuit 1 according to the first embodiment will be described. The level shift circuit 1 shifts the level of the input signal to a predetermined level, and outputs the shifted signal. At this time, in order to stably operate the initial movement of the output destination circuit, it is desired to operate the initial movement of the level shift circuit 1 stably.

  For example, the level shift circuit 1 is configured as shown in FIG. FIG. 1 is a circuit diagram showing a configuration of level shift circuit 1. The level shift circuit 1 includes an input buffer 10 and a level shifter 20.

  The input buffer 10 is composed of differential input and differential output, and has a positive inverter INV1 and a negative inverter INV2. The inverter INV1 and the inverter INV2 are connected in parallel with each other between the power supply potential VDDA and the ground potential GND.

  The inverter INV1 has a PMOS transistor PM1 and an NMOS transistor NM1. In the PMOS transistor PM1, the input terminal Tin1 is electrically connected to the gate, the power supply potential VDDA is electrically connected to the source, and the node N1 is electrically connected to the drain. In the NMOS transistor NM1, the input terminal Tin1 is electrically connected to the gate, the ground potential GND is electrically connected to the source, and the node N1 is electrically connected to the drain. That is, the drain of the PMOS transistor PM1 and the drain of the NMOS transistor NM1 are electrically connected.

  The inverter INV2 has a PMOS transistor PM4 and an NMOS transistor NM3. In the PMOS transistor PM4, the input terminal Tin2 is electrically connected to the gate, the power supply potential VDDA is electrically connected to the source, and the node N3 is electrically connected to the drain. In the NMOS transistor NM3, the input terminal Tin2 is electrically connected to the gate, the ground potential GND is electrically connected to the source, and the node N3 is electrically connected to the drain. That is, the drain of the PMOS transistor PM4 and the drain of the NMOS transistor NM3 are electrically connected.

  The level shifter 20 is configured by differential input and single output, and includes a PMOS transistor PM6, an inverter INV4, a PMOS transistor PM3, and an inverter INV3. The configuration in which PMOS transistor PM6 and inverter INV4 are connected in series and the configuration in which PMOS transistor PM3 and inverter INV3 are connected in series are connected in parallel between power supply potential VDDB and ground potential GND. Power supply potential VDDB is a potential different from power supply potential VDDA. In addition, the PMOS transistor PM6 and the inverter INV3 are cross-coupled to each other with the PMOS transistor PM3 and the inverter INV4.

  In the PMOS transistor PM6, the node N0 of the inverter INV3 is electrically connected to the gate, the power supply potential VDDB is electrically connected to the source, and the node N5 of the inverter INV4 is electrically connected to the drain.

  The inverter INV4 has a PMOS transistor PM5 and an NMOS transistor NM4. In the PMOS transistor PM5, the node N3 of the inverter INV2 is electrically connected to the gate, the node N5 is electrically connected to the source, and the node N4 is electrically connected to the drain. In the NMOS transistor NM4, the node N3 of the inverter INV2 is electrically connected to the gate, the ground potential GND is electrically connected to the source, and the node N4 is electrically connected to the drain. That is, the drain of the PMOS transistor PM5 and the drain of the NMOS transistor NM4 are electrically connected.

  In the PMOS transistor PM3, the node N4 of the inverter INV4 is electrically connected to the gate, the power supply potential VDDB is electrically connected to the source, and the node N2 of the inverter INV3 is electrically connected to the drain.

  The inverter INV3 has a PMOS transistor PM2 and an NMOS transistor NM2. In the PMOS transistor PM2, the node N1 of the inverter INV1 is electrically connected to the gate, the node N2 is electrically connected to the source, and the node N0 is electrically connected to the drain. In the NMOS transistor NM2, the node N1 of the inverter INV1 is electrically connected to the gate, the ground potential GND is electrically connected to the source, and the node N0 is electrically connected to the drain. The node N0 is electrically connected to the output terminal Tout. That is, the drain of the PMOS transistor PM2 and the drain of the NMOS transistor NM2 are electrically connected.

In the level shift circuit 1, in the input buffer 10, the inverter INV1 outputs from the node N1 as a voltage signal V _N1 obtained by logically inverting the clock φ CK input to the input terminal Tin1. The inverter INV2 outputs from the node N3 a voltage signal V _N3 obtained by logically inverting the clock φ CKB input to the input terminal Tin2. Clock φCKB is in logically inverted with respect to the clock FaiCK, the voltage signal V _N3 is logically inverted with respect to the voltage signal V _N1 (see FIG. 3).

  The level shifter 20 responds to the power supply potential VDDB from the level according to the power supply potential VDDA of the H level of the clocks φCK and φCKB received differentially by cross coupling connection of the PMOS transistor PM6 and the inverter INV3 with the PMOS transistor PM3 and the inverter INV4. Convert to a different level. At this time, this conversion operation can be performed at high speed by using the inverters INV3 and INV4 instead of the transistors as the connection partners of the PMOS transistor PM6 and the PMOS transistor PM3 in the cross coupling connection. The level shifter 20 outputs the converted clock φCKout from the output terminal Tout.

  The level shift circuit 1 is used, for example, when converting the signal level (VDDA) of the signal processing circuit to the signal level (VDDB) of the interface at high speed. At this time, in the case of the transmission and reception method in which the duty of the first clock and the duty thereafter are related to the reception performance, it is desirable that the duty is 50%.

  However, in the level shift circuit 1, when transitioning to a state (dense state) in which the signal levels of the clocks φCK and φCKB are suddenly transitioned from a state (rough state) in which there is no transition of signal levels of the input clocks φCK and φCKB. The duty of the first clock of the output clock φCKout fluctuates due to the voltage condition.

  This is because the potential of the node N2 in the level shift circuit 1 is unstable. For example, assuming that the threshold voltage of PMOS transistor PM2 is VthP, if power supply potential VDDA <power supply potential VDDB and VDDB−VDDA <VthP, PMOS transistor PM2 receiving at its gate clock φCK, which is at the H level in the initial state, The potential difference between the sources can not be sufficiently secured, and the node N2 is in a high impedance state.

  Thus, at the timing when the clock φCK transitions from L level to H level (at the start of operation), when the potential of the node N2 is unstable and is, for example, near 0 V, the output clock φCKout does not immediately come on It tends to rise at a timing delayed by the amount necessary to charge N 2. As a result, the H pulse width becomes smaller in the first cycle (first clock) of output clock φCKout, and the duty becomes smaller accordingly. For example, the setup time in the case of latching the first clock data in the circuit of the output destination The hold time may not be sufficiently secured, and an erroneous data value may be latched.

  Therefore, in the present embodiment, the charging circuit (potential adjustment circuit) 30 capable of charging the node N2 immediately before the timing at which the data transition of the output clock φCKout is to be performed provides the first clock of the output clock φCKout. Improve duty.

  Specifically, as shown in FIG. 1, the level shift circuit 1 further includes a charging circuit 30. The charging circuit 30 is electrically connected to the node N2 of the level shifter 20. The charging circuit 30 has a switch SW. Switch SW is electrically inserted between power supply potential VDDB and node N2, and its control node is electrically connected to control terminal Tsp. Switch SW is turned on / off in response to control signal φEN1 received at the control node via control terminal Tsp. The switch SW turns on to connect the power supply potential VDDB to the node N2, and turns off electrically disconnects the power supply potential VDDB from the node N2.

  The switch SW is configured, for example, as shown in FIG. FIG. 2 is a diagram showing a configuration example of the switch SW. The switch SW includes a PMOS transistor PM11, an NMOS transistor NM11, and a PMOS transistor PM12. The PMOS transistor PM11 and the NMOS transistor NM11 are inverter-connected between the power supply potential VDDB and the ground potential GND, the control terminal Tsp is commonly connected to their respective gates, and the gate of the PMOS transistor PM12 is commonly connected to their respective drains. ing. The source of the PMOS transistor PM11 is electrically connected to the power supply potential VDDB, and the source of the NMOS transistor NM11 is electrically connected to the ground potential GND. The power supply potential VDDB of the PMOS transistor PM12 is electrically connected to the source, and the node N2 of the level shifter 20 is electrically connected to the drain.

  The level shift circuit 1 including the charging circuit 30 operates as shown in FIG. 3, for example. FIG. 3 is a waveform diagram showing an operation example of the level shift circuit 1.

At timing t1 immediately before the rising timing t2 of the first clock of the input clock φCK, the control signal φEN1 transitions from the L level to the H level. As a result, the switch SW in the charging circuit 30 is turned on to charge the node N2, so that the potential V _{N2 of the} node N2 rises from L level to H level, and becomes stable at H level after timing t12. Here, the H level is VDDB.

At timing t2, control signal φEN1 transitions from H level to L level, and node N2 is electrically disconnected from power supply potential VDDB, but since potential V _{N2 of} node _N2 is already stable at H level, the clock When φCK transitions from L level to H level, rising of output clock φCKout can be made faster. Thereby, the duty of the first clock of the output clock φCKout can be improved.

Thereafter, the potential V _N2 of the node N2 may be attenuated to an intermediate level (between L level and H level) due to leakage or gate voltage value of the PMOS transistor PM2, but immediately before the rising timing t4 of the second clock of the clock φCK. At timing t3 of, the control signal .phi.EN1 transitions from L level to H level again. As a result, the switch SW in the charging circuit 30 is turned on to charge the node N2, so that the potential V _{N2 of the} node N2 rises from the intermediate level to the H level again and stabilizes at the H level after the timing t34. .

At timing t4, control signal φEN1 transitions from H level to L level, and node N2 is electrically disconnected from power supply potential VDDB, but since potential V _{N2 of} node _N2 is already stable at H level, the clock When φCK transitions from L level to H level, rising of output clock φCKout can be made faster. Thus, the duty of the second clock of the output clock φCKout can also be improved.

The operation (for example, the operation at timing t5 to t6) for the third and subsequent clocks of clock φCK is the same as the operation for the second clock of clock φCK (that is, the operation at timing t3 to t4). Further, the potentials V _N1 , V _N3 and V _N4 of the nodes N1, N3 and N4 change stably as shown in FIG.

  As described above, in the embodiment, the charging circuit 30 capable of charging the node N2 is provided immediately before the timing at which the data transition of the output clock φCKout is to be performed. This makes it possible to improve the duty of the first clock of the output clock φCKout and the duty of the subsequent clocks.

  In the embodiment, charging circuit 30 has switch SW electrically inserted between power supply potential VDDB and node N2. Thereby, charging circuit 30 can be realized with a simple configuration.

  The switch SW may be incorporated in the level shift circuit 1. Thereby, the parasitic capacitance value of the switch SW can be reduced, and the parasitic capacitance of the node N2 can be reduced.

Alternatively, a device for reducing power consumption may be added to the level shift circuit 1i. Referring to FIG. 3, the potential V _{N2 of the} node N2 is less likely to be unstable after the second clock of the clock φCK, as compared to immediately before the first clock of the clock φCK. Therefore, even if switch SW is selectively turned on immediately before the first clock of clock φCK, it is considered that potential V _{N2 of} node N 2 can be sufficiently stabilized.

  Based on such an idea, the level shift circuit 1i can be configured, for example, as shown in FIG. FIG. 4 is a diagram showing a configuration of the level shift circuit 1i according to the second embodiment. The level shift circuit 1i has a charging circuit 30i instead of the charging circuit 30 (see FIG. 1). The charging circuit 30i further includes a pulse generator PG. The pulse generator PG is electrically inserted between the control terminal Tsp and the switch SW. The pulse generator PG generates a pulse (one pulse) using the control signal φEN2 received via the control terminal Tsp, and supplies the pulse to the control node of the switch SW via the node N6.

  For example, the pulse generator PG is configured as shown in FIG. FIG. 5 is a diagram showing a configuration of a pulse generator PG in the second embodiment. The pulse generator PG has a line L1, a delay line L2, an AND gate AND, and an inverter INV14. The AND gate AND has an input node ANDa and an input node ANDb. The line L1 is electrically connected between the control terminal Tsp and the input node ANDa. The delay line L2 is electrically connected between the control terminal Tsp and the input node ANDb. The delay line L2 includes inverters INV11 to INV13 and capacitive elements C1 and C2, and delays the control signal φEN2 using the inverters INV11 to INV13 and capacitive elements C1 and C2.

  With the level of control signal .phi.EN2 at H level, pulse generator PG AND-gates the logical product of control signal .phi.EN2 transmitted almost without delay by line L1 and control signal .phi.EN2 delayed by delay line L2. The pulse (one pulse) can be generated by inverting the logic with the inverter INV14.

  The configuration of the switch SW can be simplified as shown in FIG. FIG. 6 is a diagram showing the configuration of the switch SW in the second embodiment. That is, the switch SW can be configured such that the PMOS transistor PM11 and the NMOS transistor NM11 are omitted from the configuration shown in FIG. 2 and the PMOS transistor PM12 operates alone as shown in FIG.

  At this time, the level shift circuit 1i operates, for example, as shown in FIG. FIG. 7 is a waveform diagram showing an operation of the level shift circuit 1i according to the second embodiment.

At timing t101, the control signal φEN2 changes from L level to H level, and after timing t101, the control signal φEN2 is fixed at H level. Thereby, in pulse generator PG, potential V _{N7 at} node N 7 (see FIG. 5) falls from H level to L level, and potential V _{N8 at} node N 8 (see FIG. 5) rises from L level to H level. Go. Accordingly, at timing t102 delayed from timing t101, potential V _{N9 at} node N9 (see FIG. 5) transitions from H level to L level, and the logical product and logic of the level of control signal φ EN2 and potential V _N9. As a result of the inversion, the waveform of the potential V _N6 of the node N6 can be pulsed low-active.

  Thus, the switch SW can be selectively turned on in a period from timing t101 to timing t102 immediately before the rising timing t103 of the clock φCK. That is, the number of ON operations of switch SW after the change of the level of control signal φEN2 can be reduced to one (switch SW is turned on immediately before the rising timing t103 of the first clock, rising timing after the second clock). Since the switch SW is not turned on immediately before t104, t105, etc.), the power consumption of the level shift circuit 1i can be easily reduced.

  Alternatively, as shown in FIG. 8, the capacitive elements C1 and C2 in the pulse generator PG may be replaced with PMOS transistors PM21 and PM22 and NMOS transistors NM21 and NM22. FIG. 8 is a circuit diagram showing a configuration of a pulse generator PG in the third embodiment. At this time, one of the PMOS transistors PM21 and PM22 and the NMOS transistors NM21 and NM22 may be omitted.

  The PMOS transistor PM21 has a source and a drain electrically connected in common to the power supply potential VDDB and a gate electrically connected to the node N7, and can equivalently function as a capacitive element. The NMOS transistor NM21 has a source and a drain electrically connected in common to the ground potential GND and a gate electrically connected to the node N7, and can equivalently function as a capacitive element. In the PMOS transistor PM22, the source and drain are electrically connected in common to the power supply potential VDDB, and the gate is electrically connected to the node N8, and can equivalently function as a capacitive element. The NMOS transistor NM22 has a source and a drain electrically connected in common to the ground potential GND and a gate electrically connected to the node N8, and can equivalently function as a capacitive element. Thus, the layout area of the pulse generator PG can be reduced as compared to the case where the pulse generator PG is configured using the capacitive elements C1 and C2 of the second embodiment.

Alternatively, the level shift circuit 1j may be provided with a configuration for further improving the duty accuracy of the clock. As shown in FIG. 3, the charging by the charging circuit 30 (temporary pull-up of the potential to the H level) is paused at the timing t2, so the potential V _{N2 of the} node _N2 is And to an intermediate level). However, if the potential V _{N2 of the} node N2 is continuously pulled up to the H level continuously after timing t2, attenuation to the intermediate level can be suppressed, and even after the first clock, the node N2 is The potential can be stabilized, and the rise of the clock φCKout can be made faster. Therefore, it is considered that the accuracy of the duty of the first clock of output clock φCKout and the duties thereafter can be further improved.

Based on such an idea, the level shift circuit 1j can be configured, for example, as shown in FIG. FIG. 9 is a diagram showing a configuration of the level shift circuit 1j according to the fourth embodiment. The level shift circuit 1j has a pull-up circuit (potential adjustment circuit) 30j instead of the charging circuit 30 (see FIG. 1). The pull-up circuit 30 j can pull up the potential V _{N2 of the} node N 2 continuously before the first clock of the clock φ CK. The pull-up circuit 30 j is electrically connected to the node N2. The pull-up circuit 30 j has a pull-up switch PSW1 including a PMOS transistor PM31. The PMOS transistor PM31 is electrically inserted between the power supply potential VDDB and the node N2. In the PMOS transistor PM31, the node N11 is electrically connected to the gate, the power supply potential VDDB is electrically connected to the source, and the node N2 is electrically connected to the drain.

  The pull-up circuit 30j is also electrically connected to the node N5 in consideration of circuit balance. The pull-up circuit 30j further includes a pull-up switch PSW2 including a PMOS transistor PM32. The PMOS transistor PM32 is electrically inserted between the power supply potential VDDB and the node N5. In the PMOS transistor PM32, the node N11 is electrically connected to the gate, the power supply potential VDDB is electrically connected to the source, and the node N5 is electrically connected to the drain.

In addition, there may be a plurality of voltage conditions of the power supply potential VDDA and the power supply potential VDDB. For example, assuming that the threshold voltage of PMOS transistor PM2 is VthP, voltage signal V _N1 (see FIG. 11) whose initial state is H level is used as the gate when power supply potential VDDA <power supply potential VDDB and VDDB−VDDA <VthP. The received PMOS transistor PM2 is turned off because the potential difference between the gate and the source can not be sufficiently secured, and the node N2 is in a high impedance state. On the other hand, when the power supply potential VDDA <the power supply potential VDDB and VDDB−VDDA> VthP, the PMOS transistor PM2 can be sufficiently turned on because the potential difference between the gate and the source can be maintained, and the node N2 has a stable potential. That is, by switching the pull-up potential V _N2 at the node N2 in accordance with the relationship between the power supply potential VDDA and the power supply potential VDDB, it can improve the duty precision clock.

  Based on such an idea, the level shift circuit 1j further includes a control circuit 40j. Control circuit 40 j turns on pull-up switch PSW 1 and pull-up switch PSW 2 in accordance with the potential difference between power supply potential VDDA and power supply potential VDDB. Control circuit 40 j pulls up pull-up switch PSW 1 and pull-up switch PSW 1 in response to the potential difference between power supply potential VDDA and power supply potential VDDB being smaller than the threshold (for example, when power supply potential VDDA <power supply potential VDDB and VDDB−VDDA <VthP). The up switch PSW2 is turned on. Control circuit 40 j pulls up pull-up switch PSW 1 and pull-up switch PSW 1 in response to the potential difference between power supply potential VDDA and power supply potential VDDB being larger than the threshold (for example, when power supply potential VDDA <power supply potential VDDB and VDDB−VDDA> VthP). The up switch PSW2 is turned off.

  Specifically, the control circuit 40j has a potential difference detector 41j. The potential difference detector 41j starts its operation immediately before the rise of the first clock of the input clock φCK. The potential difference detector 41 j receives the bias potential VBN, and detects the potential difference between the power supply potential VDDA and the power supply potential VDDB using the bias potential VBN.

Potential difference detector 41j is continuously output from the node N11 to L level (pull-up ON) if VDDB-VDDA <VthP as a voltage signal _{V N11.} In response to this, PMOS transistors PM31, PM 32 are both turned on, the voltage signal _{V N11} PMOS transistor PM31 in the period in which the L level, PM 32 is kept on. As a result, the potentials of the nodes N2 and N5 are pulled up to the H level corresponding to the power supply potential VDDB.

Potential difference detector 41j is continuously output from the node N11 to the H level (pull-up OFF) if VDDB-VDDA> VthP as a voltage signal _{V N11.} In response to this, PMOS transistors PM31, PM 32 are both turned off, the voltage signal _{V N11} PMOS transistor PM31, PM 32 during a period in which the H level is maintained off. As a result, the potentials of the nodes N2 and N5 are not pulled up.

  For example, the potential difference detector 41j in the control circuit 40j is configured as shown in FIG. FIG. 10 is a circuit diagram showing a configuration of a control circuit 40j in the fourth embodiment. The potential difference detector 41j in the control circuit 40j includes a PMOS transistor PM41, an NMOS transistor NM41, and a Schmitt trigger 41j.

  The PMOS transistor PM41 and the NMOS transistor NM41 are electrically inserted between the power supply potentials VDDA and VDDB and the ground potential GND. The power supply potential VDDA is connected to the gate of the PMOS transistor PM41, the power supply potential VDDB is connected to the source, and the node N12 is connected to the drain. The bias potential VBN is connected to the gate of the NMOS transistor NM41, the ground potential GND is connected to the source, and the node N12 is connected to the drain. The Schmitt trigger 41j is electrically inserted between the node N12 between the PMOS transistor PM41 and the NMOS transistor NM41 and the note N11. In the Schmitt trigger 41j, the node N12 is connected to the input node, and the node N11 is connected to the output node. That is, the drain of the PMOS transistor PM41 and the drain of the NMOS transistor NM41 are electrically connected.

  The Schmitt trigger 41 j has an effect of preventing the erroneous determination of the detector due to the power supply noise by changing the circuit threshold of L → H and H → L.

  At this time, the level shift circuit 1j operates, for example, as shown in FIG. FIG. 11 is a waveform diagram showing an operation of the level shift circuit 1j according to the fourth embodiment, and illustrates an operation in the case where VDDB−VDDA <VthP.

At timing t201 before the rising timing t202 of the first clock of the clock φCK to be input, the potential difference detector 41j in the control circuit 40j detects that VDDB-VDDA <VthP, and accordingly, the node N11 The L level voltage signal V _N11 is continuously output. As a result, the pull-up switches PSW1 and PSW2 in the pull-up circuit 30j are maintained in the on state to pull up the nodes N2 and N5. As a result, the potentials V _N2 and V _N5 of the nodes N2 and N5 are pulled up to the side of the power supply potential VDDB, and become stable H level potentials.

At timing t202, potentials V _N2 and V _{N5 of} nodes N2 and N5 are stable at H level, so that rising of output clock φ CKout can be quickened when clock φ CK transitions from L level to H level. . Thereby, the duty of the first clock of the output clock φCKout can be improved.

  Thereafter, even if there is a leak or a gate voltage value of the PMOS transistor PM2, the potential of the node N2 can be stably maintained at the H level because the pull-up switches PSW1 and PSW2 pull up the nodes N2 and N5. .

Also at timing t203, potentials V _N2 and V _{N5 of} nodes N2 and N5 are stable at H level, so that rising of output clock φ CKout can be made faster when clock φ CK transitions from L level to H level. it can. Thus, the duty of the second clock of the output clock φCKout can be improved.

The operation for the third and subsequent clocks of clock φCK (for example, the operation at timing t204) is the same as the operation for the second clock of clock φCK (that is, the operation at timing t203). Further, the potentials V _N1 , V _N3 and V _N4 of the nodes N1, N3 and N4 change stably as shown in FIG.

  Alternatively, the level shift circuit 1j operates, for example, as shown in FIG. FIG. 12 is a waveform diagram showing another operation of the level shift circuit 1j according to the fourth embodiment, and illustrates an operation in the case where VDDB−VDDA> VthP.

At timing t301 before the rising timing t302 of the first clock of the clock φCK to be input, the potential difference detector 41j in the control circuit 40j detects that VDDB−VDDA> VthP, and accordingly, the node N11 And the H level voltage signal V _N11 is continuously output. As a result, although the pull-up switches PSW1 and PSW2 in the pull-up circuit 30j are maintained in the OFF state and do not pull up the nodes N2 and N5, the PMOS transistor PM2 can secure a sufficient potential difference between the gate and the source, thereby turning on The node N2 is at a stable H level potential. Accordingly, node N5 is at a stable H level potential.

At timing t302, potentials V _N2 and V _{N5 of} nodes N2 and N5 are stable at H level, so that rising of output clock φ CKout can be quickened when clock φ CK transitions from L level to H level. . Thereby, the duty of the first clock of the output clock φCKout can be improved.

  Thereafter, since the PMOS transistor PM2 is in a stable off state since a sufficient potential difference between the gate and the source can be maintained, the potential of the node N2 can be stably maintained at the H level.

At timing t303, potentials V _N2 and V _{N5 of} nodes N2 and N5 are stable at H level, so that rising of output clock φ CKout can be quickened when clock φ CK transitions from L level to H level. . Thus, the duty of the second clock of the output clock φCKout can be improved.

The operation for the third and subsequent clocks of clock φCK (for example, the operation at timing t304) is the same as the operation for the second clock of clock φCK (that is, the operation at timing t303). Further, the potentials V _N1 , V _N3 and V _N4 of the nodes N1, N3 and N4 change stably as shown in FIG.

  Alternatively, as shown in FIG. 13, a control circuit 40k may be provided which has a simpler structure than the control circuit 40j shown in FIGS. FIG. 13 is a circuit diagram showing a configuration of the level shift circuit according to the fifth embodiment. The present invention is applicable to the case where the relationship between the power supply potential VDDA and the power supply potential VDDB is predetermined and can be externally controlled.

  Based on such an idea, the control circuit 40k has a PMOS transistor PM42 and an NMOS transistor NM42 instead of the PMOS transistor PM41, the NMOS transistor NM41, and the Schmitt trigger 41j (see FIG. 10). The PMOS transistor PM42 and the NMOS transistor NM42 are inverter-connected and electrically inserted between the power supply potential VDDB and the ground potential GND. In the PMOS transistor PM42, the node N13 is connected to the gate, the power supply potential VDDB is connected to the source, and the node N12 is connected to the drain. In the NMOS transistor NM42, the node N13 is connected to the gate, the ground potential GND is connected to the source, and the node N12 is connected to the drain. That is, the drain of the PMOS transistor PM42 and the drain of the NMOS transistor NM42 are electrically connected. The control signal φEN3 is externally supplied to the node N13. Control signal φEN 3 can be generated externally and supplied to control circuit 40 k so as to maintain L level in a period of VDDB-VDDA> VthP and maintain H level in a period of VDDB-VDDA <VthP. A signal in which the polarity of control signal φEN3 supplied to node N13 is inverted is output to node N12.

With such a configuration, the control circuit 40k is <if VthP can continuously output the L level (pull-up ON) from the node N11 as a voltage signal _{V N11, VDDB-VDDA> VDDB} -VDDA if VthP The H level (pull-up OFF) can be continuously output from the node N11 as the voltage signal _VN11 . In addition, since the control circuit 40k having a simplified structure as compared with the control circuit 40j shown in FIGS. 9 and 10 is provided, the circuit area of the control circuit 40k can be reduced.

In level shift circuit 1k shown in FIG. 13, when power supply potential VDDA <power supply potential VDDB and VDDB−VDDA <VthP, PMOS transistor PM2 receiving at its gate voltage signal V _N1 which is at the H level in the initial state is The potential difference between the two can not be sufficiently secured, leading to an incomplete off state (weak on state). In this case, if the NMOS transistor NM2 that constitutes the inverter INV3 together with the PMOS transistor PM2 is in the ON state, there is a concern that the leakage current may increase due to the incomplete OFF state of the PM2.

  In order to reduce such leakage current, the level shift circuit 1p can be configured, for example, as shown in FIG. FIG. 14 is a diagram showing a configuration of the level shift circuit 1p according to the sixth embodiment. The level shift circuit 1p has a level shifter 20p in place of the level shifter 20 (see FIG. 9). In the level shifter 20p, the connection positions of the PMOS transistor PM2p and the PMOS transistor PM3p are switched with respect to the level shifter 20 (see FIG. 9), and the connection positions of the PMOS transistor PM5p and the PMOS transistor PM6p are switched. That is, the PMOS transistor PM3p is electrically inserted between the PMOS transistor PM2p and the NMOS transistor NM2 in the inverter INV3p, and the PMOS transistor PM6p is electrically inserted between the PMOS transistor PM5p and the NMOS transistor NM4 in the inverter INV4p.

  In the inverter INV3p, the PMOS transistor PM2p has the gate connected to the node N1, the power supply potential VDDB connected to the source, and the node N2p connected to the drain. In the PMOS transistor PM3p, the node N4p is connected to the gate, the node N2p is connected to the source, and the node N0p is connected to the drain. That is, the drain of the PMOS transistor PM2p and the source of the PMOS transistor PM3p are electrically connected. In the inverter INV4p, the PMOS transistor PM5p has the gate connected to the node N3, the power supply potential VDDB connected to the source, and the node N5p connected to the drain. In the PMOS transistor PM6p, the node N0p is connected to the gate, the node N5p is connected to the source, and the node N4p is connected to the drain. That is, the drain of the PMOS transistor PM5p and the source of the PMOS transistor PM6p are electrically connected.

  As a result, the PMOS transistors PM3p and PM6p, which are the counterparts of the cross coupling connection to the inverters INV3p and INV4p, can be reliably turned off at the VDDB potential to reduce the leakage current.

  Alternatively, as shown in FIG. 15, a control circuit 40k may be provided which has a simpler structure than the control circuit 40j shown in FIGS. FIG. 15 is a circuit diagram showing a configuration of a level shift circuit 1q according to a seventh embodiment. The level shift circuit 1 q has a control circuit 40 k instead of the control circuit 40 j (see FIG. 14). The control circuit 40k has a PMOS transistor PM42 and an NMOS transistor NM42 in place of the PMOS transistor PM41, the NMOS transistor NM41, and the Schmitt trigger 41j (see FIG. 10). The PMOS transistor PM42 and the NMOS transistor NM42 are inverter-connected and electrically inserted between the power supply potential VDDB and the ground potential GND. In the PMOS transistor PM42, the node N13 is connected to the gate, the power supply potential VDDB is connected to the source, and the node N12 is connected to the drain. In the NMOS transistor NM42, the node N13 is connected to the gate, the ground potential GND is connected to the source, and the node N12 is connected to the drain. The control signal φ EN3 is supplied from the outside (host or core) to the node N13. Control signal φEN 3 can be generated externally and supplied to control circuit 40 k so as to maintain L level in a period of VDDB-VDDA> VthP and maintain H level in a period of VDDB-VDDA <VthP.

With such a configuration, the control circuit 40k is <if VthP can continuously output the L level (pull-up ON) from the node N11 as a voltage signal _{V N11, VDDB-VDDA> VDDB} -VDDA if VthP The H level (pull-up OFF) can be continuously output from the node N11 as the voltage signal _VN11 . In addition, since the control circuit 40k is simplified in configuration as compared with the control circuit 40j shown in FIGS. 9 and 10, the circuit area of the control circuit 40k can be reduced.

  While certain embodiments of the present invention have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the scope of the invention. These embodiments and modifications thereof are included in the scope and the gist of the invention, and are included in the invention described in the claims and the equivalent scope thereof.

  1, 1i, 1j, 1k, 1p, 1q Level shift circuit, 30, 30i charge circuit, 30j pull-up circuit, 40j, 40k control circuit, PG pulse generator, PSW1, PSW2 pull-up switch, SW switch.

Claims (20)

A first node to which a first signal having an amplitude of the first power supply potential is input is electrically connected to the gate, and a second node is electrically connected to the source, which is different from the first power supply potential A first PMOS transistor of which the output terminal to which a signal having the amplitude of the second power supply potential is output is electrically connected to the drain;
A first NMOS transistor having the first node electrically connected to the gate and the output terminal electrically connected to the drain;
A second PMOS transistor having a third node electrically connected to its gate, said second power supply potential electrically connected to its source, and said second node electrically connected to its drain;
A fourth node having an amplitude of the first power supply potential and receiving a second signal logically inverted with respect to the first signal is electrically connected to a gate, and a fifth node is electrically connected to a source A third PMOS transistor connected to the third PMOS transistor and the third node electrically connected to the drain;
A second NMOS transistor in which the fourth node is electrically connected to the gate and the third node is electrically connected to the drain;
A fourth PMOS transistor in which the output terminal is electrically connected to the gate, the second power supply potential is electrically connected to the source, and the fifth node is electrically connected to the drain;
A potential adjusting circuit electrically connected to at least the second node;
Level shift circuit with. The level shift circuit according to claim 1, wherein the potential adjustment circuit is a charging circuit electrically connected to the second node. The level shift circuit according to claim 2, wherein the charging circuit includes a switch electrically inserted between the second power supply potential and the second node. The switch is maintained in an on state in a first period from a first timing at which the output terminal transitions from a first level to a second level to the first timing, and continues to the first period. The level shift circuit according to claim 3, maintained in the off state in the second period. The switch is arranged in a third period prior to a second timing at which the output terminal transitions from the first level to the second level after the first timing. 5. The level shift circuit according to claim 4, wherein the level shift circuit is maintained in the on state, and is maintained in the off state in a fourth period following the third period. 5. The level shift circuit according to claim 3, further comprising a pulse generator electrically connected to a control node of the switch. The pulse generator is
A logic circuit having a first input node and a second input node;
A line connected to the first input node;
A delay line connected to the second input node and including a delay element and a MOS transistor functioning as a load capacitance;
The level shift circuit according to claim 6, comprising The level shift circuit according to any one of claims 3 to 7, wherein a voltage corresponding to the second power supply potential is supplied to the second node via the switch. The level shift circuit according to claim 1, wherein the potential adjustment circuit is a pull-up circuit electrically connected to the second node and the fifth node. The pull-up circuit is
A first pull-up switch electrically inserted between the second power supply potential and the second node;
A second pull-up switch electrically inserted between the second power supply potential and the fifth node;
The level shift circuit according to claim 9, comprising: The level shift circuit further includes a control circuit that turns on the first pull-up switch and the second pull-up switch according to a potential difference between the first power supply potential and the second power supply potential. The level shift circuit according to claim 10. The control circuit turns on the first pull-up switch and the second pull-up switch in response to a potential difference between the first power supply potential and the second power supply potential being smaller than a threshold. 11. The level shift circuit according to 11. The control circuit turns off the first pull-up switch and the second pull-up switch in response to a potential difference between the first power supply potential and the second power supply potential being greater than the threshold. Item 13. The level shift circuit according to item 12. The first node to which the first signal having the amplitude of the first power supply potential is input is electrically connected to the gate, the second power supply potential is electrically connected to the source, and the second node is connected to the drain A first PMOS transistor electrically connected,
A first node having the first node electrically connected to the gate, and an output terminal outputting a signal having an amplitude of a second power supply potential different from the first power supply potential electrically connected to a drain NMOS transistor,
A second PMOS transistor having a third node electrically connected to the gate, the second node electrically connected to the source, and the output terminal electrically connected to the drain;
A fourth node having an amplitude of the first power supply potential and to which a second signal logically inverted with respect to the first signal is input is electrically connected to a gate, and the second power supply potential is a source. A third PMOS transistor electrically connected and the fifth node electrically connected to the drain;
A second NMOS transistor in which the fourth node is electrically connected to the gate and the third node is electrically connected to the drain;
A fourth PMOS transistor in which the output terminal is electrically connected to the gate, the fifth node is electrically connected to the source, and the third node is electrically connected to the drain;
A potential adjustment circuit electrically connected to the second node and the fifth node;
Level shift circuit with. 15. The level shift circuit according to claim 14, wherein the potential adjustment circuit is a pull-up circuit that pulls up the potential of the second node and pulls up the potential of the fifth node. The pull-up circuit is
A first pull-up switch electrically inserted between the second power supply potential and the second node;
A second pull-up switch electrically inserted between the second power supply potential and the fifth node;
The level shift circuit according to claim 15, comprising The level shift circuit further includes a control circuit that turns on the first pull-up switch and the second pull-up switch according to a potential difference between the first power supply potential and the second power supply potential. The level shift circuit according to claim 16. The control circuit turns on the first pull-up switch and the second pull-up switch in response to a potential difference between the first power supply potential and the second power supply potential being smaller than a threshold. The level shift circuit according to 17. The control circuit turns off the first pull-up switch and the second pull-up switch in response to a potential difference between the first power supply potential and the second power supply potential being greater than the threshold. Item 19. The level shift circuit according to item 18. The level shift circuit according to claim 1, wherein the second power supply potential is higher than the first power supply potential.

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