CN111106174A - 包括功能层的半导体器件及其制造方法 - Google Patents

包括功能层的半导体器件及其制造方法 Download PDF

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CN111106174A
CN111106174A CN201911004608.0A CN201911004608A CN111106174A CN 111106174 A CN111106174 A CN 111106174A CN 201911004608 A CN201911004608 A CN 201911004608A CN 111106174 A CN111106174 A CN 111106174A
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gate
semiconductor device
region
isolation layer
device isolation
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CN111106174B (zh
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林杠默
金相秀
朴雨锡
许盛祺
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Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
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Abstract

一种半导体器件，包括：基板；有源区，设置在基板上并沿第一方向延伸；与有源区相邻的器件隔离层；设置在有源区中的栅极结构，该栅极结构沿与第一方向交叉的第二方向延伸并覆盖器件隔离层的一部分；栅极分离图案，接触栅极结构的端部；以及杂质区，设置在栅极分离图案下方并在器件隔离层上。

Description

包括功能层的半导体器件及其制造方法
技术领域
本公开的示例实施方式涉及半导体器件，更具体地，涉及包括功能层的半导体器件及其制造方法。
背景技术
对高度集成、高性能、高速、多功能的半导体器件的需求已经增加。高度集成的半导体器件可以包括具有最小宽度或其间具有最小间隔的图案。为了克服短沟道效应，已经提出了具有三维沟道的鳍型场效应晶体管(FinFET)或栅极全包围(GAA)晶体管。
发明内容
根据本发明构思的示例实施方式，半导体器件可以包括基板、设置在基板上并沿第一方向延伸的有源区。器件隔离层可以与有源区相邻设置。栅极结构可以设置在有源区上。栅极结构可以沿与第一方向交叉的第二方向延伸并覆盖器件隔离层的一部分。栅极分离图案可以接触栅极结构的端部。杂质区可以设置在栅极分离图案下方并在器件隔离层中。
根据本发明构思的示例实施方式，半导体器件可以包括基板和设置在基板上的多个有源区。器件隔离层可以与多个有源区相邻设置。多个栅极结构可以至少部分地交叠多个有源区并且接触器件隔离层。栅极分离图案可以设置在多个栅极结构中相邻的栅极结构之间并在器件隔离层上。低蚀刻速率区可以设置在栅极分离图案和器件隔离层之间，其中低蚀刻速率区具有比器件隔离层低的蚀刻速率。
根据本发明构思的示例实施方式，制造半导体器件的方法可以包括：在基板上形成鳍结构，该鳍结构包括交替堆叠的多个牺牲层和多个沟道层；形成至少部分地围绕鳍结构的下部的器件隔离层；在鳍结构上形成虚设栅极结构并延伸到器件隔离层上；在虚设栅极结构的相对侧形成源极/漏极；在虚设栅极结构中形成开口；通过该开口将杂质注入器件隔离层以形成杂质区。杂质区具有比器件隔离层低的蚀刻速率。
附图说明
图1是示出根据本公开示例实施方式的半导体器件的布局图；
图2是沿图1的线I-I'和II-II'截取的剖视图，示出了根据本公开示例实施方式的半导体器件；
图3和图4是示出根据本公开示例实施方式的半导体器件的一部分的剖视图，并且是图2的部分“A”的放大视图；
图5至图12是示出根据本公开示例实施方式的制造半导体器件的方法的剖视图，并且对应于沿图1的线I-I'和II-II'截取的剖视图；
图13是示出根据本公开示例实施方式的半导体器件的布局图；
图14是沿图13的线III-III'和IV-IV'截取的剖视图，示出了根据示例实施方式的半导体器件；以及
图15至图20是根据本公开示例实施方式的制造半导体器件的方法的剖视图，并且对应于沿图13的线III-III'和IV-IV'截取的剖视图。
具体实施方式
现在将参考附图更全面地描述本公开的示例实施方式。然而，本发明构思可以以许多替代形式实施，并且不应该被解释为仅限于这里阐述的本公开的示例实施方式。
图1是示出根据本公开示例实施方式的半导体器件的布局图。图2是沿图1的线I-I'和II-II'截取的剖视图，示出了根据本公开示例实施方式的半导体器件。
参照图1，根据本公开的示例实施方式的半导体器件可以包括提供在基板11(如图2所示)上的逻辑标准单元SCL。逻辑标准单元SCL每个可以包括第一器件区R1、第二器件区R2、在第一器件区R1和第二器件区R2之间的分离区SR、与第一器件区R1相邻的第一电源轨区PR1、以及与第二器件区R2相邻的第二电源轨区PR2。
N型晶体管TN可以设置在第一器件区R1中，p型晶体管TP可以设置在第二器件区R2中。n型晶体管TN和p型晶体管TP每个可以是栅极全包围结构(GAA)的晶体管。
在第一器件区R1中，第一下部有源区ARN沿第一方向X延伸。第一栅极结构GSN沿与第一方向X交叉的第二方向Y延伸，以与第一下部有源区ARN交叉。第一源极/漏极SD可以设置在第一栅极结构GSN之间。第二器件区R2可以包括沿第一方向X延伸的第二下部有源区ARP、沿第二方向Y延伸以与第二下部有源区ARP交叉的第二栅极结构GSP、以及设置在第二栅极结构GSP之间的第二源极/漏极SG。第一沟道层ACN可以设置在第一源极/漏极SD之间的第一下部有源区ARN上。第一栅极结构GSN可以至少部分地围绕第一沟道层ACN。第二沟道层ACP可以设置在第二源极/漏极SG之间的第二下部有源区ARP上。第二栅极结构GSP可以至少部分地围绕第二沟道层ACP。第一下部有源区ARN和第一沟道层ACN可以包括p型掺杂剂。第二下部有源区ARP和第二沟道层ACP可以包括n型掺杂剂。第一源极/漏极SD可以包括n型掺杂剂，第二源极/漏极SG可以包括p型掺杂剂。
n型晶体管TN每个可以包括第一沟道层ACN、第一栅极结构GSN和第一源极/漏极SD。p型晶体管TP每个可以包括第二沟道层ACP、第二栅极结构GSP和第二源极/漏极SG。
第一栅极结构GSN和第二栅极结构GSP可以在分离区SR中彼此接触。
半导体器件可以包括设置在第一电源轨区PR1和第二电源轨区PR2中的栅极分离图案80。
栅极分离图案80可以分别设置在在第二方向Y上彼此相邻的第一栅极结构GSN之间以及在第二方向Y上彼此相邻的第二栅极结构GSP之间。相邻的第一栅极结构GSN的相对端部可以接触第一电源轨区PR1中的栅极分离图案80，并且相邻的第二栅极结构GSP的相对端部可以接触第二电源轨区PR2中的栅极分离图案80。
间隔物85可以设置在第一栅极结构GSN的侧壁和第二栅极结构GSP的侧壁上。间隔物85可以沿着第一栅极结构GSN的侧壁和第二栅极结构GSP的侧壁在第二方向Y上连续延伸。
设置在第一栅极结构GSN之间的第一源极/漏极SD以及在第二栅极结构GSP之间的第二源极/漏极SG可以接触间隔物85。
接触插塞可以设置在第一源极/漏极SD上和第二源极/漏极SG上。
在第一电源轨区PR1中，第一电源轨可以设置为在第一方向X上平行于第一下部有源区ARN延伸，并且在第二电源轨区PR2中，第二电源轨可以设置为平行于第二下部有源区ARP延伸。第一电源轨和第二电源轨可以位于比第一和第二栅极结构GSN和GSP的上表面更高的水平。或者，第一电源轨和第二电源轨可以位于比第一和第二栅极结构GSN和GSP的下表面低的水平。第一电源轨和第二电源轨可以包括导电材料，例如金属。第一电源轨和第二电源轨可以提供电源电压或接地电压。例如，第一电源轨可以提供电源电压，第二电源轨可以提供接地电压。
参照图2，半导体器件可以包括基板11。第二下部有源区ARP可以从基板11突出，并且器件隔离层15可以设置在第二下部有源区ARP之间。第二沟道层ACP可以在第二下部有源区ARP上以预定垂直间隔在第三方向Z上间隔开布置。第二栅极结构GSP可以围绕第二沟道层ACP并且可以在第二方向Y上彼此相邻地布置。栅极分离图案80可以设置在第二栅极结构GSP之间。杂质区17可以设置在栅极分离图案80下方。根据本公开的示例实施方式，杂质区17可以在X方向上具有与栅极分离图案80基本相同的宽度。第二源极/漏极SG可以设置在第二栅极结构GSP之间并且接触第二沟道层ACP。例如，第二源极/漏极SG可以在第一方向X上设置在平行的第二栅极结构GSP之间。栅极覆盖层75可以设置在每个第二栅极结构GSP上。每个第二栅极结构GSP可以包括第二栅电极GP、以及设置在第二栅电极GP和每个第二沟道层ACP之间的栅极绝缘层GI。例如，当在由第二方向Y和第三方向Z形成的平面上观察时，栅极绝缘层GI可以基本上覆盖每个第二沟道层ACP的整个表面。
基板11可以包括IV族半导体(诸如硅、锗、硅锗)、III-V族化合物半导体和/或II-VI族化合物半导体。在本公开的一些示例实施方式中，基板11可以是绝缘体上硅(SOI)基板或绝缘体上锗(GOI)基板。
第二沟道层ACP可以各自包括纳米片，其宽度大于厚度。例如，在第二方向Y上的延伸长度可以超过在第三方向Z上的延伸长度。第二沟道层ACP可以包括半导体材料，例如硅和/或锗。第二沟道层ACP的数量可以如图2所示(在每个第二下部有源区ARP上堆叠三个)，但是本公开不限于此。
第二栅极结构GSP可以每个围绕第二沟道层ACP，并且可以在第二方向Y上至少部分地交叠器件隔离层15。
第二栅电极GP可以包括金属、金属氮化物和/或掺杂的多晶硅。在本公开的示例实施方式中，第二栅电极GP可以包括钛氮化物(TiN)、钛铝(TiAl)、钛铝氮化物(TiAlN)、钽氮化物(TaN)、钽铝氮化物(TaAlN)、钛铝碳化物(TiAlC)和/或钨氮化物(WN)。
栅极绝缘层GI可以至少部分地围绕第二沟道层ACP的表面。例如，当在由第二方向Y和第三方向Z形成的平面上观察时，栅极绝缘层GI可以基本上包围第二沟道层ACP的整个周边。栅极绝缘层GI可以进一步设置在第二下部有源区ARP和第二栅电极GP之间、在第二栅电极GP和器件隔离层15之间、以及在第二栅电极GP和栅极分离图案80之间。栅极绝缘层GI可以包括硅氧化物、硅氮化物、硅氮氧化物和/或高k电介质材料中的至少一种。高k电介质材料可以是具有高于硅氧化物的介电常数的电介质材料，例如铝氧化物(Al2O3)、钽氧化物(Ta2O3)、钛氧化物(TiO2)、钇氧化物(Y2O3)、锆氧化物(ZrO2)、锆硅氧化物(ZrSixOy)、铪氧化物(HfO2)、铪硅氧化物(HfSixOy)、镧氧化物(La2O3)、镧铝氧化物(LaAlxOy)、镧铪氧化物(LaHfxOy)、铪铝氧化物(HfAlxOy)和/或镨氧化物(Pr2O3)。
界面绝缘层可以进一步设置在每个第二沟道层ACP和栅极绝缘层GI之间。界面绝缘层可以包括氧化物，诸如硅氧化物。
栅极分离图案80可以设置在沿第二方向Y彼此相邻的第二栅极结构GSP之间。相邻的第二栅极结构GSP的相对端部可以接触栅极分离图案80。栅极分离图案80可以例如包括硅氮化物、硅氮氧化物和/或其组合。栅极分离图案80可以包括堆叠的下层和上层。例如，下层可以由硅氮化物形成，上层可以由硅氧化物形成。
具有低于器件隔离层15的蚀刻速率的蚀刻速率的杂质区17可以形成在栅极分离图案80下方。杂质区17可以指低蚀刻速率区。例如，器件隔离层15可以包括硅氧化物，并且杂质区17还可以包括Si、B、He、P、C和/或它们的组合。杂质区17可以包括浓度为1×1019原子/cm3或更高的杂质。例如，杂质区17可以包括浓度为1×1020原子/cm3至1×1022原子/cm3的杂质。
第二沟道层ACP可以设置在第二源极/漏极SG之间，并且第二源极/漏极SG可以接触第二沟道层ACP。源极/漏极SG可以由例如包括(掺杂有)硼(B)的硅锗形成。源极/漏极SG可以每个包括包含不同的锗组分的多个硅锗层。多个硅锗层可以包括不同的硼浓度。
间隔物85可以设置在每个第二栅极结构GSP的侧壁上，并且可以由绝缘材料形成。栅极覆盖层75可以包括例如氮化物，如硅氮化物。
接触插塞可以设置在第二源极/漏极SG上。接触插塞可以穿透层间绝缘层60以接触第二源极/漏极SG。层间绝缘层60可以包括例如硅氧化物。
图3和4是根据示例实施方式的半导体器件的一部分的剖视图，并且是图2的部分“A”的放大视图。
参照图3，杂质区17的上表面可以接触栅极分离图案80的下表面，并且杂质区17的下部可以具有比栅极分离图案80的宽度大的宽度。例如，栅极分离图案80的下表面可以包括与杂质区17的下部在第二方向Y上的宽度相比在第二方向Y上更窄的宽度。杂质区17的侧壁可以包括台阶部分。杂质区17的上表面可以高于器件隔离层15的被第二栅极结构GSP覆盖(或接触第二栅极结构GSP)的部分的上表面。第二栅极结构GSP的下表面可以低于栅极分离图案80的下表面。
参照图4，杂质区17的上表面可以接触栅极分离图案80的下表面，并且杂质区17的上部可以具有比栅极分离图案80的宽度小的宽度。例如，这里使用的术语“宽度”可以指第二方向Y上的延伸长度。杂质区17的侧壁可以包括台阶部分。杂质区17的上表面可以高于器件隔离层15的被第二栅极结构GSP覆盖(或接触第二栅极结构GSP)的部分的上表面。第二栅极结构GSP的下表面可以低于栅极分离图案80的下表面。例如，第二栅极结构GSP的一部分可以在栅极分离图案80的下表面下方延伸并且至少部分地围绕栅极分离图案80的下表面。第二栅极结构GSP的该部分可以设置在栅极分离图案80与杂质区17的下部之间。
尽管根据本公开的杂质区17的示例实施方式已经在附图中示出并且如上所述，但是应当理解，本公开不限于此。例如，杂质区17可以包括各种形状，诸如在Z方向上延伸并连接到栅极分离图案80的锥形部分或片状结构。
图5至图12是根据本公开示例实施方式的制造半导体器件的方法的剖视图，并且分别对应于沿图1中的线I-I'和II-II'截取的剖视图。
参照图5，多个牺牲材料层ASPa和多个沟道材料层ACPa可以交替地堆叠在基板11上。
例如，可以首先在基板11上形成第一牺牲材料层ASPa，并且可以在第一牺牲材料层ASPa上形成第一沟道材料层ACPa。接下来，可以在第一沟道材料层ACPa上形成第二牺牲材料层ASPa。此后，可以在第二牺牲材料层ASPa上形成第二沟道材料层ACPa。如图5所示，可以在基板11上形成三个牺牲材料层ASPa和三个沟道材料层ACPa，但是发明构思不限于此。可以不同地改变牺牲材料层ASPa和沟道材料层ACPa的数量。
多个沟道材料层ACPa可以包括半导体材料，并且可以包括具有与牺牲材料层ASPa不同的蚀刻选择性的材料。多个沟道材料层ACPa可以包括硅。多个牺牲材料层ASPa可以包括硅锗。例如，多个牺牲材料层ASPa可以每个包括具有30％的锗含量的硅锗。
根据示例实施方式，可以改变每个沟道材料层ACPa的厚度和每个牺牲材料层ASPa的厚度。例如，每个沟道材料层ACPa和每个牺牲材料层ASPa可以具有几纳米到几十纳米量级的厚度。例如，每个厚度可以在1nm和100nm之间。每个牺牲材料层ASPa的厚度可以大于每个沟道材料层ACPa的厚度。
参照图6，多个沟道材料层ACPa的部分和多个牺牲材料层ASPa的部分以及基板11的一部分可以被蚀刻以形成鳍结构FS。鳍结构FS可以在基板11上沿第一方向X延伸。
通过在其上形成有多个沟道材料层ACPa和多个牺牲材料层ASPa的基板11上形成掩模图案并执行各向异性蚀刻工艺，可以形成鳍结构FS。鳍结构FS可以包括彼此交替堆叠的多个沟道层ACP和多个牺牲层ASP。在形成鳍结构FS的工艺中，基板11的一部分可以被蚀刻以形成从基板11突出的下部有源区(即，第二下部有源区)ARP。基板11的下部有源区ARP可以包括包含多个沟道层ACP和多个牺牲层ASP的鳍结构FS。多个沟道层ACP可以指上部有源区。器件隔离层15可以形成在基板11的该部分被蚀刻的区域中。器件隔离层15可以部分地覆盖下部有源区ARP的侧壁。器件隔离层15的上表面可以低于下部有源区ARP的上表面。例如，下部有源区ARP的上部可以突出到器件隔离层15之上。器件隔离层15可以包括硅氧化物。
在形成鳍结构FS和器件隔离层15之后，可以去除掩模图案。
参照图7，虚设栅极结构SGS可以形成为横过鳍结构FS。间隔物85可以形成在虚设栅极结构SGS的侧壁上。虚设栅极结构SGS每个可以包括虚设栅电极PG和在虚设栅电极PG与鳍结构FS之间的虚设绝缘层IN。覆盖层25可以形成在虚设栅电极PG上。
虚设栅极结构SGS可以以预定间隔在第一方向X上间隔开布置。虚设栅极结构SGS可以覆盖鳍结构FS的上部和器件隔离层15并且可以沿第二方向Y延伸。间隔物85可以平行于每个虚设栅极结构SGS延伸。例如，间隔物85可以沿第二方向Y延伸并且至少部分地交叠虚设栅极结构SGS。
虚设栅电极PG可以由诸如多晶硅的半导体材料形成。虚设绝缘层IN可以由硅氧化物形成。间隔物85可以由硅氮氧化物(SiON)、硅氮化物(SiN)、SiOC、SiOCN和/或SiBCN形成。
参照图8，通过使用覆盖层25、虚设栅极结构SGS和间隔物85作为蚀刻掩模的各向异性干蚀刻工艺，可以去除鳍结构FS的一部分，以在虚设栅极结构SGS之间形成凹陷。
通过使用各向异性干蚀刻工艺去除多个沟道层ACP和多个牺牲层ASP的部分，可以形成凹槽。下部有源区ARP可以通过凹槽被暴露。通过各向异性蚀刻工艺可以蚀刻下部有源区ARP的一部分。
参照图9，通过使用下部有源区ARP作为籽晶的选择性外延生长工艺可以在凹槽中形成源极/漏极(即，第二源极/漏极)SG。
源极/漏极SG可以掺杂有p型杂质。p型杂质可以在选择性外延生长工艺期间被原位注入，或者可以通过随后的离子注入工艺被注入。源极/漏极SG可以由包括硼(B)的硅锗形成。源极/漏极SG可以由具有不同锗含量的多个硅锗层形成。多个硅锗层可以包括彼此不同的硼浓度。层间绝缘层60可以填充间隔物85之间的空间。
参照图10，覆盖层25和虚设栅电极PG可以被蚀刻以形成第一开口OP1。
通过在覆盖层25和层间绝缘层60上形成掩模图案并且通过使用该掩模图案作为蚀刻掩模的各向异性蚀刻工艺蚀刻覆盖层25和虚设栅电极PG，可以形成第一开口OP1。第一开口OP1可以暴露器件隔离层15。在形成第一开口OP1之后可以去除掩模图案。
杂质可以通过离子注入工艺被注入到暴露的器件隔离层15的上部以形成杂质区17。杂质可以包括Si、B、He、P和/或C。例如，器件隔离层15可以包括硅氧化物，并且与器件隔离层15相比，杂质区17还可以包括Si、B、He、P和/或C。
杂质区17可以具有1×1019原子/cm3或更高的杂质浓度。例如，杂质区17可以具有1×1020原子/cm3至1×1022原子/cm3的杂质浓度。
参照图11，栅极分离图案80可以形成在第一开口OP1中。
通过将绝缘材料沉积到第一开口OP1中并对绝缘材料执行平坦化工艺可以形成栅极分离图案80。通过平坦化工艺，可以去除覆盖层25并且可以暴露虚设栅电极PG。栅极分离图案80的下表面可以接触杂质区17。栅极分离图案80可以包括堆叠的下层和上层。例如，下层可以由硅氮化物形成，上层可以由硅氧化物形成。
参照图12，第二开口OP2可以被形成以暴露多个沟道层ACP。
虚设栅电极PG和虚设绝缘层IN可以被顺序地去除，然后多个牺牲层ASP可以相对于多个沟道层ACP被选择性地去除。
例如，多个沟道层ACP可以包括硅，并且多个牺牲层ASP可以包括硅锗。为了选择性地去除多个牺牲层ASP，可以使用具有对于硅锗的蚀刻速率高于对于硅的蚀刻速率的蚀刻剂。例如，为了选择性地去除多个牺牲层ASP，可以使用包含过氧化氢(H2O2)、氢氟酸(HF)和乙酸(CH3COOH)的蚀刻溶液，包含氢氧化铵(NH4OH)、过氧化氢(H2O2)和去离子水(H2O)的蚀刻溶液和/或包含过乙酸的蚀刻溶液。
由于杂质区17具有比器件隔离层15的蚀刻速率低的蚀刻速率，所以可以防止在栅极分离图案80下方的器件隔离层15被过蚀刻。
返回参考图2，栅极绝缘层GI和栅电极(即，第二栅电极)GP可以顺序地形成在第二开口OP2中。
栅极绝缘层GI可以形成在由第二开口OP2暴露的间隔物85的内表面、沟道层ACP的表面、源极/漏极SG的表面的部分上。栅极绝缘层GI可以围绕沟道层ACP。栅极绝缘层GI可以包括顺序堆叠并具有不同介电常数的第一绝缘层和第二绝缘层。第二绝缘层的介电常数可以大于第一绝缘层的介电常数。第一绝缘层可以是硅氧化物层，第二绝缘层可以是高k电介质层。
栅电极GP可以形成在栅极绝缘层GI上。栅电极GP可以包括金属、金属氮化物和/或掺杂的多晶硅。
返回参考图2，栅极覆盖层75可以形成在栅电极GP上。栅极覆盖层75可以由硅氮化物形成。栅极覆盖层75可以用作保护层以防止氧等穿透栅电极GP，使得阈值电压不改变。
栅电极GP的一部分可以被去除，然后栅极覆盖层75可以形成在栅电极的该部分被去除的区域中。
图13是示出根据本公开示例实施方式的半导体器件的布局图。图14是沿图13中的线III-III'和IV-IV'截取的剖视图，示出了根据本公开示例实施方式的半导体器件。
参照图13，根据本公开的示例实施方式的半导体器件可以包括逻辑标准单元SCL。逻辑标准单元SCL可以每个包括第一器件区R1、第二器件区R2、在第一器件区R1和第二器件区R2之间的分离区SR、与第一器件区R1相邻的第一电源轨区PR1、以及与第二器件区R2相邻的第二电源轨区PR2。
n型晶体管TN可以设置在第一器件区R1中，并且p型晶体管TP可以设置在第二器件区R2中。n型晶体管TN和p型晶体管TP每个可以是鳍型场效应晶体管(FinFET)。
在第一器件区R1中，可以形成沿第一方向X延伸的第一鳍型有源区AFN、横过第一鳍型有源区AFN并沿第二方向Y延伸的第一栅极结构GSN、在第一栅极结构GSN之间的第一鳍型有源区AFN上的第一源极/漏极SD。在第二器件区R2中，可以形成沿第一方向X延伸的第二鳍型有源区AFP、横过第二鳍型有源区AFP并沿第二方向Y延伸的第二栅极结构GSP、在第二栅极结构GSP之间的第二鳍型有源区AFP上的第二源极/漏极SG。
在图13的所示示例中，两个第一鳍型有源区AFN可以设置在第一器件区R1中，并且两个第二鳍型有源区AFP可以设置在第二器件区R2中。可以改变第一鳍型有源区AFN和第二鳍型有源区AFP的数量。第一鳍型有源区AFN和第二鳍型有源区AFP可以从基板(参见图14的11)突出。第一鳍型有源区AFN可以包括第一有源鳍，第二鳍型有源区AFP可以包括第二有源鳍。第一鳍型有源区AFN和第二鳍型有源区AFP可以包括硅和/或锗。
n型晶体管TN可以包括第一鳍型有源区AFN、第一栅极结构GSN和第一源极/漏极SD。p型晶体管TP可以包括第二鳍型有源区AFP、第二栅极结构GSP和第二源极/漏极SG。
栅极分离图案80可以设置在沿第二方向Y彼此相邻的第一栅极结构GSN之间以及在沿第二方向Y彼此相邻的第二栅极结构GSP之间。
间隔物85可以设置在第一栅极结构GSN的侧壁和第二栅极结构GSP的侧壁上。
第一源极/漏极SD和第二源极/漏极SG可以接触间隔物85。
参照图14，半导体器件可以包括第二下部有源区ARP、从第二下部有源区ARP突出的第二鳍型有源区AFP、设置在第二鳍型有源区AFP之间和第二下部有源区ARP之间的器件隔离层15、覆盖第二鳍型有源区AFP的上部的第二栅极结构GSP、设置在第二栅极结构GSP之间的栅极分离图案80、设置在栅极分离图案80下方的杂质区17、以及设置在第二鳍型有源区AFP上的第二源极/漏极SG。器件隔离层15可以包括在第二鳍型有源区AFP之间的第一隔离层15s和设置在第二下部有源区ARP之间的第二隔离层15d。
基板11可以包括IV族半导体、III-V族化合物半导体或II-VI族化合物半导体。在本公开的一些实施方式中，基板11可以是绝缘体上硅(SOI)基板和/或绝缘体上锗(GOI)基板。
第二下部有源区ARP和第二鳍型有源区AFP可以包括n型掺杂剂。第二下部有源区ARP和第二鳍型有源区AFP可以包括IV族半导体、III-V族化合物半导体和/或II-VI族化合物半导体。
第二鳍型有源区AFP可以沿第一方向X延伸，并且第二栅极结构GSP可以覆盖第二鳍型有源区AFP的突出到器件隔离层15之上的上部并且可以沿交叉第一方向X的第二方向Y延伸。
栅极分离图案80可以设置在沿第二方向Y彼此相邻的第二栅极结构GSP之间。
杂质区17可以具有比器件隔离层15更低的蚀刻选择性，并且可以设置在栅极分离图案80下方。杂质区17可以指低蚀刻速率区域。
第二栅极结构GSP每个可以包括栅极绝缘层GI和栅电极GP。栅极绝缘层GI可以设置在第二鳍型有源区AFP的每个上部与栅电极GP之间、器件隔离层15和栅电极GP之间、以及栅极分离图案80的侧壁和栅电极GP之间。界面绝缘层可以进一步设置在每个第二鳍型有源区AFP与栅极绝缘层GI之间。
栅极绝缘层GI可以包括硅氧化物、硅氮化物、硅氮氧化物和/或高k电介质材料。栅电极GP可以由堆叠在栅极绝缘层GI上的多个层形成。栅电极GP的多个层中的至少一些可以由彼此不同的材料形成。
第二源极/漏极SG可以设置在第二鳍型有源区AFP中的凹陷区域中，并且可以沿第二方向Y延伸。第二源极/漏极SG可以形成为在设置在单个第二下部有源区ARP上的第二鳍型有源区AFP上彼此一体地联接，并且可以具有倾斜的上表面。
层间绝缘层60可以设置在第二源极/漏极SG上。接触插塞可以穿透层间绝缘层60以延伸到第二源极/漏极SG。
栅极覆盖层75可以设置在每个第二栅极结构GSP上。
图14的“A”部分可以与以上参考图3和4描述的那些相似或相同。
图15至图20是根据本公开示例实施方式的制造半导体器件的方法的剖视图，并且对应于沿图13的线III-III'和IV-IV'截取的剖视图。
参照图15，可以蚀刻基板11的一部分以形成鳍型有源区(即，第二鳍型有源区)AFP和下部有源区(即，第二下部有源区)ARP。鳍型有源区AFP和下部有源区ARP可以在基板11上沿第一方向X延伸。器件隔离层15可以形成在基板11的该部分被蚀刻的区域中。器件隔离层15可以覆盖下部有源区ARP的侧壁和鳍型有源区AFP的侧壁的部分。器件隔离层15的上表面可以低于鳍型有源区AFP的上表面。鳍型有源区AFP的上部可以突出到器件隔离层15之上。器件隔离层15可以包括在鳍型有源区AFP之间的第一隔离层15s和在下部有源区ARP之间的第二隔离层15d。器件隔离层15可以包括例如硅氧化物。
参照图16，虚设栅极结构SGS可以形成为横过鳍型有源区AFP。间隔物85可以形成在虚设栅极结构SGS的侧壁上。虚设栅极结构SGS每个可以包括虚设栅电极PG和在虚设栅电极PG与每个鳍型有源区AFP之间的虚设栅极绝缘层IN。覆盖层25可以形成在虚设栅电极PG上。
虚设栅极结构SGS可以以预定间隔在第一方向X上间隔开布置。虚设栅极结构SGS可以覆盖器件隔离层15和鳍型有源区AFP的上部并且可以沿第二方向Y延伸。间隔物85可以沿着虚设栅极结构SGS的延伸方向延伸。
参照图17，通过使用覆盖层25、每个虚设栅极结构SGS、以及间隔物85作为蚀刻掩模的各向异性干蚀刻工艺，可以蚀刻鳍型有源区AFP的部分，以在虚设栅极结构SGS中相应的虚设栅极结构的相对侧之间形成凹陷。
通过使用鳍型有源区AFP作为籽晶的选择性外延生长工艺可以形成源极/漏极(即，第二源极/漏极)SG，例如p型源极/漏极。
参照图18，层间绝缘层60可以形成为覆盖源极/漏极SG。层间绝缘层60可以填充间隔物85之间的空间。覆盖层25和虚设栅电极PG可以被蚀刻以形成第一开口OP1。
通过在覆盖层25和层间绝缘层60上形成掩模图案并通过使用该掩模图案作为蚀刻掩模的各向异性蚀刻工艺蚀刻覆盖层25和第二虚设栅电极PG，可以形成第一开口OP1。第一开口OP1可以暴露器件隔离层15。
杂质可以通过离子注入工艺被注入到器件隔离层15的上部以形成杂质区17。例如，器件隔离层15可以包括硅氧化物，并且与器件隔离层15相比杂质区17可以进一步包括Si、B、He、P和/或C。杂质区17可以具有1×1019原子/cm3或更高的杂质浓度。例如，杂质区17可以具有1×1020原子/cm3至1×1022原子/cm3的杂质浓度。根据本公开的示例性实施方式，可以在凹陷形成在相应的虚设栅极结构SGS的相对侧之间之前形成第一开口OP1和杂质区17。
参照图19，栅极分离图案80可以形成在第一开口OP1中。
通过沉积绝缘材料并对绝缘材料执行平坦化工艺可以形成栅极分离图案80。通过平坦化，覆盖层25可以被去除以暴露虚设栅电极PG。栅极分离图案80的下表面可以接触杂质区17。
参照图20，第二开口OP2'可以被形成以暴露多个鳍型有源区AFP的上部。
首先，可以顺序地去除虚设栅电极PG和虚设绝缘层IN。此时，由于存在相对于器件隔离层15具有低蚀刻速率的杂质区17，所以可以防止栅极分离图案80下方的器件隔离层15被过蚀刻。
返回参考图14，栅极绝缘层GI和栅电极(即，第二栅电极)GP可以顺序地形成在第二开口OP2'中。
栅极绝缘层GI可以形成在由第二开口OP2'暴露的间隔物85的内表面、鳍型有源区AFP的上部的表面、栅极分离图案80的侧壁以及器件隔离层15的上表面上。栅极绝缘层GI可以包括顺序堆叠并具有不同介电常数的第一绝缘层和第二绝缘层。第二绝缘层的介电常数可以大于第一绝缘层的介电常数。
栅电极GP可以形成在栅极绝缘层GI上。栅极覆盖层75可以形成在栅电极GP上。
在半导体器件中，根据本公开的示例实施方式，杂质区17可以形成在栅极分离图案80下方的器件隔离层15中，使得器件隔离层15的蚀刻速率可以降低。因此，可以防止相邻栅电极GP之间的桥接缺陷(短路)，从而提高半导体器件的产量或可靠性。
尽管已经参考本发明的示例实施方式具体示出和描述了本发明构思，但是本领域普通技术人员将理解，在不脱离本公开的精神和范围的情况下，可以在形式和细节上进行各种改变。
本申请要求于2018年10月29日向韩国专利局提交的韩国专利申请第10-2018-0130032号的优先权，其全部内容通过引用结合在此。

Claims (17)

1.一种半导体器件，包括：
基板；
有源区，设置在所述基板上并沿第一方向延伸；
器件隔离层，与所述有源区相邻；
栅极结构，设置在所述有源区上，所述栅极结构沿与所述第一方向交叉的第二方向延伸并覆盖所述器件隔离层的一部分；
栅极分离图案，接触所述栅极结构的端部；和
杂质区，设置在所述栅极分离图案下方并在所述器件隔离层上。
2.如权利要求1所述的半导体器件，其中所述杂质区的宽度大于所述栅极分离图案的宽度。
3.如权利要求1所述的半导体器件，其中所述杂质区的侧壁具有台阶部分。
4.如权利要求1所述的半导体器件，其中所述杂质区的上表面高于所述器件隔离层的由所述栅极结构覆盖的部分的上表面。
5.如权利要求1所述的半导体器件，其中所述栅极结构的一部分在所述栅极分离图案下方延伸。
6.如权利要求1所述的半导体器件，其中所述栅极结构的下表面低于所述栅极分离图案的下表面。
7.如权利要求1所述的半导体器件，其中所述器件隔离层包括硅氧化物，并且
其中所述杂质区包括Si、B、He、P和/或C。
8.如权利要求1所述的半导体器件，其中所述杂质区的杂质浓度在从1×1020原子/cm3至1×1022原子/cm3的范围。
9.如权利要求1所述的半导体器件，还包括设置在所述有源区上的至少一个沟道层，
其中所述栅极结构至少部分地围绕所述至少一个沟道层。
10.一种半导体器件，包括：
基板；
多个有源区，设置在所述基板上；
器件隔离层，与所述多个有源区相邻；
多个栅极结构，至少部分地交叠所述多个有源区并与所述器件隔离层接触；
栅极分离图案，设置在所述多个栅极结构中相邻的栅极结构之间并在所述器件隔离层上；和
低蚀刻速率区，设置在所述栅极分离图案和所述器件隔离层之间，其中所述低蚀刻速率区具有比所述器件隔离层低的蚀刻速率。
11.如权利要求10所述的半导体器件，其中所述低蚀刻速率区的宽度大于所述栅极分离图案的宽度。
12.如权利要求10所述的半导体器件，其中所述低蚀刻速率区的侧壁包括台阶部分。
13.如权利要求10所述的半导体器件，其中所述低蚀刻速率区的上表面沿第三方向高于所述器件隔离层的在所述多个栅极结构下方的一部分的上表面，所述第三方向远离所述基板延伸。
14.如权利要求10所述的半导体器件，其中所述多个栅极结构中的每个栅极结构的一部分在所述栅极分离图案下方延伸。
15.如权利要求10所述的半导体器件，其中所述器件隔离层包括硅氧化物，
其中所述低蚀刻速率区包括杂质，并且
其中所述杂质包括Si、B、He、P和/或C。
16.如权利要求15所述的半导体器件，其中所述低蚀刻速率区中的所述杂质的浓度在从1×1020原子/cm3至1×1022原子/cm3的范围。
17.如权利要求10所述的半导体器件，还包括在每个所述有源区上的至少一个沟道层，
其中所述多个栅极结构中的每个至少部分地围绕所述至少一个沟道层。
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