CN111106058A - 高压led芯片及其制备方法 - Google Patents
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Abstract
本发明提供了一种高压LED芯片制备方法,包括:S1在生长衬底上形成外延结构和p型欧姆接触层,外延结构中包括n型GaN层、量子阱层及p型GaN层;S2蚀刻外延结构直至生长衬底形成隔离槽,将外延结构分割成多个相互隔离的子外延结构,隔离槽的侧壁倾斜角度为80°~90°,且隔离槽的宽度为2~4μm;S3于N电极处对各子外延结构表面的p型欧姆接触层和外延结构进行蚀刻直至n型GaN层;S4于步骤S3得到的结构表面生长绝缘层,将子外延结构之间的隔离槽填满;S5分别对各子外延结构n型GaN层和p型欧姆接触层表面的绝缘层进行蚀刻形成N极孔和P极孔;S6于步骤S5得到的结构表面制作电极互联线,实现相邻子外延结构之间的电连接,完成高压LED芯片的制备。相对于现有高压LED芯片来说,增加了发光面积,提高了器件的亮度。
Description
技术领域
本发明涉及半导体技术领域,尤其是一种高压LED芯片及其制备方法。
背景技术
LED(Light Emitting Diode,发光二极管)光源属于绿色光源,具有节能环保、寿命长、能耗低、安全系数高等优点,被广泛应用于照明和背光等领域。相对于低压芯片,高压芯片具备诸多优势:1)能够在小电流下使用;2)由于单个单元面积小使其电流扩张好;3)能直接用高压驱动而节省应用端成本。
在制备高压芯片中,通常在芯片上刻蚀隔离槽1以将其分割成多颗相互隔离的子芯片,如图1所示。该隔离槽刻蚀至芯片的衬底上,且于隔离槽中设绝缘层2和电极互联线,通过电极互联线3连接各颗子芯片的电极,从而实现各颗子芯片的串联或者并联,如图2和图3所示。
但是,在目前的高压LED芯片工艺中,为了不影响绝缘层对隔离槽边缘的包覆性,隔离槽的角度都设计的比较小(一般来说该角度小于60°,若大于60°,电极互连线3容易断,在器件使用过程中容易产生开路等问题;同时可能出现绝缘层2对隔离槽侧壁保护不够导致漏电等问题),导致整个隔离槽较宽,如图1~图3所示,子芯片之间的间距较大,而从牺牲了芯片的发光面积,影响整个器件的亮度。
发明内容
为了克服以上不足,本发明提供了一种高压LED芯片制备方法,有效解决现有高压LED芯片中的隔离槽影响发光亮度的技术问题。
本发明提供的技术方案为:
一种高压LED芯片制备方法,包括:
S1在生长衬底上形成外延结构和p型欧姆接触层,所述外延结构中包括n型GaN层、量子阱层及p型GaN层;
S2蚀刻所述外延结构直至生长衬底形成隔离槽,将所述外延结构分割成多个相互隔离的子外延结构,所述隔离槽的侧壁倾斜角度为80°~90°,且所述隔离槽的宽度为2~4μm;
S3于N电极处对各子外延结构表面的p型欧姆接触层和外延结构进行蚀刻直至n型GaN层;
S4于步骤S3得到的结构表面生长绝缘层,将子外延结构之间的隔离槽填满;
S5分别对各子外延结构n型GaN层和p型欧姆接触层表面的绝缘层进行蚀刻形成N极孔和P极孔;
S6于步骤S5得到的结构表面制作电极互联线,实现相邻子外延结构之间的电连接,完成高压LED芯片的制备。
在本发明提供的高压LED芯片制备方法中,在子外延结构之间开设角度为80°~90°、宽度为2~4μm的隔离槽,并将绝缘层填满该隔离槽,使得电极互联线能够很好的把相邻子芯片连接在一起,降低出现漏电、开路等风险。此外,由于隔离槽比较窄,相对于现有高压LED芯片来说,很大程度上减小了芯片上的牺牲面积,增加了发光面积,进而提高器件的亮度。
附图说明
图1~图3为现有技术中高压LED芯片制备方法流程示意图;
图4~图6为本发明中高压LED芯片制备方法流程示意图;
附图标记:
1/4-隔离槽,2/5-绝缘层,3/6-电极互联线。
具体实施方式
为了更清楚地说明本发明实施案例或现有技术中的技术方案,下面将对照附图说明本发明的具体实施方式。显而易见地,下面描述中的附图仅仅是本发明的一些实施例,对于本领域普通技术人员来讲,在不付出创造性劳动的前提下,还可以根据这些附图获得其他的附图,并获得其他的实施方式。
在本发明提供的高压LED芯片制备方法中,包括:
S1在生长衬底上形成外延结构和p型欧姆接触层,外延结构中包括n型GaN层、量子阱层及p型GaN层;p型欧姆接触层3可以为ITO(氧化铟锡)、NiAu、Ag、NiAg等。这里对生长衬底表面形成的外延结构不做具体限定,现有适于制作高压LED芯片的外延结构均包括在本发明的内容中。
S2蚀刻外延结构直至生长衬底形成隔离槽4,将外延结构分割成多个相互隔离的子外延结构,如图4所示。具体,隔离槽的宽度为2~4μm,且侧壁倾斜角度(隔离槽侧壁与生长衬底所在平面之间的夹角)为80°~90°,且在实际应用中,隔离槽的侧壁倾斜越大越接近90°越好。
S3于N电极处对各子外延结构表面的p型欧姆接触层和外延结构进行蚀刻直至n型GaN层。蚀刻的方法可以为光刻等。
S4于步骤S3得到的结构表面生长绝缘层5,将子外延结构之间的隔离槽填满。在该过程中,通过等离子沉积或原子沉积技术在步骤S3得到的结构表面沉积绝缘层,绝缘层的厚度根据实际情况进行调整,确保将隔离槽填满,如隔离槽的厚度为1~2μm。且该绝缘层6可为SiO2、SiN或SiON,或者为SiO2、SiN及SiON中任意两者或者三者的夹层。
S5分别对各子外延结构n型GaN层和p型欧姆接触层表面的绝缘层进行蚀刻形成N极孔和P极孔,如图5所示。蚀刻的方法可以为光刻等。
S6于步骤S5得到的结构表面制作电极互联线6,实现相邻子外延结构之间的电连接,如图6所示,完成高压LED芯片的制备。在该过程中,通过光刻、蒸镀、合金等技术制作电极互联线6。
应当说明的是,上述实施例均可根据需要自由组合。以上所述仅是本发明的优选实施方式,应当指出,对于本技术领域的普通技术人员来说,在不脱离本发明原理的前提下,还可以做出若干改进和润饰,这些改进和润饰也应视为本发明的保护范围。
Claims (2)
1.一种高压LED芯片制备方法,其特征在于,包括:
S1在生长衬底上形成外延结构和p型欧姆接触层,所述外延结构中包括n型GaN层、量子阱层及p型GaN层;
S2蚀刻所述外延结构直至生长衬底形成隔离槽,将所述外延结构分割成多个相互隔离的子外延结构,所述隔离槽的侧壁倾斜角度为80°~90°,且所述隔离槽的宽度为2~4μm;
S3于N电极处对各子外延结构表面的p型欧姆接触层和外延结构进行蚀刻直至n型GaN层;
S4于步骤S3得到的结构表面生长绝缘层,将子外延结构之间的隔离槽填满;
S5分别对各子外延结构n型GaN层和p型欧姆接触层表面的绝缘层进行蚀刻形成N极孔和P极孔;
S6于步骤S5得到的结构表面制作电极互联线,实现相邻子外延结构之间的电连接,完成高压LED芯片的制备。
2.如权利要求1所示的高压LED芯片制备方法,其特征在于,在步骤S4中,所述绝缘层的厚度为1~2μm。
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Citations (4)
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US20100219431A1 (en) * | 2010-03-16 | 2010-09-02 | Ghulam Hasnain | Multi-Junction LED |
US20130214297A1 (en) * | 2012-02-17 | 2013-08-22 | Walsin Lihwa Corporation | High voltage light emitting diode chip and its manufacturing method |
US20150325621A1 (en) * | 2013-02-25 | 2015-11-12 | Seoul Viosys Co., Ltd. | Light-emitting diode with a plurality of light-emitting elements and method for manufacturing same |
CN105449084A (zh) * | 2015-12-22 | 2016-03-30 | 浙江师范大学 | 一种倒装高压led芯片电极及芯片制造方法 |
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Publication number | Priority date | Publication date | Assignee | Title |
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US20100219431A1 (en) * | 2010-03-16 | 2010-09-02 | Ghulam Hasnain | Multi-Junction LED |
US20130214297A1 (en) * | 2012-02-17 | 2013-08-22 | Walsin Lihwa Corporation | High voltage light emitting diode chip and its manufacturing method |
US20150325621A1 (en) * | 2013-02-25 | 2015-11-12 | Seoul Viosys Co., Ltd. | Light-emitting diode with a plurality of light-emitting elements and method for manufacturing same |
CN105449084A (zh) * | 2015-12-22 | 2016-03-30 | 浙江师范大学 | 一种倒装高压led芯片电极及芯片制造方法 |
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