CN111081675A - 具有绝缘电容的集成电路装置及其制造方法 - Google Patents

具有绝缘电容的集成电路装置及其制造方法 Download PDF

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CN111081675A
CN111081675A CN201811215085.XA CN201811215085A CN111081675A CN 111081675 A CN111081675 A CN 111081675A CN 201811215085 A CN201811215085 A CN 201811215085A CN 111081675 A CN111081675 A CN 111081675A
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metal layer
layer
dielectric
integrated circuit
pad
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CN111081675B (zh
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林正基
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Yuanxin Semiconductor Co ltd
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UPI Semiconductor Corp
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Abstract

本发明提供一种集成电路装置包括衬底、绝缘电容以及打线接垫。绝缘电容设置于衬底上且包括下金属层、介电层以及上金属层。介电层位于下金属层与上金属层之间。打线接垫设置于衬底上且包括第一金属层与第二金属层。打线接垫具有开口区与边缘区。第二金属层设置于第一金属层上，且于开口区中与第一金属层接触，介电层延伸至边缘区且堆叠配置于边缘区的第一金属层与第二金属层之间。

Description

具有绝缘电容的集成电路装置及其制造方法
技术领域
本发明涉及一种集成电路装置及其制造方法，尤其涉及一种具有绝缘电容的集成电路装置及其制造方法。
背景技术
金属-绝缘体-金属(metal-insulator-metal，MIM)电容器已经广泛地应用在例如混合信号电路、模拟电路、射频(radio frequency，RF)电路、动态随机存取存储器(dynamicrandom access memory，DRAM)、嵌入式DRAM以及逻辑运算电路的功能电路中。举例来说，在混合信号电路中，电容器可用以当作去耦电容器或高频噪音滤波器。若用在电源电路中，可作为直流隔离元件或能量存储器。然而，在电源电路的直流隔离元件应用中，欲隔离的电压越大，MIM电容器的绝缘体就要越厚，方能提供高击穿电压(breakdown voltage)使电容器维持直流隔离功能。
然而，在高压应用下(例如电容器两端电压差大于2千伏特)，MIM电容器的绝缘体厚度需求随之增加，而厚的绝缘体易使得半导体装置容易在打线工艺中被碰伤，或是导致打线结构与半导体装置的接垫连接不完全。
再者，半导体装置的接垫区通常为布局金属的延伸，厚度较薄，如果在接垫区下方配置电路元件，容易在打线工艺中因打线应力而损及电路元件。因此，现有技术会避免在接垫区下方配置电路，导致半导体装置面积的浪费。
发明内容
为了解决上述问题，本发明提供一种具有绝缘电容的集成电路装置，其可增加打线接垫的厚度以降低阻抗，并提升打线接垫对于打线应力的承受程度。
本发明提供一种具有绝缘电容的集成电路装置的制造方法，其同时形成绝缘电容的上金属层与打线接垫的第二金属层，以节省制造成本。
本发明提供一种集成电路装置包括衬底、绝缘电容以及打线接垫。绝缘电容设置于衬底上且包括下金属层、介电层以及上金属层。介电层位于下金属层与上金属层之间。打线接垫设置于衬底上且包括第一金属层与第二金属层。打线接垫具有开口区与边缘区，第二金属层设置于第一金属层上，且于开口区中与第一金属层接触。介电层延伸至边缘区且堆叠配置于边缘区的第一金属层与第二金属层之间。
在本发明的一实施例中，上述的集成电路装置还包括：第一打线接头、第二打线接头以及至少一有源元件。第一打线接头位于打线接垫上。第二打线接头位于绝缘电容上。至少一有源元件位于衬底与打线接垫之间。
在本发明的一实施例中，第二金属层与上金属层为同一工艺制作。
在本发明的一实施例中，下金属层与第一金属层位于同一水平高度。
在本发明的一实施例中，介电层的厚度大于上金属层的厚度。
在本发明的一实施例中，介电层包括复合层结构。复合层结构包括第一介电材料与第二介电材料。第一介电材料与第二介电材料具有不同的介电常数。
本发明提供另一种集成电路装置包括功能电路、第一接脚以及第二接脚。第一接脚通过绝缘电容耦接至功能电路。第二接脚通过打线接垫与内连线耦接至功能电路。绝缘电容包括下金属层、上金属层以及位于下金属层与上金属层之间的介电层。打线接垫包括第一金属层与第二金属层且具有开口区与边缘区，第二金属层设置于第一金属层上，且于开口区中与第一金属层接触，介电层延伸至边缘区且堆叠配置于边缘区的第一金属层与第二金属层之间。
在本发明的一实施例中，下金属层与第一金属层彼此分离。
本发明提供一种集成电路装置的制造方法，其步骤如下。提供衬底，其定义有打线接垫区与绝缘电容区。于绝缘电容区中的衬底上形成下金属层。于下金属层上共形地形成第一介电层。于打线接垫区中的第一介电层上形成第一金属层。于第一金属层上共形地形成第二介电层。图案化第二介电层，以于打线接垫区中形成暴露出第一金属层的接垫开口。形成第二金属层，其步骤包括：形成第一部分，以接触第一金属层，第一部分沿着接垫开口的侧壁共形地延伸，并覆盖第二介电层的部分顶面；以及形成与第一部分彼此分离的第二部分，其与绝缘电容区的下金属层重叠。
在本发明的一实施例中，于打线接垫区中形成暴露出第一金属层的接垫开口的方法包括：在第二介电层上形成光刻胶图案；形成第一开口；以及形成位于第一开口下方的第二开口，第一开口的最大宽度大于第二开口的最大宽度。
基于上述，本发明提供一种具有绝缘电容的集成电路装置，其具有厚介电层以达到高压绝缘的功效。另外，本发明的集成电路装置增加打线接垫的厚度以降低阻抗，并提升打线接垫对于打线应力的承受程度。此外，本发明还提供一种具有绝缘电容的集成电路装置的制造方法，其同时形成绝缘电容的上金属层与打线接垫的第二金属层，以节省制造成本。
为让本发明的上述特征和优点能更明显易懂，下文特举实施例，并配合附图作详细说明如下。
附图说明
图1是本发明的第一实施例的一种集成电路装置的俯视示意图。
图2是图1的等效电路示意图。
图3A至图3K是沿着图1的线I-I’的制造流程的剖面示意图。
图4是本发明的第二实施例的一种集成电路装置的剖面示意图。
图5是本发明的第三实施例的一种集成电路装置的剖面示意图。
具体实施方式
参照本实施例的附图以更全面地阐述本发明。然而，本发明也可以各种不同的形式体现，而不应限于本文中所述的实施例。附图中的层与区域的厚度会为了清楚起见而放大。相同或相似的标号表示相同或相似的元件，以下段落将不再一一赘述。
图1是本发明的第一实施例的一种集成电路装置的俯视示意图。图2是图1的等效电路示意图。
请参照图1与图2，第一实施例的集成电路装置10包括功能电路200以及多个接脚A、B、C、D、E、F、G、H、I、J(以下简称为接脚A-J)。在一实施例中，功能电路200可以是具有多种功能的电路元件，例如是混合信号电路、模拟电路、RF电路、DRAM、嵌入式DRAM、逻辑运算电路以及电源转换电路等。
如图1所示，接脚A-J分别配置在功能电路200旁。具体来说，接脚A、F、H分别通过绝缘电容CA、CF、CH以及内连线(interconnects)211a、211f、211h耦接至功能电路200。另外，接脚B、C、D、E、G、I、J则是通过打线接垫111与内连线211b、211c、211d、211g、211i、211j耦接至功能电路200。在图1中，两个接脚D、E可共用同一内连线211d，但本发明不以此为限。在其他实施例中，也可三个或更多个接脚共用同一内连线。
在一实施例中，内连线211(其包括211a、211b、211c、211d、211f、211g、211h、211i、211j)的材料包括导体材料(例如金属、阻障(barrier)金属等合适导体材料)，且内连线211通过后段工艺(BEOL)来形成。在一些实施例中，内连线211彼此分隔，而不会直接连接。在替代实施例中，如图1所示，内连线211可通过功能电路200电性连接在一起。在其他实施例中，内连线211可位于不同水平高度或是相同水平高度。
图3A至图3K是沿着图1的线I-I’的制造流程的剖面示意图。
请参照图3A，本实施例提供一种集成电路装置10(如图3K所示)的制造方法，其步骤如下。提供衬底100。衬底100定义有打线接垫区R1与绝缘电容区R2。在一实施例中，衬底100例如是半导体衬底或是半导体化合物衬底。在本实施例中，衬底100为硅衬底。
如图3A所示，衬底100中具有隔离结构101。在一实施例中，隔离结构101可以是场氧化物(field oxide，FOX)或是浅沟渠隔离结构(shallow trench isolation，STI)。虽然图3A仅示出2个隔离结构101，但本发明不以此为限。在其他实施例中，隔离结构101的数量可依需求来调整。
在打线接垫区R1中的衬底100上形成有源元件102。在一实施例中，有源元件102可以是晶体管、二极管、存储器等类似元件。虽然图3A仅示出1个有源元件102，但本发明不以此为限。在其他实施例中，有源元件102的数量可以是1个、2个或多个。
接着，在衬底100上形成介电层104。介电层104自绝缘电容区R2延伸至打线接垫区R1且覆盖有源元件102。在一实施例中，介电层104的材料包括氧化硅、氮化硅、氮氧化硅或其组合。介电层104的形成方法可以是，但不限于化学气相沉积法(chemical vapordeposition，CVD)。
请参照图3B，在介电层104上全面性地形成下金属材料层106。下金属材料层106自绝缘电容区R2延伸至打线接垫区R1。在一实施例中，下金属材料层106的材料包括Cu、Al、AlCu、Ti、TiN、Ta、TaN或其组合。下金属材料层106的形成方法可以是，但不限于物理气相沉积法(physical vapor deposition，PVD)。
请参照图3B与图3C，图案化下金属材料层106，以于绝缘电容区R2中的衬底100(或介电层104)上形成下金属层106a。
请参照图3D，在介电层104上共形地形成介电层108。介电层108(其可视为第一介电层)自打线接垫区R1延伸至绝缘电容区R2，且共形地覆盖下金属层106a。在一实施例中，介电层108的材料包括氧化硅、氮化硅、氮氧化硅或其组合。介电层108的形成方法可以是，但不限于CVD。在替代实施例中，介电层108与介电层104的材料可以相同或是不同。
接着，在介电层108上全面性地形成第一金属材料层110。第一金属材料层110共形地覆盖介电层108。在一实施例中，第一金属材料层110的材料包括Cu、Al、AlCu、Ti、TiN、Ta、TaN或其组合。第一金属材料层110的形成方法可以是，但不限于PVD。
请参照图3D与图3E，图案化第一金属材料层110，以于打线接垫区R1中的介电层108上形成第一金属层110a。如图3E所示，第一金属层110a对应于有源元件102。也就是说，第一金属层110a位于有源元件102的正上方。
请参照图3F，在介电层108上共形地形成介电层112。介电层112(其可视为第二介电层)自绝缘电容区R2延伸至打线接垫区R1，且共形地覆盖第一金属层110a。在一实施例中，介电层112的材料包括氧化硅、氮化硅、氮氧化硅或其组合。介电层112的形成方法可以是，但不限于CVD。在替代实施例中，介电层112与介电层108的材料可以是相同或是不同。
请参照图3F与图3G，图案化介电层112，以于打线接垫区R1中形成接垫开口114。接垫开口114暴露出第一金属层110a的部分顶面。具体来说，接垫开口114包括第一开口114a与位于第一开口114a下方的第二开口114b。在一实施例中，接垫开口114的形成方法包括：在介电层112上形成光刻胶图案(未示出)；以光刻胶图案为罩幕，进行各向同性刻蚀工艺，以形成第一开口114a；接着进行各向异性刻蚀工艺，以形成第二开口114b；以及移除光刻胶图案。在此情况下，如图3G所示，第一开口114a与第二开口114b连通。第一开口114a呈碗状，其具有弧形的侧壁。第二开口114b的剖面轮廓呈矩形，其具有实质上垂直于第一金属层110a的顶面的侧壁。在一实施例中，第一开口114a的最大宽度W1大于第二开口114b的最大宽度W2。
请参照图3H，在介电层112上全面性地形成第二金属材料层116。第二金属材料层116共形地覆盖介电层112的顶面、接垫开口114的侧壁以及第一金属层110a的部分顶面。在一实施例中，第二金属材料层116的材料包括Cu、Al、AlCu、Ti、TiN、Ta、TaN或其组合。第二金属材料层116的形成方法可以是，但不限于是PVD。
请参照图3H与图3I，图案化第二金属材料层116，以形成第二金属层118。具体来说，如图3I所示，第二金属层118包括彼此分离的第一部分118a与第二部分118b。第一部分118a(其可视为第二金属层)位于打线接垫区R1中的衬底100上。第一部分118a接触第一金属层110a的部分顶面，且沿着接垫开口114的侧壁共形地延伸，并覆盖介电层112的部分顶面。另一方面，第二部分118b(其可视为上金属层)位于绝缘电容区R2中的衬底100上，且与下金属层106a重叠。也就是说，第二部分118b位于下金属层106a的正上方。在一实施例中，介电层112的厚度T1约为4至6微米(μm)；第二部分(或上金属层)118b的厚度T2约为3至5μm。在另一实施例中，介电层112的厚度T1大于第二部分(或上金属层)118b的厚度T2，但本发明不以此为限。
请参照图3J，在介电层112上全面性地形成保护材料层120。保护材料层120共形地覆盖介电层112与第二金属层118。具体来说，保护材料层120可以是复合层结构，其包括第一保护材料层120a与位于第一保护材料层120a上的第二保护材料层120b。但本发明不以此为限，在其他实施例中，保护材料层120可以是3层或更多层的复合层结构。在一实施例中，第一保护材料层120a为氧化物层(例如是氧化硅)；而第二保护材料层120b为氮化物层(例如是氮化硅)；上述两者的形成方法可以是，但不限于是CVD。但本发明不以此为限，在其他实施例中，第一保护材料层120a与第二保护材料层120b可以是相同材料或是不同材料。在替代实施例中，第二保护材料层120b的致密度高于第一保护材料层120a的致密度，以更进一步地阻挡外部的水气及氧气。
请参照图3J与图3K，图案化保护材料层120，以形成保护层122。保护层122暴露出第二金属层118的部分顶面。保护层122包括第一保护层122a与位于第一保护层122a上的第二保护层122b。在此情况下，如图3K所示，打线接垫区R1中的第一金属层110a与第一部分118a接触以形成打线接垫111。打线接垫111具有开口区111a与边缘区111b。开口区111a由接垫开口114所定义，而边缘区111b环绕开口区111a的边缘。介电层112延伸至边缘区111b且堆叠配置于边缘区111b的第一金属层110a与第一部分(以下称为第二金属层)118a之间。
另一方面，绝缘电容区R2中的第二部分(以下称为上金属层)118b、下金属层106a以及两者之间的介电层113(其包括部分介电层108、112)可形成绝缘电容CA。在本实施例中，由厚的介电层113所构成的绝缘电容CA可达到超高压绝缘的功效。也就是说，本实施例的绝缘电容CA可应用在超高压半导体元件中。于此，所谓的超高压半导体元件可以是耐受2千伏特(V)以上的半导体元件。在一实施例中，介电层113的厚度约为5至6μm。在替代实施例中，第二金属层118a与上金属层118b是同时形成的，也就是说，第二金属层118a与上金属层118b源自于相同材料与相同工艺。
如图3K所示，形成保护层122之后，在打线接垫111上形成第一打线接头(firstwelding head)130与第一焊线132(其可视为接脚B)，并在绝缘电容CA上第二打线接头140与第二焊线142(其可视为接脚A)。在一实施例中，第一打线接头130、第一焊线132、第二打线接头140以及第二焊线142的材料包括金属，其可例如是Cu、Au、Ni或其组合。举例来说，第一打线接头130、第一焊线132、第二打线接头140以及第二焊线142的材料皆可为金属Cu，相较于金属Au，其可降低工艺成本。第一打线接头130、第一焊线132、第二打线接头140以及第二焊线142的形成方法可以是打线工艺，其为本领域技术人员所熟知，于此便不再详述。
值得注意的是，如图3K所示，本实施例将第二金属层118a形成在第一金属层110a上，可增加打线接垫111的厚度，以降低打线接垫111的阻抗。同时，可防止打线应力(即形成第一焊接头130与第一焊线132时的应力)损伤打线接垫111下方的电路元件(例如有源元件102)，从而适用电路位于接垫下方(circuit under pad)的设计规则。因此，本实施例的集成电路装置10使集成电路的电路配置更有弹性。另一方面，在形成第二金属层118a时也同时形成绝缘电容CA的上金属层118b，可减少工艺步骤并降低工艺成本。另外，第一金属层110a不用再考虑维持厚度以抵抗打线应力，厚度也可进一步降低以达到更小的线宽，进而缩小整体集成电路装置10的面积。此外，本实施例的第二金属层118a沿着接垫开口114的侧壁共形地延伸，以形成包覆接垫开口114的尖角的圆角结构(rounding structure)118c，进而避免后续打线时第一打线接头130与第一焊线132被碰伤所导致的工艺缺陷。如此一来，本实施例便可提升打线稳定度，以增加良率。
图4是本发明的第二实施例的一种集成电路装置的剖面示意图。
请参照图4，第二实施例的集成电路装置20与第一实施例的集成电路装置10相似。上述两者不同之处在于：集成电路装置20的下电极层110a2与第一金属层110a位于同一水平高度(at a same level)处。于此，所谓“同一水平高度”是指下电极层110a2与第一金属层110a是同时形成的，也就是说，下电极层110a2与第一金属层110a源自于相同材料与相同工艺。详细地说，在图案化第一金属材料层110(如图3D所示)之后，第一金属层110a1形成在打线接垫区R1中的介电层108上，而下电极层110a2则是形成在绝缘电容区R2中的介电层108上。在此情况下，如图4所示，绝缘电容区R2中的上金属层118b、下金属层110a2以及两者之间的介电层115(其包括部分介电层112)可形成绝缘电容C2。在本实施例中，同时形成绝缘电容C2的下电极层110a2以及打线接垫111的第一金属层110a可减少工艺步骤，进而节省工艺成本。
图5是本发明的第三实施例的一种集成电路装置的剖面示意图。
请参照图5，第三实施例的集成电路装置30与第一实施例的集成电路装置10相似。上述两者不同之处在于：集成电路装置30的介电层112’是复合层结构，其包括两个第一介电材料112a、112c与两者之间的第二介电材料112b。在一实施例中，第一介电材料112a、112c与第二介电材料112b具有不同的介电常数。举例来说，第一介电材料112a、112c的材料可以氧化物(例如氧化硅)，而第二介电材料112b的材料则可以是氮化物(例如氮化硅)，以形成ONO结构，藉此提升介电层112’的电性隔离效果。但本发明不以此为限，在其他实施例中，介电层112’也可以ON、ONNO、ONONO等各种复合层结构。
如图5所示，绝缘电容区R2中的上金属层118b、下金属层106a以及两者之间的介电层117(其包括部分介电层108、112’)可形成绝缘电容C3。相较于图3K的集成电路装置10，具有高介电常数(k>4)的第二介电材料112b可增加绝缘电容C3的电容值，以提升效能。
综上所述，本发明提供一种具有绝缘电容的集成电路装置，其具有厚介电层以达到超高压绝缘的功效。另外，本发明的集成电路装置增加打线接垫的厚度以降低阻抗，并提升打线接垫对于打线应力的承受程度。此外，本发明还提供一种具有绝缘电容的集成电路装置的制造方法，其同时形成绝缘电容的上金属层与打线接垫的第二金属层，以节省制造成本。
虽然本发明已以实施例揭示如上，然其并非用以限定本发明，任何所属技术领域中技术人员，在不脱离本发明的精神和范围内，当可作些许的更改与润饰，故本发明的保护范围当视所附权利要求所界定者为准。

Claims (10)

1.一种集成电路装置，包括：
衬底；
绝缘电容，设置于所述衬底上且包括下金属层、介电层以及上金属层，其中所述介电层位于所述下金属层与所述上金属层之间；以及
打线接垫，设置于所述衬底上且包括第一金属层与第二金属层，所述打线接垫具有开口区与边缘区，其中所述第二金属层设置于所述第一金属层上，且于所述开口区中与所述第一金属层接触，所述介电层延伸至所述边缘区且堆叠配置于所述边缘区的所述第一金属层与所述第二金属层之间。
2.根据权利要求1所述的集成电路装置，还包括：
第一打线接头，位于所述打线接垫上；
第二打线接头，位于所述绝缘电容上；以及
至少一有源元件位于所述衬底与所述打线接垫之间。
3.根据权利要求1所述的集成电路装置，其中所述第二金属层与所述上金属层为同一工艺制作。
4.根据权利要求1所述的集成电路装置，其中所述下金属层与所述第一金属层位于同一水平高度。
5.根据权利要求1所述的集成电路装置，其中所述介电层的厚度大于所述上金属层的厚度。
6.根据权利要求1所述的集成电路装置，其中所述介电层包括复合层结构，所述复合层结构包括第一介电材料与第二介电材料，所述第一介电材料与所述第二介电材料具有不同的介电常数。
7.一种集成电路装置，包括：
功能电路；
第一接脚，通过绝缘电容耦接至所述功能电路；以及
第二接脚，通过打线接垫与内连线耦接至所述功能电路，
其中所述绝缘电容包括下金属层、上金属层以及位于所述下金属层与所述上金属层之间的介电层，
其中所述打线接垫包括第一金属层与第二金属层且具有开口区与边缘区，其中所述第二金属层设置于所述第一金属层上，且于所述开口区中与所述第一金属层接触，所述介电层延伸至所述边缘区且堆叠配置于所述边缘区的所述第一金属层与所述第二金属层之间。
8.根据权利要求7所述的集成电路装置，其中所述下金属层与所述第一金属层彼此分离。
9.一种集成电路装置的制造方法，包括：
提供衬底，其定义有打线接垫区与绝缘电容区；
于所述绝缘电容区中的所述衬底上形成下金属层；
于所述下金属层上共形地形成第一介电层；
于所述打线接垫区中的所述第一介电层上形成第一金属层；
于所述第一金属层上共形地形成第二介电层；
图案化所述第二介电层，以于所述打线接垫区中形成暴露出所述第一金属层的接垫开口；以及
形成第二金属层，包括：
形成第一部分，以接触所述第一金属层，所述第一部分沿着所述接垫开口的侧壁共形地延伸，并覆盖所述第二介电层的部分顶面；以及
形成与所述第一部分彼此分离的第二部分，其与所述绝缘电容区的所述下金属层重叠。
10.根据权利要求9所述的集成电路装置的制造方法，其中于所述打线接垫区中形成暴露出所述第一金属层的所述接垫开口的方法包括：
在所述第二介电层上形成光刻胶图案；
形成第一开口；以及
形成位于所述第一开口下方的第二开口，其中所述第一开口的最大宽度大于所述第二开口的最大宽度。
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