CN111077822A

CN111077822A - Multi-channel programmable acquisition system based on software channel configuration item reconstruction

Info

Publication number: CN111077822A
Application number: CN201911351112.0A
Authority: CN
Inventors: 王森; 杨帆; 云建军; 唐侃; 南非
Original assignee: CHINA AEROSPACE TIMES ELECTRONICS CO LTD
Current assignee: CHINA AEROSPACE TIMES ELECTRONICS CO LTD
Priority date: 2019-12-24
Filing date: 2019-12-24
Publication date: 2020-04-28

Abstract

The invention discloses a multichannel programmable acquisition system based on software channel configuration item reconstruction, which comprises: the device comprises a first input channel module, a second input channel module, an AD acquisition module, a power supply module and a control core module; after a control signal sent by the upper computer is input into the control core module, the control core module controls a specified channel in the first input channel module or the second input channel module to be opened according to a control signal sending address signal, an analog quantity signal needing to be collected from the outside enters the AD acquisition module through the specified channel, the AD acquisition module converts the analog quantity signal into a 16-bit digital quantity signal to be input into the control core module, the control core module takes the first 8 bits of the 16-bit digital quantity signal to be written into a storage area, and after the upper computer sends a reading signal, the collected first 8-bit digital quantity signals are sequentially reported to finish the collection of the analog quantity signal. The invention is well suitable for complex application scenes with more acquisition paths, changed acquisition path sequences and changed acquisition intervals.

Description

Multi-channel programmable acquisition system based on software channel configuration item reconstruction

Technical Field

The invention belongs to the technical field of signal acquisition, and particularly relates to a multi-channel programmable acquisition system based on software channel configuration item reconstruction.

Background

The existing analog quantity acquisition method is mostly a single-path analog signal acquisition method or a multi-path fixed sequence analog quantity acquisition method. When the complex application scene with more acquisition paths, changed acquisition path sequence and changed acquisition intervals is required, the existing acquisition method cannot meet the application requirements of the scene.

Disclosure of Invention

The technical problem solved by the invention is as follows: the multichannel programmable acquisition system based on software channel configuration item reconstruction is provided, and is well suitable for complex application scenes with more acquisition paths, acquisition path sequence change and acquisition interval change.

The purpose of the invention is realized by the following technical scheme: a multi-channel programmable acquisition system based on software channel configuration item reconstruction comprises: the device comprises a first input channel module, a second input channel module, an AD acquisition module, a power supply module and a control core module; after a control signal sent by the upper computer is input into the control core module, the control core module controls a specified channel in the first input channel module or the second input channel module to be opened according to a control signal sending address signal, an analog quantity signal needing to be collected from the outside enters the AD acquisition module through the specified channel, the AD acquisition module converts the analog quantity signal into a 16-bit digital quantity signal to be input into the control core module, the control core module writes the first 8 bits of the 16-bit digital quantity signal into a storage area, and after the upper computer sends a reading signal, the collected first 8-bit digital quantity signals are sequentially reported to finish the collection of the analog quantity signal; the power supply module supplies power to the first input channel module, the second input channel module, the AD acquisition module and the control core module respectively.

In the above multi-channel programmable acquisition system based on software channel configuration item reconstruction, the first input channel module and the second input channel module have the same structure, and include: the circuit comprises a U9 digital selection switch, a U10 level conversion chip, a capacitor C119, a capacitor C38, a capacitor C40, a resistor R80, a resistor R83 and a resistor R85; the VDD13 end and the VDD14 end of the U9 digital selection switch are both connected with one end of the capacitor C119, and the Vss124 end and the GND23 end of the U9 digital selection switch are both connected with the other end of the capacitor C119; the GND11 end and the GND12 end of the U10 level conversion chip are both connected with the other end of the capacitor C119; the A0 end of the U9 number selection switch is connected with the A8 end of the U10 level conversion chip; the A1 end of the U9 number selection switch is connected with the A7 end of the U10 level conversion chip; the A2 end of the U9 number selection switch is connected with the A6 end of the U10 level conversion chip; the A3 end of the U9 number selection switch is connected with the A5 end of the U10 level conversion chip; the A4 end of the U9 number selection switch is connected with the A4 end of the U10 level conversion chip; 20 pins of the U9 digital selection switch are connected with the A3 end of the U10 level conversion chip; the 21 feet of the U9 number selection switch is connected with the A2 end of the U10 level conversion chip; the 22 feet of the U9 number selection switch is connected with the A1 end of the U10 level conversion chip; the DIR end of the U10 level conversion chip is connected with one end of a capacitor C38, and the DIR end of the U10 level conversion chip is grounded; the VCCA end of the U10 level conversion chip is connected with the other end of the capacitor C38, and the VCCA end of the U10 level conversion chip is connected with + 5V; the B3 end of the U10 level conversion chip is connected with one end of a resistor R80, the B2 end of the U10 level conversion chip is connected with one end of a resistor R83, and the B1 end of the U10 level conversion chip is connected with one end of a resistor R85; the other end of the resistor R80 and the other end of the resistor R83 are connected with the other end of the resistor R85; the OE end of the U10 level conversion chip is connected with one end of the capacitor C40; the OE end of the U10 level conversion chip is grounded; the VCCB23 end and the VCCB24 end of the U10 level conversion chip are both connected with the other end of the capacitor C40; the other end of the capacitor C40 is 3.3 v.

In the multi-channel programmable acquisition system reconstructed based on the software channel configuration item, the AD acquisition module includes a U7 follower amplifier, a U8AD acquisition chip, a capacitor C83, a capacitor C13, a capacitor C27, a capacitor C30, a resistor R26, a capacitor C96, a capacitor C97, a resistor R60, a resistor R61, a resistor R72, a resistor R58, a resistor R65, a resistor R67, a resistor R69, a resistor R71, a capacitor C93, a capacitor C90, a capacitor C91, a capacitor C84, a capacitor C102, a capacitor C94, a capacitor C95, a capacitor C99, a capacitor C72, and a capacitor C85; the OUT1 end and the IN1 end of the U7 follower amplifier are both connected with one end of a resistor R24, and the other end of the resistor R24 is respectively connected with the V1 end of the U8AD acquisition chip and one end of a capacitor C27; the other end of the capacitor C27 is connected with one end of the capacitor C30 and is grounded; the OUT2 end and the IN2 end of the U7 follower amplifier are both connected with one end of a resistor R22, and the other end of the resistor R22 is respectively connected with the V3 end of the U8AD acquisition chip and the other end of a capacitor C30; the VCC + end of the U7 following amplifier is connected with one end of a capacitor C83, and the VCC + end of the U7 following amplifier is connected with + 15V; the VCC-terminal of the U7 follower amplifier is connected with one end of a capacitor C13, the other end of the capacitor C13 is connected with the other end of the capacitor C83 and is grounded, and the VCC-terminal of the U7 follower amplifier is-15V; one end of the resistor R26 is respectively connected with the V2 end, the V4 end, the V5 end and the V6 end of the U8AD acquisition chip, and the other end of the resistor R26 is grounded; one end of the capacitor C72 and one end of the capacitor C85 are both connected with the other end of the MB2, and one end of the capacitor C72 and one end of the capacitor C85 are both connected with the DVCC end of the U8AD acquisition chip; the other end of the capacitor C72 and the other end of the capacitor C85 are both connected with the ground; the DVCC end of the U8AD acquisition chip is connected with the other end of the MB2, one end of the MB2 is connected with one end of the capacitor C102 and one end of the capacitor C94, and the other end of the capacitor C102 and the other end of the capacitor C94 are grounded; an AVCC34 end, an AVCC35 end, an AVCC40 end, an AVCC41 end, an AVCC46 end, an AVCC47 end, an AVCC50 end and an AVCC60 end of the U8AD acquisition chip are all connected with one end of a capacitor C102; one end of the capacitor C93 is connected with the pin 51 of the U8AD acquisition chip, and the other end of the capacitor C93 is grounded; one end of the capacitor C90 is connected with the pin 54 of the U8AD acquisition chip, and the other end of the capacitor C90 is grounded; one end of the capacitor C91 is connected with the pin 56 of the U8AD acquisition chip, and the other end of the capacitor C91 is grounded; one end of the resistor R71 is connected with the pin 28 of the U8AD acquisition chip, and the other end of the resistor R71 is grounded; one end of the capacitor C73 is connected with the pin 9 of the U8AD acquisition chip, and the pin 9 of the U8AD acquisition chip is connected with 3.3V voltage; the other end of the capacitor C73 is grounded; one end of the resistor R69 is connected with the pin 23 of the U8AD acquisition chip, and the other end of the resistor R69 is grounded; one end of the resistor R67 is connected with the pin 22 of the U8AD acquisition chip, and the other end of the resistor R67 is grounded; one end of the resistor R65 is connected with the pin 21 of the U8AD acquisition chip, and the other end of the resistor R65 is grounded; one end of the resistor R72 is connected with the pin 24 of the U8AD acquisition chip, and the other end of the resistor R72 is connected with 3.3V; one end of the resistor R58 is connected with the pin 63 of the U8AD acquisition chip, and the other end of the resistor R72 is connected with 3.3V; one end of the resistor R61 is connected with the pin 20 of the U8AD acquisition chip, and the other end of the resistor R61 is connected with 3.3V; one end of the resistor R60 is connected with the pin 19 of the U8AD acquisition chip, and the other end of the resistor R60 is connected with 3.3V; one end of the capacitor C96 is connected with an AGND32 end, an AGND37 end, an AGND38 end, an AGND43 end, an AGND44 end, an AGND49 end, an AGND52 end, an AGND53 end, an AGND55 end, an AGND57 end and an AGND59 end of the U10 level conversion chip; one end of the capacitor C97 is connected with an AGND32 end, an AGND37 end, an AGND38 end, an AGND43 end, an AGND44 end, an AGND49 end, an AGND52 end, an AGND53 end, an AGND55 end, an AGND57 end and an AGND59 end of the U10 level conversion chip; the other end of the capacitor C96 is connected with the VSS end of the U10 level conversion chip, the other end of the capacitor C97 is connected with the VSS end of the U10 level conversion chip, and the VSS end of the U10 level conversion chip is connected with-15V.

In the multi-channel programmable acquisition system reconstructed based on the software channel configuration items, the power supply module comprises a U1 follower amplifier, a capacitor C8, a capacitor C9, a tantalum capacitor C45, a tantalum capacitor C55, a tantalum capacitor C3, a tantalum capacitor C60, a resistor R48 and a resistor R49; the positive electrode of the tantalum capacitor C3 is connected with the VIN 210 end and the VIN 211 end of the U1 following amplifier, and the VIN 210 end and the VIN 211 end of the U1 following amplifier are connected with + 5V; the negative electrode of the tantalum capacitor C3 is grounded; the anode of the tantalum capacitor C45, the anode of the tantalum capacitor C55, one end of the capacitor C8 and one end of the capacitor C9 are all connected with the VIN1 end of the U1 follower amplifier, and the cathode of the tantalum capacitor C45, the cathode of the tantalum capacitor C55, the other end of the capacitor C8 and the other end of the capacitor C9 are all grounded; the anode of the tantalum capacitor C55 is respectively connected with the VIN 23 end of the U1 follower amplifier, the pin 5 of the U1 follower amplifier and the pin 6 of the U1 follower amplifier; u1 follows pin 7 of the amplifier to ground; u1 follows the 8 pins of the amplifier at + 5V; u1 follows the 9 th pin of the amplifier to ground; the anode of the tantalum capacitor C49, one end of the resistor R48 and one end of the resistor R49 are connected with the 23 feet of the U1 follower amplifier; the anode of the tantalum capacitor C49, one end of the resistor R48 and one end of the resistor R49 are connected with the pin 22 of the U1 follower amplifier; the anode of the tantalum capacitor C49, one end of the resistor R48 and one end of the resistor R49 are connected with the 21 pin of the U1 follower amplifier; the negative electrode of the tantalum capacitor C49 is grounded, the other end of the resistor R48 is connected with the 19 pin of the U1 follower amplifier, and the other end of the resistor R49 is connected with the 18 pin of the U1 follower amplifier; the positive electrode of the tantalum capacitor C60 is connected with the 16 pin, the 15 pin and the 14 pin of the U1 follower amplifier, and the negative electrode of the tantalum capacitor C60 is grounded; u1 follows the

amplifier pins

13, 24 to ground.

In the multi-channel programmable acquisition system based on software channel configuration item reconstruction, the U9 number selection switch is an ADG732 multi-channel number selection switch, the acquisition input end is 32 channels, a designated single-channel switch in the 32 channels can be selected to be turned on according to address codes input from the control end to A0 to A4, and the turn-on sequence and time of the number selection switch can be selected by controlling the address codes input from the control end. The U10 is a level conversion chip, the front end of the chip is connected with a control chip FPGA, and the FPGA sends an A0-A4 address signal, a chip selection signal, a programming signal and an enabling signal which are required by the control of a digital selection switch. The control signal is converted from 3.3V level to 5V level signal after passing through U10, and then is input into the digital selection switch to be controlled. When no signal is input, the chip selection signal, the programming signal and the enabling signal are pulled up to 3.3V through R80, R83 and R85 resistors, and at the moment, the digital selection switch is closed by default; analog signals needing to be collected from the outside enter the digital selection switch U9 after passing through an RC filter network, the U9 is controlled by control signals converted by the U10, a designated single path is selectively opened, the analog signals input by opening a path enter the rear end of the digital selection switch, and the analog signals are input into a rear end circuit through a pin 43 of a chip.

In the multi-channel programmable acquisition system based on software channel configuration item reconstruction, the U7 follower amplifier is a TLE2142 dual-path follower amplifier and is used as an active filter chip in a circuit, and single-path analog signals acquired by the first input channel and the second input channel enter the U7, are subjected to active filtering by the U7 and passive filtering by the RC at the rear end and enter the U8AD acquisition chip; the U8AD acquisition chip can support 6 paths of AD signal acquisition at most, the acquisition range is +/-10V, the acquisition precision is 16 bits, the acquisition conversion time is 3.1us, and the throughput rate is 250 KSPS. Analog quantity signals after active filtering and passive filtering enter an AD chip, then are converted into 16-bit digital quantity to be output, and output signals enter a rear-end FPGA.

In the multi-channel programmable acquisition system based on software channel configuration item reconstruction, the control core module comprises an FPGA, a 32M crystal oscillator U3, an 8-path level conversion chip U11, an 8-path level conversion chip U13 and a single-path level conversion chip U12; the 8-channel level conversion chip U13 and the one-channel level conversion chip U12 convert 5V control signals output by an upper computer into 3.3V control signals to be input into the FPGA, and the 8-channel level conversion chip U11 converts 8-bit 3.3V level acquisition data output by the single chip microcomputer into 5V acquisition data to be reported to the upper computer; the 32M crystal oscillator U3 provides a 32M crystal oscillator clock for the FPGA for internal frequency division calculation of the FPGA.

Compared with the prior art, the invention has the following beneficial effects:

(1) the multi-channel programmable acquisition system based on software channel configuration item reconstruction is well suitable for complex application scenes with more acquisition paths, acquisition path sequence change and acquisition interval change.

(2) Because the invention adopts the multi-channel digital selection switch to control the input of the acquisition signals, the increase of the number of the acquisition signal channels can be realized under the condition that the output pins of the control chip are enough, so that the product has good expansibility;

(3) according to the invention, the on-off of the multi-path number selection switch is controlled by the control chip, the control on the acquisition channels can be completed by changing the configuration items of the acquisition channels built in the control chip, the acquisition of each channel in any sequence is realized, and the acquisition is carried out on a certain channel for multiple times or the acquisition is not carried out by skipping over the certain channel;

(4) the invention adopts the FPGA chip as the control chip, can carry out online editing on the configuration items of the acquisition channel table, carries out online editing on the opening path sequence and the acquisition interval of the input switch, and realizes the acquisition and real-time update of any path sequence of the multichannel acquisition signals.

Drawings

Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The drawings are only for purposes of illustrating the preferred embodiments and are not to be construed as limiting the invention. Also, like reference numerals are used to refer to like parts throughout the drawings. In the drawings:

fig. 1 is a block diagram of a multi-channel programmable acquisition system based on software channel configuration item reconstruction according to an embodiment of the present invention;

FIG. 2 is a schematic diagram of a first input channel module or a second input channel module provided by an embodiment of the invention;

fig. 3 is a schematic diagram of an AD acquisition module provided in an embodiment of the present invention;

FIG. 4 is a schematic diagram of a control core module provided by an embodiment of the present invention;

FIG. 5 is a schematic diagram of a power supply module provided by an embodiment of the invention;

fig. 6 is a timing diagram of an AD acquisition provided by an embodiment of the present invention;

FIG. 7 is a software timing diagram of a memory module according to an embodiment of the present invention;

fig. 8 is a timing diagram of data reception and transmission according to an embodiment of the present invention.

Detailed Description

Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be embodied in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art. It should be noted that the embodiments and features of the embodiments may be combined with each other without conflict. The present invention will be described in detail below with reference to the embodiments with reference to the attached drawings.

Fig. 1 is a block diagram of a multi-channel programmable acquisition system based on software channel configuration item reconstruction according to an embodiment of the present invention. As shown in fig. 1, the multi-channel programmable acquisition system based on software channel configuration item reconstruction includes: the device comprises a first input channel module, a second input channel module, an AD acquisition module, a power supply module and a control core module; after a control signal sent by the upper computer is input into the control core module, the control core module controls a specified channel in the first input channel module or the second input channel module to be opened according to a control signal sending address signal, an analog quantity signal needing to be collected from the outside enters the AD acquisition module through the specified channel, the AD acquisition module converts the analog quantity signal into a 16-bit digital quantity signal to be input into the control core module, the control core module writes the first 8 bits of the 16-bit digital quantity signal into a storage area, and after the upper computer sends a reading signal, the collected first 8-bit digital quantity signals are sequentially reported to finish the collection of the analog quantity signal; the power supply module supplies power to the first input channel module, the second input channel module, the AD acquisition module and the control core module respectively.

Fig. 2 is a schematic diagram of a first input channel module or a second input channel module according to an embodiment of the present invention. As shown in fig. 2, the first input channel module and the second input channel module have the same structure, and include: the circuit comprises a U9 digital selection switch, a U10 level conversion chip, a capacitor C119, a capacitor C38, a capacitor C40, a resistor R80, a resistor R83 and a resistor R85; wherein the content of the first and second substances,

a VDD13 terminal and a VDD14 terminal of the U9 digital selection switch are both connected with one end of the capacitor C119, and a Vss124 terminal and a GND23 terminal of the U9 digital selection switch are both connected with the other end of the capacitor C119; the GND11 end and the GND12 end of the U10 level conversion chip are both connected with the other end of the capacitor C119; the A0 end of the U9 number selection switch is connected with the A8 end of the U10 level conversion chip; the A1 end of the U9 number selection switch is connected with the A7 end of the U10 level conversion chip; the A2 end of the U9 number selection switch is connected with the A6 end of the U10 level conversion chip; the A3 end of the U9 number selection switch is connected with the A5 end of the U10 level conversion chip; the A4 end of the U9 number selection switch is connected with the A4 end of the U10 level conversion chip; 20 pins of the U9 digital selection switch are connected with the A3 end of the U10 level conversion chip; the 21 feet of the U9 number selection switch is connected with the A2 end of the U10 level conversion chip; the 22 feet of the U9 number selection switch is connected with the A1 end of the U10 level conversion chip; the DIR end of the U10 level conversion chip is connected with one end of a capacitor C38, and the DIR end of the U10 level conversion chip is grounded; the VCCA end of the U10 level conversion chip is connected with the other end of the capacitor C38, and the VCCA end of the U10 level conversion chip is connected with + 5V; the B3 end of the U10 level conversion chip is connected with one end of a resistor R80, the B2 end of the U10 level conversion chip is connected with one end of a resistor R83, and the B1 end of the U10 level conversion chip is connected with one end of a resistor R85; the other end of the resistor R80 and the other end of the resistor R83 are connected with the other end of the resistor R85; the OE end of the U10 level conversion chip is connected with one end of the capacitor C40; the OE end of the U10 level conversion chip is grounded; the VCCB23 end and the VCCB24 end of the U10 level conversion chip are both connected with the other end of the capacitor C40; the other end of the capacitor C40 is 3.3 v.

The connection relationships of all the first input channel modules and the connection relationships of the resistors and the capacitors are shown in table 1

TABLE 1 first input channel Module connectivity

U9 is ADG732 multichannel number selection switch, and the acquisition input end is 32 ways, can select to open appointed single way switch in 32 ways according to control end input A0 to A4 address code, through the control to control end input address code, can select the order and the time that the number selection switch opened. The U10 is a level conversion chip, the front end of the chip is connected with a control chip FPGA, and the FPGA sends an A0-A4 address signal, a chip selection signal, a programming signal and an enabling signal which are required by the control of a digital selection switch. The control signal is converted from 3.3V level to 5V level signal after passing through U10, and then is input into the digital selection switch to be controlled. When no signal is input, the chip selection signal, the programming signal and the enable signal are pulled up to 3.3V through the resistors R80, R83 and R85, and the digital selection switch is closed by default.

Analog signals needing to be collected from the outside enter the digital selection switch U9 after passing through an RC filter network, the U9 is controlled by control signals converted by the U10, a designated single path is selectively opened, the analog signals input by opening a path enter the rear end of the digital selection switch, and the analog signals are input into a rear end circuit through a pin 43 of a chip.

The second input channel module is an acquisition channel expansion module, a circuit schematic diagram is completely the same as that of the first input channel module, when the number of signal paths needing to be acquired is greater than 32, the second input channel module starts to work to realize the acquisition of signals from the 33 th path to the 64 th path, if the acquired signals are greater than 64 paths, a third input channel module and a fourth input channel module can be added according to actual conditions until the input channels meet the requirements, and each input channel module can be added with 32 paths of acquisition channels.

Fig. 3 is a schematic diagram of an AD acquisition module according to an embodiment of the present invention. As shown in fig. 3, the AD acquisition module includes a U7 follower amplifier, a U8AD acquisition chip, a capacitor C83, a capacitor C13, a capacitor C27, a capacitor C30, a resistor R26, a capacitor C96, a capacitor C97, a resistor R60, a resistor R61, a resistor R72, a resistor R58, a resistor R65, a resistor R67, a resistor R69, a resistor R71, a capacitor C93, a capacitor C90, a capacitor C91, a capacitor C84, a capacitor C102, a capacitor C94, a capacitor C95, a capacitor C99, a capacitor C72, and a capacitor C85; the OUT1 end and the IN1 end of the U7 follower amplifier are both connected with one end of a resistor R24, and the other end of the resistor R24 is respectively connected with the V1 end of the U8AD acquisition chip and one end of a capacitor C27; the other end of the capacitor C27 is connected with one end of the capacitor C30 and is grounded; the OUT2 end and the IN2 end of the U7 follower amplifier are both connected with one end of a resistor R22, and the other end of the resistor R22 is respectively connected with the V3 end of the U8AD acquisition chip and the other end of a capacitor C30; the VCC + end of the U7 following amplifier is connected with one end of a capacitor C83, and the VCC + end of the U7 following amplifier is connected with + 15V; the VCC-terminal of the U7 follower amplifier is connected with one end of a capacitor C13, the other end of the capacitor C13 is connected with the other end of the capacitor C83 and is grounded, and the VCC-terminal of the U7 follower amplifier is-15V; one end of the resistor R26 is respectively connected with the V2 end, the V4 end, the V5 end and the V6 end of the U8AD acquisition chip, and the other end of the resistor R26 is grounded; one end of the capacitor C72 and one end of the capacitor C85 are both connected with the other end of the MB2, and one end of the capacitor C72 and one end of the capacitor C85 are both connected with the DVCC end of the U8AD acquisition chip; the other end of the capacitor C72 and the other end of the capacitor C85 are both connected with the ground; the DVCC end of the U8AD acquisition chip is connected with the other end of the MB2, one end of the MB2 is connected with one end of the capacitor C102 and one end of the capacitor C94, and the other end of the capacitor C102 and the other end of the capacitor C94 are grounded; an AVCC34 end, an AVCC35 end, an AVCC40 end, an AVCC41 end, an AVCC46 end, an AVCC47 end, an AVCC50 end and an AVCC60 end of the U8AD acquisition chip are all connected with one end of a capacitor C102; one end of the capacitor C93 is connected with the pin 51 of the U8AD acquisition chip, and the other end of the capacitor C93 is grounded; one end of the capacitor C90 is connected with the pin 54 of the U8AD acquisition chip, and the other end of the capacitor C90 is grounded; one end of the capacitor C91 is connected with the pin 56 of the U8AD acquisition chip, and the other end of the capacitor C91 is grounded; one end of the resistor R71 is connected with the pin 28 of the U8AD acquisition chip, and the other end of the resistor R71 is grounded; one end of the capacitor C73 is connected with the pin 9 of the U8AD acquisition chip, and the pin 9 of the U8AD acquisition chip is connected with 3.3V voltage; the other end of the capacitor C73 is grounded; one end of the resistor R69 is connected with the pin 23 of the U8AD acquisition chip, and the other end of the resistor R69 is grounded; one end of the resistor R67 is connected with the pin 22 of the U8AD acquisition chip, and the other end of the resistor R67 is grounded; one end of the resistor R65 is connected with the pin 21 of the U8AD acquisition chip, and the other end of the resistor R65 is grounded; one end of the resistor R72 is connected with the pin 24 of the U8AD acquisition chip, and the other end of the resistor R72 is connected with 3.3V; one end of the resistor R58 is connected with the pin 63 of the U8AD acquisition chip, and the other end of the resistor R72 is connected with 3.3V; one end of the resistor R61 is connected with the pin 20 of the U8AD acquisition chip, and the other end of the resistor R61 is connected with 3.3V; one end of the resistor R60 is connected with the pin 19 of the U8AD acquisition chip, and the other end of the resistor R60 is connected with 3.3V; one end of the capacitor C96 is connected with an AGND32 end, an AGND37 end, an AGND38 end, an AGND43 end, an AGND44 end, an AGND49 end, an AGND52 end, an AGND53 end, an AGND55 end, an AGND57 end and an AGND59 end of the U10 level conversion chip; one end of the capacitor C97 is connected with an AGND32 end, an AGND37 end, an AGND38 end, an AGND43 end, an AGND44 end, an AGND49 end, an AGND52 end, an AGND53 end, an AGND55 end, an AGND57 end and an AGND59 end of the U10 level conversion chip; the other end of the capacitor C96 is connected with the VSS end of the U10 level conversion chip, the other end of the capacitor C97 is connected with the VSS end of the U10 level conversion chip, and the VSS end of the U10 level conversion chip is connected with-15V.

The connection relationship of the AD acquisition modules is shown in Table 2:

TABLE 2 AD Collection Module connection

U7 is TLE2142 double-circuit follower amplifier, uses as the active filtering chip in the circuit, and the single-circuit analog signal that first input channel and second input channel gathered gets into after U7, gets into AD acquisition chip U8 after U7 active filtering and rear end RC passive filtration. U8 is AD acquisition chip, and the chip model is AD7656 YSTZ. The chip can support 6 paths of AD signal acquisition at most, the acquisition range is +/-10V, the acquisition precision is 16 bits, the acquisition conversion time is 3.1us, and the throughput rate is 250 KSPS. Analog quantity signals after active filtering and passive filtering enter an AD chip, then are converted into 16-bit digital quantity to be output, and output signals enter a rear-end FPGA.

Fig. 4 is a schematic diagram of a control core module according to an embodiment of the present invention. As shown in fig. 4, the control core module includes an FPGA, a 32M crystal oscillator U3, an 8-way level shift chip U11, an 8-way level shift chip U13, and a single-way level shift chip U12; the 8-channel level conversion chip U13 and the one-channel level conversion chip U12 convert 5V control signals output by an upper computer into 3.3V control signals to be input into the FPGA, and the 8-channel level conversion chip U11 converts 8-bit 3.3V level acquisition data output by the single chip microcomputer into 5V acquisition data to be reported to the upper computer; the 32M crystal oscillator U3 provides a 32M crystal oscillator clock for the FPGA for internal frequency division calculation of the FPGA.

The connection relationships among all the control core modules and the connection relationships among the resistors and capacitors are shown in Table 3, and the connection relationships among the control core modules

The FPGA in the table does not mark the connection relation, the IO port connection relation is connected with other modules, and the connection mode is shown in the connection table of other modules. Other ports on the FPGA are all connected by device standards, and the specific connection mode can be seen in A3P1000-1 chip datasheet.

The control core module comprises chips which are FPGA chips U6, 32M crystal oscillators U3, 8-path level conversion chips U11 and U13 and a single-path level conversion chip U12.

The U13 and U12 level conversion chips are responsible for converting 5V control signals output by an upper computer into 3.3V control signals to be input into the FPGA, and the U11 level conversion chips are responsible for converting 8-bit 3.3V level acquisition data output by the single chip microcomputer into 5V acquisition data to be reported to the upper computer. The U3 crystal oscillator provides 32M crystal oscillator clocks for the FPGA for internal frequency division calculation of the FPGA. The FPGA chip is a control terminal of the control core module, and the model number of the FPGA chip is A3P 1000-1.

Fig. 5 is a schematic diagram of a power supply module according to an embodiment of the present invention. As shown in fig. 5, the power supply module includes a U1 follower amplifier, a capacitor C8, a capacitor C9, a tantalum capacitor C45, a tantalum capacitor C55, a tantalum capacitor C3, a tantalum capacitor C60, a resistor R48, and a resistor R49; the positive electrode of the tantalum capacitor C3 is connected with the VIN 210 end and the VIN 211 end of the U1 following amplifier, and the VIN 210 end and the VIN 211 end of the U1 following amplifier are connected with + 5V; the negative electrode of the tantalum capacitor C3 is grounded; the anode of the tantalum capacitor C45, the anode of the tantalum capacitor C55, one end of the capacitor C8 and one end of the capacitor C9 are all connected with the VIN1 end of the U1 follower amplifier, and the cathode of the tantalum capacitor C45, the cathode of the tantalum capacitor C55, the other end of the capacitor C8 and the other end of the capacitor C9 are all grounded; the anode of the tantalum capacitor C55 is respectively connected with the VIN 23 end of the U1 follower amplifier, the pin 5 of the U1 follower amplifier and the pin 6 of the U1 follower amplifier; u1 follows pin 7 of the amplifier to ground; u1 follows the 8 pins of the amplifier at + 5V; u1 follows the 9 th pin of the amplifier to ground; the anode of the tantalum capacitor C49, one end of the resistor R48 and one end of the resistor R49 are connected with the 23 feet of the U1 follower amplifier; the anode of the tantalum capacitor C49, one end of the resistor R48 and one end of the resistor R49 are connected with the pin 22 of the U1 follower amplifier; the anode of the tantalum capacitor C49, one end of the resistor R48 and one end of the resistor R49 are connected with the 21 pin of the U1 follower amplifier; the negative electrode of the tantalum capacitor C49 is grounded, the other end of the resistor R48 is connected with the 19 pin of the U1 follower amplifier, and the other end of the resistor R49 is connected with the 18 pin of the U1 follower amplifier; the positive electrode of the tantalum capacitor C60 is connected with the 16 pin, the 15 pin and the 14 pin of the U1 follower amplifier, and the negative electrode of the tantalum capacitor C60 is grounded; u1 follows the amplifier pins 13, 24 to ground.

The connection relationships among all the power supply modules, the connection relationships among the resistors and the capacitors are shown in table 4, and the connection relationships among the power supply modules

After an external 5V power supply is input into a product, a power supply module generates stable 3.3V voltage and 1.5V voltage for internal use of the product.

As shown in fig. 1, after the module of the present invention is reset and receives a synchronous frame command of an external signal, the control chip sequentially switches the analog switches by sending an address gating command of the corresponding analog switch. After the analog switch is switched on, signals collected by the corresponding channels are synchronously amplified and then collected by a bipolar 16-bit one-way AD chip. The control chip finishes the acquisition and recording of the channel analog signal through a 16-bit parallel port output port of the AD chip. And after the signal acquisition of one period is finished, storing the acquisition values of all the acquisition channels in an external signal reading area. After receiving the next frame of synchronous signal, if the external sending address code is matched with the built-in address code of the product control chip, reporting all data in the control chip in sequence according to the frequency of the external sending reading signal, and completing the cycle of data acquisition and reporting once. And when the control chip receives the external sending synchronous frame again, the control chip collects and reports the plurality of channel analog quantities again.

As shown in fig. 6, the product realizes K-way analog quantity acquisition in a small frame, where K is 10 cases. The channels are divided into 10 channels in a small frame according to a certain rule, and the time intervals among the corresponding acquisition channels among the small frames are ensured to be the same. And the uniform division method is adopted to ensure that all channels needing to be acquired are acquired once in a single small frame. The channel sequence and the number can be adjusted to realize the random change of the acquisition sequence of each channel. And the channel error elimination area reserved behind each small frame can ensure that the acquisition time error is eliminated in the current small frame, and ensure that the acquisition error of a single small frame does not influence the acquisition of large frame data.

As shown in fig. 7, in order to prevent the read/write signals in the control chip from colliding, two storage areas are created in the control chip, which are named as an area a and an area B, respectively, and the area a and the area B are in a ping-pong relationship with each other. And when the Nth frame synchronization rising edge arrives 10 groups of data, the time period from the time point to the (N + 2) th frame synchronization rising edge arrives is the storage time of the group of data, and after the group of analog quantity is stored, the data is sent by the corresponding storage area when the (N + 3) th frame synchronization rising edge arrives. And starting the product to collect and report data simultaneously when the power-on starts until the first synchronous frame is received. The secondary data is the initial data of the area A. After the 10 th data is acquired in the first synchronous frame period, the time from the rising edge of the third synchronous frame is the storage time of the effective data in the area A. The time from the rising edge of the second synchronous frame to the 10 th data acquired in the second synchronous frame period is the acquisition time of the B area, and the time is the initial data of the B area. After the 10 th data is acquired in the second synchronous frame period, the time from the rising edge of the fourth synchronous frame is the storage time of the effective data in the B area. The ping-pong relationship between the area A and the area B meets the matching relationship of 'A-transmission B-acquisition and B-transmission A-acquisition'. The reason why the first group of data acquired by the area a and the area B are invalid data is that when the corresponding system in the area a or the area B sends a data command for the first time, the area a or the area B is in a primary acquisition state, and at this time, the data in the storage area is meaningless, and the reported data is invalid data. In order to ensure no conflict in the data reading and writing process, an internal storage area of the FPGA is divided into an A area and a B area, and a ping-pong reading and writing mode is adopted between the two areas.

As shown in fig. 8, a synchronization frame and a read command are received in the control module. When receiving the frame synchronization signal, the acquisition module starts to acquire the analog quantity. When receiving the rising edge of the reading instruction and the address codes are matched, preparing data of the corresponding storage area to a parallel port sending end according to the ping-pong reading and writing requirement when reading the rising edge of the signal, waiting for the upper computer to read, and when receiving the falling edge of the reading instruction, sequentially transmitting the prepared 10-channel acquisition data (parallel port transmission).

Although the present invention has been described with reference to the preferred embodiments, it is not intended to limit the present invention, and those skilled in the art can make variations and modifications of the present invention without departing from the spirit and scope of the present invention by using the methods and technical contents disclosed above.

Claims

1. A multi-channel programmable acquisition system based on software channel configuration item reconstruction is characterized by comprising: the device comprises a first input channel module, a second input channel module, an AD acquisition module, a power supply module and a control core module; wherein the content of the first and second substances,

after a control signal sent by an upper computer is input into a control core module, the control core module controls a specified channel in a first input channel module or a second input channel module to be opened according to a control signal sending address signal, an analog quantity signal needing to be collected from the outside enters an AD collection module through the specified channel, the AD collection module converts the analog quantity signal into a 16-bit digital quantity signal to be input into the control core module, the control core module writes the first 8 bits of the 16-bit digital quantity signal into a storage area, and after the upper computer sends a reading signal, the collected first 8-bit digital quantity signals are sequentially reported to complete the collection of the analog quantity signal;

the power supply module supplies power to the first input channel module, the second input channel module, the AD acquisition module and the control core module respectively.

2. The multi-channel programmable acquisition system based on software channel configuration item reconstruction as claimed in claim 1, characterized in that: the first input channel module and the second input channel module are of the same structure and comprise: the circuit comprises a U9 digital selection switch, a U10 level conversion chip, a capacitor C119, a capacitor C38, a capacitor C40, a resistor R80, a resistor R83 and a resistor R85; wherein the content of the first and second substances,

a VDD13 terminal and a VDD14 terminal of the U9 digital selection switch are both connected with one end of the capacitor C119, and a Vss124 terminal and a GND23 terminal of the U9 digital selection switch are both connected with the other end of the capacitor C119;

the GND11 end and the GND12 end of the U10 level conversion chip are both connected with the other end of the capacitor C119;

the A0 end of the U9 number selection switch is connected with the A8 end of the U10 level conversion chip;

the A1 end of the U9 number selection switch is connected with the A7 end of the U10 level conversion chip;

the A2 end of the U9 number selection switch is connected with the A6 end of the U10 level conversion chip;

the A3 end of the U9 number selection switch is connected with the A5 end of the U10 level conversion chip;

the A4 end of the U9 number selection switch is connected with the A4 end of the U10 level conversion chip;

20 pins of the U9 digital selection switch are connected with the A3 end of the U10 level conversion chip;

the 21 feet of the U9 number selection switch is connected with the A2 end of the U10 level conversion chip;

the 22 feet of the U9 number selection switch is connected with the A1 end of the U10 level conversion chip;

the DIR end of the U10 level conversion chip is connected with one end of a capacitor C38, and the DIR end of the U10 level conversion chip is grounded;

the VCCA end of the U10 level conversion chip is connected with the other end of the capacitor C38, and the VCCA end of the U10 level conversion chip is connected with + 5V;

the B3 end of the U10 level conversion chip is connected with one end of a resistor R80, the B2 end of the U10 level conversion chip is connected with one end of a resistor R83, and the B1 end of the U10 level conversion chip is connected with one end of a resistor R85;

the other end of the resistor R80 and the other end of the resistor R83 are connected with the other end of the resistor R85;

the OE end of the U10 level conversion chip is connected with one end of the capacitor C40; the OE end of the U10 level conversion chip is grounded;

the VCCB23 end and the VCCB24 end of the U10 level conversion chip are both connected with the other end of the capacitor C40; the other end of the capacitor C40 is 3.3 v.

3. The multi-channel programmable acquisition system based on software channel configuration item reconstruction as claimed in claim 1, characterized in that: the AD acquisition module comprises a U7 follower amplifier, a U8AD acquisition chip, a capacitor C83, a capacitor C13, a capacitor C27, a capacitor C30, a resistor R26, a capacitor C96, a capacitor C97, a resistor R60, a resistor R61, a resistor R72, a resistor R58, a resistor R65, a resistor R67, a resistor R69, a resistor R71, a capacitor C93, a capacitor C90, a capacitor C91, a capacitor C84, a capacitor C102, a capacitor C94, a capacitor C95, a capacitor C99, a capacitor C72 and a capacitor C85; wherein the content of the first and second substances,

the OUT1 end and the IN1 end of the U7 follower amplifier are both connected with one end of a resistor R24, and the other end of the resistor R24 is respectively connected with the V1 end of the U8AD acquisition chip and one end of a capacitor C27; the other end of the capacitor C27 is connected with one end of the capacitor C30 and is grounded;

the OUT2 end and the IN2 end of the U7 follower amplifier are both connected with one end of a resistor R22, and the other end of the resistor R22 is respectively connected with the V3 end of the U8AD acquisition chip and the other end of a capacitor C30;

the VCC + end of the U7 following amplifier is connected with one end of a capacitor C83, and the VCC + end of the U7 following amplifier is connected with + 15V;

the VCC-terminal of the U7 follower amplifier is connected with one end of a capacitor C13, the other end of the capacitor C13 is connected with the other end of the capacitor C83 and is grounded, and the VCC-terminal of the U7 follower amplifier is-15V;

one end of the resistor R26 is respectively connected with the V2 end, the V4 end, the V5 end and the V6 end of the U8AD acquisition chip, and the other end of the resistor R26 is grounded;

one end of the capacitor C72 and one end of the capacitor C85 are both connected with the other end of the MB2, and one end of the capacitor C72 and one end of the capacitor C85 are both connected with the DVCC end of the U8AD acquisition chip; the other end of the capacitor C72 and the other end of the capacitor C85 are both connected with the ground;

the DVCC end of the U8AD acquisition chip is connected with the other end of the MB2, one end of the MB2 is connected with one end of the capacitor C102 and one end of the capacitor C94, and the other end of the capacitor C102 and the other end of the capacitor C94 are grounded;

an AVCC34 end, an AVCC35 end, an AVCC40 end, an AVCC41 end, an AVCC46 end, an AVCC47 end, an AVCC50 end and an AVCC60 end of the U8AD acquisition chip are all connected with one end of a capacitor C102;

one end of the capacitor C93 is connected with the pin 51 of the U8AD acquisition chip, and the other end of the capacitor C93 is grounded;

one end of the capacitor C90 is connected with the pin 54 of the U8AD acquisition chip, and the other end of the capacitor C90 is grounded;

one end of the capacitor C91 is connected with the pin 56 of the U8AD acquisition chip, and the other end of the capacitor C91 is grounded;

one end of the resistor R71 is connected with the pin 28 of the U8AD acquisition chip, and the other end of the resistor R71 is grounded;

one end of the capacitor C73 is connected with the pin 9 of the U8AD acquisition chip, and the pin 9 of the U8AD acquisition chip is connected with 3.3V voltage; the other end of the capacitor C73 is grounded;

one end of the resistor R69 is connected with the pin 23 of the U8AD acquisition chip, and the other end of the resistor R69 is grounded;

one end of the resistor R67 is connected with the pin 22 of the U8AD acquisition chip, and the other end of the resistor R67 is grounded;

one end of the resistor R65 is connected with the pin 21 of the U8AD acquisition chip, and the other end of the resistor R65 is grounded;

one end of the resistor R72 is connected with the pin 24 of the U8AD acquisition chip, and the other end of the resistor R72 is connected with 3.3V;

one end of the resistor R58 is connected with the pin 63 of the U8AD acquisition chip, and the other end of the resistor R72 is connected with 3.3V;

one end of the resistor R61 is connected with the pin 20 of the U8AD acquisition chip, and the other end of the resistor R61 is connected with 3.3V;

one end of the resistor R60 is connected with the pin 19 of the U8AD acquisition chip, and the other end of the resistor R60 is connected with 3.3V;

one end of the capacitor C96 is connected with an AGND32 end, an AGND37 end, an AGND38 end, an AGND43 end, an AGND44 end, an AGND49 end, an AGND52 end, an AGND53 end, an AGND55 end, an AGND57 end and an AGND59 end of the U10 level conversion chip;

one end of the capacitor C97 is connected with an AGND32 end, an AGND37 end, an AGND38 end, an AGND43 end, an AGND44 end, an AGND49 end, an AGND52 end, an AGND53 end, an AGND55 end, an AGND57 end and an AGND59 end of the U10 level conversion chip;

the other end of the capacitor C96 is connected with the VSS end of the U10 level conversion chip, the other end of the capacitor C97 is connected with the VSS end of the U10 level conversion chip, and the VSS end of the U10 level conversion chip is connected with-15V.

4. The multi-channel programmable acquisition system based on software channel configuration item reconstruction as claimed in claim 1, characterized in that: the power supply module comprises a U1 follower amplifier, a capacitor C8, a capacitor C9, a tantalum capacitor C45, a tantalum capacitor C55, a tantalum capacitor C3, a tantalum capacitor C60, a resistor R48 and a resistor R49; wherein the content of the first and second substances,

the anode of the tantalum capacitor C3 is connected with the VIN 210 end and the VIN 211 end of the U1 follower amplifier, and the VIN 210 end and the VIN 211 end of the U1 follower amplifier are connected with + 5V; the negative electrode of the tantalum capacitor C3 is grounded;

the anode of the tantalum capacitor C45, the anode of the tantalum capacitor C55, one end of the capacitor C8 and one end of the capacitor C9 are all connected with the VIN1 end of the U1 follower amplifier, and the cathode of the tantalum capacitor C45, the cathode of the tantalum capacitor C55, the other end of the capacitor C8 and the other end of the capacitor C9 are all grounded;

the anode of the tantalum capacitor C55 is respectively connected with the VIN 23 end of the U1 follower amplifier, the pin 5 of the U1 follower amplifier and the pin 6 of the U1 follower amplifier;

u1 follows pin 7 of the amplifier to ground; u1 follows the 8 pins of the amplifier at + 5V; u1 follows the 9 th pin of the amplifier to ground;

the anode of the tantalum capacitor C49, one end of the resistor R48 and one end of the resistor R49 are connected with the 23 feet of the U1 follower amplifier;

the anode of the tantalum capacitor C49, one end of the resistor R48 and one end of the resistor R49 are connected with the pin 22 of the U1 follower amplifier;

the anode of the tantalum capacitor C49, one end of the resistor R48 and one end of the resistor R49 are connected with the 21 pin of the U1 follower amplifier;

the negative electrode of the tantalum capacitor C49 is grounded, the other end of the resistor R48 is connected with the 19 pin of the U1 follower amplifier, and the other end of the resistor R49 is connected with the 18 pin of the U1 follower amplifier;

the positive electrode of the tantalum capacitor C60 is connected with the 16 pin, the 15 pin and the 14 pin of the U1 follower amplifier, and the negative electrode of the tantalum capacitor C60 is grounded;

u1 follows the amplifier pins 13, 24 to ground.