CN111052362A - 合金扩散阻挡层 - Google Patents

合金扩散阻挡层 Download PDF

Info

Publication number
CN111052362A
CN111052362A CN201880056085.1A CN201880056085A CN111052362A CN 111052362 A CN111052362 A CN 111052362A CN 201880056085 A CN201880056085 A CN 201880056085A CN 111052362 A CN111052362 A CN 111052362A
Authority
CN
China
Prior art keywords
metal
copper
barrier layer
solder
molybdenum
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201880056085.1A
Other languages
English (en)
Other versions
CN111052362B (zh
Inventor
N·戴德文德
S·F·帕沃内
C·D·马纳克
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Texas Instruments Inc
Original Assignee
Texas Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Texas Instruments Inc filed Critical Texas Instruments Inc
Publication of CN111052362A publication Critical patent/CN111052362A/zh
Application granted granted Critical
Publication of CN111052362B publication Critical patent/CN111052362B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D3/00—Electroplating: Baths therefor
    • C25D3/02—Electroplating: Baths therefor from solutions
    • C25D3/30—Electroplating: Baths therefor from solutions of tin
    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D3/00—Electroplating: Baths therefor
    • C25D3/02—Electroplating: Baths therefor from solutions
    • C25D3/56—Electroplating: Baths therefor from solutions of alloys
    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D3/00—Electroplating: Baths therefor
    • C25D3/02—Electroplating: Baths therefor from solutions
    • C25D3/56—Electroplating: Baths therefor from solutions of alloys
    • C25D3/562—Electroplating: Baths therefor from solutions of alloys containing more than 50% by weight of iron or nickel or cobalt
    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D3/00—Electroplating: Baths therefor
    • C25D3/02—Electroplating: Baths therefor from solutions
    • C25D3/56—Electroplating: Baths therefor from solutions of alloys
    • C25D3/60—Electroplating: Baths therefor from solutions of alloys containing more than 50% by weight of tin
    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D5/00—Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
    • C25D5/02—Electroplating of selected surface areas
    • C25D5/022—Electroplating of selected surface areas using masking means
    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D5/00—Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
    • C25D5/10—Electroplating with more than one layer of the same or of different metals
    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D5/00—Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
    • C25D5/10—Electroplating with more than one layer of the same or of different metals
    • C25D5/12—Electroplating with more than one layer of the same or of different metals at least one layer being of nickel or chromium
    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D5/00—Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
    • C25D5/18—Electroplating using modulated, pulsed or reversing current
    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D5/00—Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
    • C25D5/48—After-treatment of electroplated surfaces
    • C25D5/50—After-treatment of electroplated surfaces by heat-treatment
    • C25D5/505—After-treatment of electroplated surfaces by heat-treatment of electroplated tin coatings, e.g. by melting
    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D7/00—Electroplating characterised by the article coated
    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D7/00—Electroplating characterised by the article coated
    • C25D7/12—Semiconductors
    • C25D7/123—Semiconductors first coated with a seed layer or a conductive layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/288—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49517—Additional leads
    • H01L23/49524—Additional leads the additional leads being a tape carrier or flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49579—Lead-frames or other flat leads characterised by the materials of the lead frames or layers thereon
    • H01L23/49582—Metallic layers on lead frames
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D3/00—Electroplating: Baths therefor
    • C25D3/02—Electroplating: Baths therefor from solutions
    • C25D3/38—Electroplating: Baths therefor from solutions of copper
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/288—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition
    • H01L21/2885—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition using an external electrical current, i.e. electro-deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/7685—Barrier, adhesion or liner layers the layer covering a conductive structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76885—By forming conductive members before deposition of protective insulating material, e.g. pillars, studs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/0502—Disposition
    • H01L2224/05022—Disposition the internal layer being at least partially embedded in the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05075—Plural internal layers
    • H01L2224/0508—Plural internal layers being stacked
    • H01L2224/05085—Plural internal layers being stacked with additional elements, e.g. vias arrays, interposed between the stacked layers
    • H01L2224/05089—Disposition of the additional element
    • H01L2224/05093—Disposition of the additional element of a plurality of vias
    • H01L2224/05096—Uniform arrangement, i.e. array
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05124—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05155—Nickel [Ni] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05571—Disposition the external layer being disposed in a recess of the surface
    • H01L2224/05572—Disposition the external layer being disposed in a recess of the surface the external layer extending out of an opening
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/114—Manufacturing methods by blanket deposition of the material of the bump connector
    • H01L2224/1146—Plating
    • H01L2224/11462—Electroplating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/1147—Manufacturing methods using a lift-off mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/118—Post-treatment of the bump connector
    • H01L2224/11848—Thermal treatments, e.g. annealing, controlled cooling
    • H01L2224/11849—Reflowing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13075—Plural core members
    • H01L2224/1308—Plural core members being stacked
    • H01L2224/13083—Three-layer arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13109—Indium [In] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13111—Tin [Sn] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13113—Bismuth [Bi] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13139—Silver [Ag] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/13198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/13199—Material of the matrix
    • H01L2224/132—Material of the matrix with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13263—Material of the matrix with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/13284—Tungsten [W] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/1354—Coating
    • H01L2224/13575—Plural coating layers
    • H01L2224/1358—Plural coating layers being stacked
    • H01L2224/13582—Two-layer coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/1354—Coating
    • H01L2224/13599—Material
    • H01L2224/136—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13601—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13609—Indium [In] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/1354—Coating
    • H01L2224/13599—Material
    • H01L2224/136—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13601—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13611—Tin [Sn] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/1354—Coating
    • H01L2224/13599—Material
    • H01L2224/136—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13601—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13613—Bismuth [Bi] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/1354—Coating
    • H01L2224/13599—Material
    • H01L2224/136—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13639—Silver [Ag] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/1354—Coating
    • H01L2224/13599—Material
    • H01L2224/136—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13655—Nickel [Ni] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/1354—Coating
    • H01L2224/13599—Material
    • H01L2224/136—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13657—Cobalt [Co] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/1354—Coating
    • H01L2224/13599—Material
    • H01L2224/136—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13663—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/1368—Molybdenum [Mo] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/1354—Coating
    • H01L2224/13599—Material
    • H01L2224/136—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13663—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/13684—Tungsten [W] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/1354—Coating
    • H01L2224/13599—Material
    • H01L2224/13693—Material with a principal constituent of the material being a solid not provided for in groups H01L2224/136 - H01L2224/13691, e.g. allotropes of carbon, fullerene, graphite, carbon-nanotubes, diamond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/165—Material
    • H01L2224/16501—Material at the bonding interface
    • H01L2224/16503—Material at the bonding interface comprising an intermetallic compound
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81191—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
    • H01L2224/81815—Reflow soldering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01057—Lanthanum [La]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01058—Cerium [Ce]

Landscapes

  • Chemical & Material Sciences (AREA)
  • Engineering & Computer Science (AREA)
  • Organic Chemistry (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Metallurgy (AREA)
  • Materials Engineering (AREA)
  • Electrochemistry (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Wire Bonding (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

一种微电子装置(100)包括回流结构(110)。回流结构(110)具有含铜构件(114)和焊料构件(118)以及在它们之间的阻挡层(116)。阻挡层(116)具有金属颗粒(120)，和在金属颗粒(120)之间的扩散阻挡填料(122)。金属颗粒(120)至少包含第一金属和第二金属，该第一金属和第二金属各自选自镍、钴、镧和铈，其中该第一金属和第二金属各自在金属颗粒中的浓度为至少10重量％。扩散阻挡填料(122)至少包含第三金属，该第三金属选自钨和钼。钨和钼在扩散阻挡填料(122)中的组合浓度高于在金属颗粒(120)中的组合浓度，以提供期望的铜扩散阻力。阻挡层(116)包含的钨和钼的组合浓度为2重量％至15重量％。

Description

合金扩散阻挡层
技术领域
本申请总体涉及微电子装置，并且更具体地，涉及微电子装置中的阻挡层。
背景技术
许多微电子装置具有凸块接合结构以提供与引线框架和其他封装端子的连接，该凸块接合结构具有铜柱和在铜柱上的焊料凸块。对铜柱的小型化和较高的柱密度的需求的增加已经增加了通过铜柱和焊料凸块的电流密度。焊料直接接触铜柱的凸块接合结构中的电迁移故障归因于铜和焊料(其通常含有锡)的界面处金属间化合物的耗尽。这些故障使得在铜和焊料之间使用阻挡层。据报道，镍、镍磷、镍磷钨、镍铁磷、镍铼磷、钴磷和钴钨磷是阻挡层的潜在候选方案。这些层中的每个都具有缺点。镍形成脆性金属间化合物Ni3Sn4，这可带来可靠性问题。即使在低回流温度下铜上的薄镍层可减少与富锡焊料的界面反应，但在较高的温度下执行较长时段的回流工艺时，其可能不是那么有效。其余建议的阻挡层组合物与富锡焊料反应，导致形成脆性金属间化合物，从而在凸块接合结构中产生断裂或空隙。
发明内容
在所描述的示例中，微电子装置具有回流结构，该回流结构具有含铜构件和焊料构件以及在含铜构件和焊料构件之间的阻挡层。阻挡层具有金属颗粒，和在金属颗粒之间的扩散阻挡填料。
金属颗粒至少包含第一金属和第二金属，该第一金属和第二金属在金属颗粒中的浓度分别为至少10重量％。第一金属和第二金属选自镍、钴、镧和铈。金属颗粒中镍、钴、镧和铈的组合浓度为至少85重量％。
阻挡层至少包含第三金属，该第三金属选自钨和钼。阻挡层包含的钨和钼的组合浓度为至少2重量％且小于15重量％。扩散阻挡填料中钨和钼的组合浓度高于金属颗粒中钨和钼的组合浓度。
在一个方面，可使回流结构表现为凸块接合结构，可使含铜构件表现为含铜柱，并且可使焊料构件表现为焊料凸块。在另一个方面，可使回流结构表现为引线框架封装，可使含铜构件表现为含铜引线框架端子，并且可使焊料构件表现为焊料层。
可通过将第一金属、第二金属和第三金属同时镀覆到含铜构件上来形成阻挡层。第三金属从金属颗粒的内部扩散出来，以在金属颗粒之间的扩散阻挡填料中累积。
附图说明
图1是示例微电子装置的剖视图，该微电子装置包括含铜柱、阻挡层和焊料凸块。
图2A至图2E是在示例形成方法的阶段中描绘的微电子装置的剖视图，该微电子装置包括含铜柱、阻挡层和焊料凸块。
图3描绘示例反向脉冲镀覆波形。
图4A和图4B描绘在示例形成方法的阶段中描绘的微电子装置，该微电子装置具有包括阻挡层的引线框架。
具体实施方式
附图未按比例绘制。该描述不受动作或事件的示出排序的限制，因为一些动作或事件可以以不同的顺序发生和/或与其他动作或事件同时发生。此外，一些示出的动作或事件可以是任选地用于实施根据该描述的方法。
微电子装置包括回流结构，诸如凸块接合结构或引线框架封装。回流结构具有含铜构件和焊料构件，以及在含铜构件和焊料构件之间的阻挡层。阻挡层具有金属颗粒，其中在金属颗粒之间具有扩散阻挡填料。焊料构件可包含锡，以及其他金属，诸如铋、铟或银。焊料构件的回流温度在150℃至400℃之间。焊料构件可包含至少25重量％的锡，以提供期望的回流温度和期望的性质，诸如硬度和电导率。
金属颗粒至少包含第一金属和第二金属，其中该第一金属和第二金属各自在金属颗粒中的浓度分别为至少10重量％。第一金属和第二金属选自镍、钴、镧和铈。金属颗粒可包含来自该镍、钴、镧和铈组的附加金属。金属颗粒中镍、钴、镧和铈的组合浓度为至少85重量％。金属颗粒可形成比Ni3Sn4更具延伸性的混合的锡金属间化合物，从而有利地减少了可靠性问题。
阻挡层包含至少2重量％的第三金属，该第三金属选自钨和钼。阻挡层可包含钨和钼两者。扩散阻挡填料中钨和钼的组合浓度高于金属颗粒中钨和钼的组合浓度，以提供期望的铜扩散阻力。阻挡层包含的钨和钼的组合浓度小于15重量％。在阻挡层中具有至少2重量％的钨和钼可有利地提供：与相等厚度的镍相比，扩散阻挡填料降低了铜通过阻挡层的扩散。具有小于15重量％的钨和钼可使阻挡层的电导率保持在期望值以上。
在一个实例中，可使回流结构表现为凸块接合结构，可使含铜构件表现为含铜柱，并且可使焊料构件表现为焊料凸块。在另一个示例中，可使回流结构表现为引线框架封装，其中可使含铜构件表现为含铜引线框架端子，并且可使焊料构件表现为焊料层。具有阻挡层的回流结构的其他表现形式在该描述的范围内。
可通过将第一金属、第二金属和第三金属同时镀覆到含铜构件上来形成阻挡层。第三金属从金属颗粒的内部扩散出来，以在金属颗粒之间的扩散阻挡填料中累积。
在该描述中，如果一个元件被称为在另一个元件上，则其可直接在另一元件上，或可存在介入元件。
图1是示例微电子装置的剖视图，该微电子装置包括含铜柱、阻挡层和焊料凸块。微电子装置100包括电介质层102，该电介质层102可包括二氧化硅、氮化硅或类似电介质材料的一个或多个电介质子层。微电子装置100包括在电介质层102中的互连件104。互连件104可以是顶部互连级的部件，或可以是重新分布层的部件。微电子装置100的接合焊盘106电耦合到互连件104。接合焊盘106可包含铝、铜、镍或适用于接合焊盘的其他金属。保护性外涂(PO)层108位于电介质层102上。PO层108使每个接合焊盘106的至少一部分暴露。PO层108可包括二氧化硅、氮化硅、氮氧化硅、聚酰亚胺、氧化铝或提供对水蒸气和其他污染物的阻挡的其他电介质材料的一个或多个层。
微电子装置100包括在接合焊盘106上的凸块接合结构110。每个凸块接合结构110包括凸块下金属化(UBM)层112，该UBM层112与对应的接合焊盘106电接触。UBM层112可包含钛、镍、钯、铜或适用于金属层的其他金属，该金属层提供对接合焊盘106和凸块接合结构110的镀覆表面的粘附。
每个凸块接合结构110进一步包括在对应的UBM层112上的含铜柱114，该含铜柱114在本文中称为铜柱114。铜柱114可主要包含铜以及百分之几的其他元素，或可基本上由铜组成。
每个凸块接合结构110包括耦合到对应的铜柱114的阻挡层116，和耦合到阻挡层116的焊料的焊料凸块118，使得阻挡层116将铜柱114与焊料凸块118分离。焊料凸块118包含提供150℃至400℃的回流温度的金属。例如，焊料凸块118可包含锡，并且可包含其他金属，诸如铋、铟或银。铅以前曾用于焊料凸块，但在该描述中，由于健康和环境问题，铅通常不用于焊料凸块。
例如，阻挡层116的厚度可为2微米至20微米，以在将铜与焊料凸块中的金属隔离与凸块接合结构110的制造成本和复杂度之间提供期望的平衡。阻挡层116包括金属颗粒120和在金属颗粒120之间的扩散阻挡填料122。金属颗粒120至少包含第一金属和第二金属，该第一金属和第二金属选自镍、钴、镧和铈。第一金属和第二金属各自在金属颗粒120中的浓度分别为至少10重量％。金属颗粒120可包含镍、钴、镧和铈的任何组合。金属颗粒120中的镍、钴、镧和铈的组合浓度为至少85重量％。可选择金属颗粒120的不同组成，以在可靠性和制造成本之间提供期望的平衡。例如，金属颗粒120可包含至少10重量％的镍和至少10重量％的钴，以及小于1重量％的镧和铈。
阻挡层116包含第三金属，该第三金属选自钨和钼。扩散阻挡填料可包含钨和钼两者。扩散阻挡填料122中钨和钼的组合浓度高于金属颗粒120中钨和钼的组合浓度。阻挡层116包含的钨和钼的总浓度为至少2重量％且小于15重量％。可选择扩散阻挡填料122的不同组成，以在可靠性和制造成本之间提供期望的平衡。例如，扩散阻挡填料122可包含钨和非常少量的钼。
阻挡层116可为微电子装置100提供两个优点。首先，金属颗粒120可与焊料凸块118中的锡组合以形成混合的锡金属间化合物124，从而阻止或减少脆性锡-镍金属间化合物Ni3Sn4的形成。混合的锡金属间化合物124比Ni3Sn4更具延伸性，并且因此当凸块接合结构110受到应力时不易破裂和形成空隙，从而有利地减少了可靠性问题。其次，扩散阻挡填料122中的钨或钼减少了铜通过阻挡层116的扩散；铜通过阻挡层116的扩散速率比通过相等厚度的镍的扩散速率低。
图2A至图2E是在示例形成方法的阶段中描绘的微电子装置的剖视图，该微电子装置包括含铜柱、阻挡层和焊料凸块。参照图2A，该示例的微电子装置200包括电介质层202，和在电介质层202中的互连件204。微电子装置200的接合焊盘206电耦合到互连件204。PO层208位于电介质层202上，使每个接合焊盘206的至少一部分暴露。
将UBM层212形成在PO层208上方并且形成在由PO层208暴露的接合焊盘206上。UBM层212可包括具有钛或其他金属的粘附子层，该粘附子层提供对PO层208的良好粘附，并且对接合焊盘206进行低电阻和可靠的电连接。UBM层212可进一步包括在粘附子层上的晶种子层；晶种子层可包含镍、铜或其他金属，以提供用于后续镀覆操作的低薄层电阻层。例如，可通过循序溅射工艺形成UBM层212。
将镀覆掩模226形成在UBM层212上。镀覆掩模226使用于凸块接合结构210的接合焊盘206上方的区域暴露。镀覆掩模226可包含光致抗蚀剂，并且可通过光刻工艺形成。替代地，镀覆掩模226可包含有机聚合物，并且可通过诸如喷墨工艺的加成工艺来形成。
使UBM层212暴露于包含铜的铜镀浴228。如在图2A中指示的，可将铜以硫酸铜的形式添加到铜镀浴228中，其中用酸提供铜镀浴228的期望电导率。可将润湿剂、整平剂、促进剂或抑制剂添加到铜镀浴228中，以提供期望的特性和表面光洁度。使电流从铜镀浴228流动到UBM层212，从而使铜从铜镀浴228镀覆到由镀覆掩模226暴露的UBM层212上，以在每个凸块接合结构210中的UBM层212上形成含铜柱214，该含铜柱214在本文中称为铜柱214。
参照图2B，将镀覆掩模226留在原处，并且将铜柱214暴露于阻挡镀浴230。阻挡镀浴230包含选自镍、钴、镧和铈中的至少两种金属，和选自钨和钼的至少一种金属。如在图2B中指示的，可将镍以硫酸镍的形式添加到阻挡镀浴230中。可将钴以硫酸钴的形式添加到阻挡镀浴230中。可将镧以氧化镧或氯化镧的形式添加到阻挡镀浴230中。可将铈以硫酸铈的形式添加到阻挡镀浴230中。可将钨以钨酸钠的形式添加到阻挡镀浴230中。可将钼以钼酸钠的形式添加到阻挡镀浴230中。阻挡镀浴230可进一步包含添加剂，诸如润湿剂、整平剂、促进剂或抑制剂。将阻挡镀浴230中的金属镀覆到铜柱214上，以在每个凸块接合结构210中的对应的铜柱214上形成阻挡层216。阻挡层216具有参照图1的阻挡层116描述的组成和结构。
可选择阻挡镀浴230的组成，以在可靠性和制造成本之间提供期望的平衡。在一个示例中，阻挡镀浴230可包含镍和钴，并且可基本上不含镧和铈。在另一个示例中，阻挡镀浴230可包含钨，并且可基本上不含钼。
可使用反向的脉冲镀覆工艺(有时称为反向脉冲镀覆工艺)来形成阻挡层216。在将反向的脉冲镀覆工艺应用于阻挡镀浴230期间，使正向电流以一个或多个正向脉冲的形式从阻挡镀浴230流动到铜柱214，从而将金属从阻挡镀浴230镀覆到铜柱214上，以形成阻挡层216的一部分，从而产生部分形成的阻挡层216。选择正向脉冲的幅度和持续时间，以在部分形成的阻挡层216中提供期望的金属颗粒尺寸。在正向脉冲之后，使反向电流以一个或多个反向脉冲的形式从铜柱214流动到阻挡镀浴230，从而从部分形成的阻挡层216的表面选择性地去除钨和钼。选择反向脉冲的幅度和持续时间，以去除期望量的钨和钼。钨和钼从阻挡层216中的金属颗粒的内部扩散并累积，以在金属颗粒的颗粒边界之间形成扩散阻挡填料。因此，反向的脉冲镀覆工艺形成具有参照图1的阻挡层116描述的组成和结构的阻挡层116。
图3描绘示例反向脉冲镀覆波形。波形描绘在垂直轴线上的电流密度随着在水平轴线上的时间的变化关系。在该示例波形中，施加四个正向脉冲，随后施加四个反向脉冲。正向脉冲的正向电流密度可具有比反向脉冲的反向电流密度更大的幅度，以在图2B的阻挡镀浴230和铜柱214之间提供较高的正向电压，用于以期望的组成镀覆阻挡镀浴230中的金属。反向脉冲的反向电流密度的较低幅度可在阻挡镀浴230和铜柱214之间提供足够的电压，以去除处于较高氧化态的钨和钼，诸如W+6和Mo+6，从而在图2B的部分形成的阻挡层216中留下较大比例的具有较低氧化态的镍、钴、镧和铈。正向电流密度的范围可为约0.5安培/平方厘米(A/cm2)至约1.0A/cm2，并且每个正向脉冲的持续时间的范围可为10毫秒至50毫秒，其中占空比为75％至100％，以在阻挡层216中提供期望的金属颗粒结构。反向电流密度可为正向电流密度的35％至60％，并且反向脉冲的持续时间可为正向脉冲持续时间的30％至70％，其中占空比为60％至100％，以在扩散阻挡填料中提供期望量的钨和钼。重复正向脉冲和其后的反向脉冲的组合，以形成具有期望厚度的阻挡层216。
参照图2C，将镀覆掩模226留在原处，并且将阻挡层216暴露于焊料镀浴232。如在图2C中指示的，焊料镀浴232包含诸如锡和银的金属，并且可包含其他金属，诸如铋。焊料镀浴232也可包含润湿剂、整平剂、促进剂或抑制剂。用于焊料镀浴232的其他配方在该示例的范围内。使电流从阻挡层216流动到焊料镀浴232，从而将焊料从焊料镀浴232镀覆到阻挡层216上，以在每个凸块接合结构210中的阻挡层216上形成焊料凸块218。
随后去除镀覆掩模226，将凸块接合结构210留在原处。例如，可通过溶解在有机溶剂或有机酸中或暴露于氧自由基或臭氧来去除镀覆掩模226。在去除镀覆掩模226之后，在由铜柱214暴露的地方去除UBM层212，从而在铜柱214和接合焊盘206之间留下UBM层212。例如，可通过定时湿法蚀刻工艺去除UBM层212。
参照图2D，可任选地加热凸块接合结构210以使焊料凸块218回流。如在图2D中指示的，可通过辐射加热工艺234来加热凸块接合结构210。替代地，可用链炉或加热与凸块接合结构210接触的环境的其他工艺来加热凸块接合结构210。使焊料凸块218回流可需要将焊料凸块218加热到150℃至400℃的温度，这取决于焊料凸块218的组成。使焊料凸块218回流可在焊料凸块218和阻挡层216之间提供更强的连接。如参照图1所述的阻挡层216的结构和组成可在焊料凸块218的回流期间有利地减少铜和锡以及镍和锡的不期望的金属间化合物的形成。
参照图2E，将微电子装置200凸块接合到引线框架236。例如，引线框架236可以是在金属端子240之间具有模制化合物238的预模制的引线框架236。例如，金属端子240可包含铜。在凸块接合工艺中，加热焊料凸块218以使焊料回流，用于将焊料连接到金属端子240。可通过诸如在图2E中指示的辐射加热工艺242或通过环境加热工艺(诸如链炉工艺)来加热焊料凸块218。将微电子装置200凸块接合到引线框架236可需要将焊料凸块218加热到150℃至400℃的温度，这取决于焊料凸块218的组成。可任选地向微电子装置200施加压力以辅助凸块接合工艺。将微电子装置200凸块接合到引线框架236所需的温度可高于参照图2D所述的使焊料凸块218回流所需的温度。阻挡层216的结构和组成可在凸块接合工艺期间有利地减少铜和锡以及镍和锡的不期望的金属间化合物的形成。阻挡层216的结构和组成可进一步减少镍和锡的脆性金属间化合物的形成，这可在引线框架236与微电子装置200之间的机械和热应力期间提高凸块接合结构210的可靠性。
图4A和图4B描绘在示例形成方法的阶段中描绘的微电子装置，该微电子装置具有包括阻挡层的引线框架。参照图4A，微电子装置400包括引线框架436。在该示例中，引线框架436主要包含铜。将第一阻挡层416形成在引线框架436上，以覆盖引线框架436上的用于焊料连接的区域。诸如参照图2B和图2C所描述的，可通过镀覆工艺形成第一阻挡层416。用于形成第一阻挡层416的其他工艺(诸如直流(DC)电镀或化学镀)在该示例的范围内。第一阻挡层416具有如参照图1所述的结构和组成。可将第一阻挡层416定位在用于焊料连接的区域，如图4A所描绘的，或可覆盖引线框架436。
微电子装置400进一步包括具有第二阻挡层446的夹件444。第二阻挡层446覆盖夹件444上的用于焊料连接的区域。第二阻挡层446可具有与第一阻挡层416类似的结构和组成，并且可通过类似的工艺形成。
微电子装置400进一步包括用于焊料连接的焊料材料418。例如，可使焊料材料418表现为焊料预成型件或焊料膏。焊料材料418可包含锡、银、铋或其他金属。
如在图4A中指示的，通过使引线框架436通过第一阻挡层416与焊料材料418接触，并且使夹件444通过第二阻挡层446与焊料材料418接触来形成微电子装置400。
参照图4B，将微电子装置400加热，从而使焊料材料418回流，并且在引线框架436和夹件444之间形成焊料连接。可通过如在图4B中指示的辐射加热工艺442或通过炉工艺来加热微电子装置400。
在焊料回流工艺期间，第一阻挡层416的结构和组成可有利地减少铜和锡以及镍和锡的不期望的金属间化合物的形成。第一阻挡层416的结构和组成可进一步减少镍和锡的脆性金属间化合物的形成，这可在引线框架436和夹件444之间的机械和热应力期间提高微电子装置400的可靠性。在其中第二阻挡层446具有与第一阻挡层416类似的结构和组成的该示例的版本中，可存在相同的优点。
在所描述的实施例中可进行修改，并且其他实施例可在权利要求的范围内。

Claims (20)

1.一种微电子装置，所述微电子装置包括：
回流结构，所述回流结构包括：含铜构件；在所述含铜构件上的阻挡层，所述阻挡层包括金属颗粒和在所述金属颗粒之间的扩散阻挡填料；和在所述阻挡层上的焊料构件，所述焊料构件的回流温度在150℃至400℃之间；
其中：
所述金属颗粒包含至少10重量％的第一金属，所述第一金属选自由镍、钴、镧和铈组成的组；
所述金属颗粒包含至少10重量％的不同于所述第一金属的第二金属，所述第二金属选自由镍、钴、镧和铈组成的组；并且
所述阻挡层包含选自由钨和钼组成的组中的至少一种金属，其中所述阻挡层中的钨和钼的组合浓度大于2重量％且小于15重量％，并且其中所述扩散阻挡填料中的钨和钼的组合浓度高于所述金属颗粒中的钨和钼的组合浓度。
2.根据权利要求1所述的微电子装置，其中：所述金属颗粒包含至少10重量％的镍；所述金属颗粒包含至少10重量％的钴；并且所述金属颗粒包含小于1重量％的镧和铈。
3.根据权利要求1所述的微电子装置，其中所述阻挡层包含小于1重量％的钼。
4.根据权利要求1所述的微电子装置，其中所述阻挡层的厚度为2微米至20微米。
5.根据权利要求1所述的微电子装置，其中：所述回流结构是凸块接合结构；并且所述含铜构件是含铜柱；并且所述焊料构件是焊料凸块。
6.根据权利要求1所述的微电子装置，其中所述回流结构是在引线框架上的焊料连接件，并且所述含铜构件是所述引线框架的含铜端子。
7.根据权利要求1所述的微电子装置，其中所述焊料包含至少25重量％的锡。
8.根据权利要求1所述的微电子装置，其中所述回流结构在所述阻挡层和所述焊料构件之间包含金属间化合物，所述金属间化合物包含来自所述焊料构件的金属和来自所述金属颗粒的至少两种金属。
9.根据权利要求8所述的微电子装置，其中所述金属间化合物比Ni3Sn4更具延展性。
10.根据权利要求1所述的微电子装置，其中所述回流结构不含包含铜和锡的金属间化合物。
11.一种形成微电子装置的方法，所述方法包括：
提供含铜构件；
提供阻挡镀浴，所述阻挡镀浴包含：第一金属，所述第一金属选自由镍、钴、镧和铈组成的组；与所述第一金属不同的第二金属，所述第二金属选自由镍、钴、镧和铈组成的组；和第三金属，所述第三金属选自由钨和钼组成的组；
通过将所述第一金属、所述第二金属和所述第三金属从所述阻挡镀浴同时镀覆到所述含铜构件上来在所述含铜构件上形成阻挡层，所述阻挡层包括金属颗粒和在所述金属颗粒之间的扩散阻挡填料；和
在所述阻挡层上形成焊料构件，所述焊料构件的回流温度在150℃至400℃之间；
其中：
所述金属颗粒包含至少10重量％的第一金属和至少10重量％的与所述第一金属不同的第二金属，其中所述第一金属和所述第二金属各自选自由镍、钴、镧和铈组成的组；
所述阻挡层中的钨和钼的组合浓度大于2重量％且小于15重量％；并且
所述扩散阻挡填料中的钨和钼的组合浓度高于所述金属颗粒中的钨和钼的组合浓度。
12.根据权利要求11所述的方法，其中所述阻挡镀浴包含镍和钴，并且基本不含镧和铈。
13.根据权利要求11所述的方法，其中所述阻挡镀浴包含钨，并且基本上不含钼。
14.根据权利要求11所述的方法，其中使用反向的脉冲镀覆工艺来执行同时镀覆所述第一金属、所述第二金属和所述第三金属，其中正向电流密度的量值大于反向电流密度的量值，其中通过所述正向电流密度将所述第一金属、所述第二金属和所述第三金属从所述阻挡镀浴中镀覆，并且通过所述反向电流密度从所述阻挡层中去除金属。
15.根据权利要求11所述的方法，其中：所述含铜构件是含铜柱；提供所述含铜柱包括将铜镀覆到凸块下金属化(UBM)层上；所述焊料构件是焊料凸块；并且形成焊料构件包括将所述焊料凸块镀覆到所述阻挡层上。
16.根据权利要求11所述的方法，其中所述含铜构件是引线框架的含铜端子。
17.一种形成微电子装置的方法，所述方法包括：
提供回流结构，所述回流结构包括：含铜构件；在所述含铜构件上的阻挡层，所述阻挡层包括金属颗粒和在所述金属颗粒之间的扩散阻挡填料；和在所述阻挡层上的焊料构件，所述焊料构件的回流温度在150℃至400℃之间；
其中：
所述金属颗粒包含至少10重量％的第一金属，所述第一金属选自由镍、钴、镧和铈组成的组；
所述金属颗粒包含至少10重量％的不同于所述第一金属的第二金属，所述第二金属选自由镍、钴、镧和铈组成的组；并且
所述阻挡层包含选自由钨和钼组成的组中的至少一种金属；
所述阻挡层中的钨和钼的组合浓度大于2重量％且小于15重量％；并且
所述扩散阻挡填料中的钨和钼的组合浓度高于所述金属颗粒中的钨和钼的组合浓度；和
将所述回流结构加热至高于所述回流温度，使得所述焊料构件在所述阻挡层和所述微电子装置的构件之间形成连接。
18.根据权利要求17所述的方法，其中：所述回流结构是凸块接合结构；所述含铜构件是含铜柱；并且所述焊料构件是焊料凸块。
19.根据权利要求17所述的方法，其中所述回流结构是引线框架上的焊料连接件，并且所述含铜构件是所述引线框架的含铜端子。
20.根据权利要求17所述的方法，其中：所述金属颗粒包含至少10重量％的镍；所述金属颗粒包含至少10重量％的钴；所述金属颗粒包含小于1重量％的镧和铈；并且所述阻挡层包含小于1重量％的钼。
CN201880056085.1A 2017-09-20 2018-09-20 合金扩散阻挡层 Active CN111052362B (zh)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US201762561070P 2017-09-20 2017-09-20
US62/561,070 2017-09-20
US15/954,254 US10424552B2 (en) 2017-09-20 2018-04-16 Alloy diffusion barrier layer
US15/954,254 2018-04-16
PCT/US2018/051874 WO2019060496A1 (en) 2017-09-20 2018-09-20 ALLOY DIFFUSION BARRIER LAYER

Publications (2)

Publication Number Publication Date
CN111052362A true CN111052362A (zh) 2020-04-21
CN111052362B CN111052362B (zh) 2023-04-21

Family

ID=65720677

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201880056085.1A Active CN111052362B (zh) 2017-09-20 2018-09-20 合金扩散阻挡层

Country Status (4)

Country Link
US (2) US10424552B2 (zh)
JP (1) JP7185375B2 (zh)
CN (1) CN111052362B (zh)
WO (1) WO2019060496A1 (zh)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP7353794B2 (ja) 2019-05-13 2023-10-02 ローム株式会社 半導体装置、その製造方法、及びモジュール
US11380613B2 (en) * 2020-05-29 2022-07-05 Qualcomm Incorporated Repurposed seed layer for high frequency noise control and electrostatic discharge connection
US11753736B2 (en) * 2020-11-16 2023-09-12 Raytheon Company Indium electroplating on physical vapor deposition tantalum
US11862593B2 (en) * 2021-05-07 2024-01-02 Microsoft Technology Licensing, Llc Electroplated indium bump stacks for cryogenic electronics

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1317389A (zh) * 2000-03-24 2001-10-17 德克萨斯仪器股份有限公司 用于铜金属化集成电路的丝焊工艺
US20050085062A1 (en) * 2003-10-15 2005-04-21 Semitool, Inc. Processes and tools for forming lead-free alloy solder precursors
CN101944496A (zh) * 2009-07-02 2011-01-12 台湾积体电路制造股份有限公司 柱状结构及其形成方法、倒装芯片接合结构
US20120007231A1 (en) * 2010-07-08 2012-01-12 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming cu pillar capped by barrier layer

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8148822B2 (en) 2005-07-29 2012-04-03 Megica Corporation Bonding pad on IC substrate and method for making the same
JP2007250849A (ja) 2006-03-16 2007-09-27 Casio Comput Co Ltd 半導体装置の製造方法
JP4829340B2 (ja) 2009-12-25 2011-12-07 株式会社東芝 半導体装置の製造方法
US9598772B2 (en) 2010-04-16 2017-03-21 Taiwan Semiconductor Manufacturing Company, Ltd. Method for fabricating bump structure without UBM undercut
US8922004B2 (en) 2010-06-11 2014-12-30 Taiwan Semiconductor Manufacturing Company, Ltd. Copper bump structures having sidewall protection layers
US8283781B2 (en) 2010-09-10 2012-10-09 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device having pad structure with stress buffer layer
US8664760B2 (en) 2011-05-30 2014-03-04 Taiwan Semiconductor Manufacturing Company, Ltd. Connector design for packaging integrated circuits
US8698308B2 (en) 2012-01-31 2014-04-15 Taiwan Semiconductor Manufacturing Company, Ltd. Bump structural designs to minimize package defects
US9425136B2 (en) 2012-04-17 2016-08-23 Taiwan Semiconductor Manufacturing Company, Ltd. Conical-shaped or tier-shaped pillar connections
US9831201B2 (en) 2015-03-11 2017-11-28 Guy F. Burgess Methods for forming pillar bumps on semiconductor wafers
US9728521B2 (en) * 2015-07-23 2017-08-08 Taiwan Semiconductor Manufacturing Co., Ltd. Hybrid bond using a copper alloy for yield improvement
JP6572673B2 (ja) 2015-08-13 2019-09-11 富士通株式会社 電子装置及び電子装置の製造方法
US9748173B1 (en) * 2016-07-06 2017-08-29 International Business Machines Corporation Hybrid interconnects and method of forming the same
US10431464B2 (en) * 2016-10-17 2019-10-01 International Business Machines Corporation Liner planarization-free process flow for fabricating metallic interconnect structures

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1317389A (zh) * 2000-03-24 2001-10-17 德克萨斯仪器股份有限公司 用于铜金属化集成电路的丝焊工艺
US20050085062A1 (en) * 2003-10-15 2005-04-21 Semitool, Inc. Processes and tools for forming lead-free alloy solder precursors
CN101944496A (zh) * 2009-07-02 2011-01-12 台湾积体电路制造股份有限公司 柱状结构及其形成方法、倒装芯片接合结构
US20120007231A1 (en) * 2010-07-08 2012-01-12 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming cu pillar capped by barrier layer

Also Published As

Publication number Publication date
JP2020534695A (ja) 2020-11-26
US10424552B2 (en) 2019-09-24
US20190088608A1 (en) 2019-03-21
US20200020656A1 (en) 2020-01-16
CN111052362B (zh) 2023-04-21
WO2019060496A1 (en) 2019-03-28
JP7185375B2 (ja) 2022-12-07

Similar Documents

Publication Publication Date Title
CN111052362B (zh) 合金扩散阻挡层
CN102456651B (zh) 具有含钴的侧壁保护层的铜柱
US8592995B2 (en) Method and structure for adhesion of intermetallic compound (IMC) on Cu pillar bump
US9607936B2 (en) Copper bump joint structures with improved crack resistance
US7838954B2 (en) Semiconductor structure with solder bumps
US9881886B2 (en) Semiconductor device assemblies including intermetallic compound interconnect structures
US20060276022A1 (en) Capping copper bumps
EP2276063A2 (en) Improvement of solder interconnect by addition of copper
TWI431702B (zh) 半導體元件及其形成方法
JP2005513759A (ja) 半導体素子及びその形成方法
US20040121267A1 (en) Method of fabricating lead-free solder bumps
TW200926373A (en) Soldering method and related device for improved resistance to brittle fracture
US11587858B2 (en) Zinc-cobalt barrier for interface in solder bond applications
US20200035633A1 (en) Bump bond structure for enhanced electromigration performance
JP2020534695A5 (zh)
US8252677B2 (en) Method of forming solder bumps on substrates
TW201225209A (en) Semiconductor device and method of confining conductive bump material with solder mask patch
US10066303B2 (en) Thin NiB or CoB capping layer for non-noble metallic bonding landing pads
KR100534108B1 (ko) 무연 솔더범프 제조 방법
JP3916850B2 (ja) 半導体装置
US20220262754A1 (en) Sintering a nanoparticle paste for semiconductor chip join
TW200534447A (en) Bump and the fabricating method thereof

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant