CN111033718A - 用于使用通孔阻滞层的薄膜电阻器的装置和方法 - Google Patents
用于使用通孔阻滞层的薄膜电阻器的装置和方法 Download PDFInfo
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- 239000010409 thin film Substances 0.000 title claims abstract description 92
- 238000000034 method Methods 0.000 title claims abstract description 87
- 230000000903 blocking effect Effects 0.000 title description 3
- 239000010410 layer Substances 0.000 claims abstract description 224
- 239000000463 material Substances 0.000 claims abstract description 89
- 238000005530 etching Methods 0.000 claims abstract description 44
- 238000000151 deposition Methods 0.000 claims abstract description 41
- 238000000059 patterning Methods 0.000 claims abstract description 20
- 238000004519 manufacturing process Methods 0.000 claims abstract description 7
- 239000011229 interlayer Substances 0.000 claims abstract description 5
- 229920002120 photoresistant polymer Polymers 0.000 claims description 22
- 239000004065 semiconductor Substances 0.000 claims description 18
- 239000000758 substrate Substances 0.000 claims description 18
- 238000001465 metallisation Methods 0.000 claims description 13
- 229910018487 Ni—Cr Inorganic materials 0.000 claims description 6
- VNNRSPGTAMTISX-UHFFFAOYSA-N chromium nickel Chemical compound [Cr].[Ni] VNNRSPGTAMTISX-UHFFFAOYSA-N 0.000 claims description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 5
- 229910052710 silicon Inorganic materials 0.000 claims description 5
- 239000010703 silicon Substances 0.000 claims description 5
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 claims description 4
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 4
- 239000001301 oxygen Substances 0.000 claims description 4
- 229910052760 oxygen Inorganic materials 0.000 claims description 4
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims description 4
- 229910010271 silicon carbide Inorganic materials 0.000 claims description 4
- 238000004380 ashing Methods 0.000 claims description 3
- DYRBFMPPJATHRF-UHFFFAOYSA-N chromium silicon Chemical compound [Si].[Cr] DYRBFMPPJATHRF-UHFFFAOYSA-N 0.000 claims description 3
- 238000004140 cleaning Methods 0.000 claims description 3
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 2
- 229910004541 SiN Inorganic materials 0.000 claims description 2
- 229910052786 argon Inorganic materials 0.000 claims description 2
- 229910003465 moissanite Inorganic materials 0.000 claims description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 2
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 2
- ASAMIKIYIFIKFS-UHFFFAOYSA-N chromium;oxosilicon Chemical compound [Cr].[Si]=O ASAMIKIYIFIKFS-UHFFFAOYSA-N 0.000 claims 2
- 210000002381 plasma Anatomy 0.000 description 4
- 238000013459 approach Methods 0.000 description 3
- 230000008021 deposition Effects 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 239000000956 alloy Substances 0.000 description 2
- 229910045601 alloy Inorganic materials 0.000 description 2
- 229910052799 carbon Inorganic materials 0.000 description 2
- 230000008878 coupling Effects 0.000 description 2
- 238000010168 coupling process Methods 0.000 description 2
- 238000005859 coupling reaction Methods 0.000 description 2
- 238000013461 design Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 239000003989 dielectric material Substances 0.000 description 2
- 150000004767 nitrides Chemical class 0.000 description 2
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 2
- 101100272788 Arabidopsis thaliana BSL3 gene Proteins 0.000 description 1
- 101150068401 BSL1 gene Proteins 0.000 description 1
- 101150011571 BSL2 gene Proteins 0.000 description 1
- 208000029523 Interstitial Lung disease Diseases 0.000 description 1
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 1
- 238000009825 accumulation Methods 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000012467 final product Substances 0.000 description 1
- 229940104869 fluorosilicate Drugs 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 238000010998 test method Methods 0.000 description 1
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- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
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- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
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- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
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Abstract
在一种制造集成电路(IC)芯片的方法中,该方法包括在第一层间电介质(ILD)层(114)上沉积第一薄膜电阻器材料;覆盖第一薄膜电阻器材料沉积蚀刻阻滞剂层(118);以及图案化并蚀刻该蚀刻阻滞剂层(118)和第一薄膜电阻器材料,以形成第一电阻器(116)。该方法继续:覆盖第一电阻器(116)沉积第二ILD层(120);以及使用第一蚀刻化学过程图案化和蚀刻第二ILD层(120),以形成穿过第二ILD(120)层和蚀刻阻滞剂层(118)到第一电阻器(116)的通孔(122C,122D)。蚀刻阻滞剂层(118)对第一蚀刻化学过程具有选择性,并且蚀刻阻滞剂层(118)的厚度使得通孔蚀刻过程去除蚀刻阻滞剂层(118)的基本上所有暴露部分并且基本上防止下面第一薄膜电阻器材料的消耗。
Description
技术领域
本文总体上涉及薄膜电阻器(TFR),并且更具体地涉及用于使用通孔阻滞层的薄膜电阻器的装置和方法。
背景技术
设计具有多个电阻器的芯片时的一个问题是确保设计为具有相同电阻率的所有电阻器将在最终产品中匹配,从而使电路正常工作。使跨芯片匹配TFR的任务进一步增加复杂性的一个因素是希望通过限制合并形成TFR的过程所需的步骤数量和掩模数量来降低成本。包含需要不同电阻值的多个薄膜电阻器会使过程进一步复杂化。
发明内容
所描述的实施例涉及用于制造具有薄膜电阻器的集成电路的过程。所描述的过程使用蚀刻阻滞剂,其可在蚀刻过程中被完全蚀刻掉,同时在薄膜电阻器材料上提供平缓的着陆。通过在薄膜电阻器材料上提供通孔的平缓着陆,同时还提供与下面的金属层的良好通孔耦合,该过程提供在电气特性方面的显著改善,并促进整个集成电路中电阻器匹配的改善。
在制造集成电路芯片的方法的一个方面中,一种方法包括:在第一层间电介质(ILD)层上沉积第一薄膜电阻器材料;覆盖第一薄膜电阻器材料沉积蚀刻阻滞剂层;图案化并蚀刻该蚀刻阻滞剂层和第一薄膜电阻器材料以形成第一电阻器;覆盖第一电阻器沉积第二ILD层;和使用第一蚀刻化学过程图案化和蚀刻第二ILD层,以形成穿过第二ILD层和蚀刻阻滞剂层到第一电阻的通孔。蚀刻阻滞剂层对第一蚀刻化学过程具有选择性,并且蚀刻阻滞剂层的厚度使得通孔蚀刻去除蚀刻阻滞剂层的基本上所有暴露的部分,并且基本上防止下面的第一薄膜电阻器材料的消耗。
在另一方面中,一种集成电路芯片包括:金属化层;直接覆盖在金属化层上的第一电介质层;在第一电介质层上形成的薄膜电阻器;覆盖薄膜电阻器的蚀刻阻滞剂层;覆盖电阻器的第二电介质层;第一通孔,位于电阻器的第一端附近并延伸穿过第一电介质层和蚀刻阻滞剂层并接触薄膜电阻器;第二通孔,位于电阻器的与第一通孔的相对端,并延伸穿过第一电介质层和蚀刻阻滞剂层并接触薄膜电阻器;和第三通孔,其延伸穿过第一电介质层和第二电介质层以接触金属化层。
附图说明
图1描绘根据一个实施例的在不同层间电介质ILD层上具有两种不同类型的电阻器的示例集成电路(IC)芯片。
图1A-G描绘根据一个实施例的形成图1所示的电阻器的过程中的不同阶段和层。
图2比较包括所描述的方法的几种不同过程提供低薄层电阻器匹配的能力。
图3描绘根据一个实施例的具有单一类型的电阻器的示例集成电路芯片。
图4A-4E描绘根据一个实施例的制造包含TFR的芯片的整体方法。
图5、5A和5B描绘在不同的ILD上具有两种不同类型的电阻器的IC芯片的部分,以及实现该设计必须克服的问题。
具体实施方式
在附图中,相同的附图标记指示相同的元件。在本说明书中,除非符合“可通信耦合”中的限定,否则术语“耦合”是指间接或直接电连接,其可包括无线连接。因此,如果第一设备耦合到第二设备,则该连接可通过直接电连接,或者通过经由其他设备和连接的间接电连接。
图5描绘具有不同电阻率要求的两个电阻器的示例芯片500;这两个电阻器通常形成在不同层级(level)的电介质上。芯片500包括硅衬底502,在其上已经形成集成电路(未具体示出)的组件。在芯片500中示出两个薄膜电阻器,尽管通常提供这些电阻器中的每个的多个版本。通常将薄膜电阻器定义为具有约0.1微米或更小的厚度。这两个电阻器包括薄膜电阻器512和薄膜电阻器517,薄膜电阻器512被认为是高薄层电阻电阻器(在本文中也称为高薄层电阻器(HSR))并且具有电阻基本在500-2000Ω/cm2之间,薄膜电阻器517被认为是低薄层电阻电阻器(在本文中也称为低薄层电阻器(LSR))并且具有基本上在50-300Ω/cm2之间的电阻。在所示示例中,电阻器512、517形成在金属-1层506和金属-2层(未具体示出)之间。电介质层504已经形成在硅衬底502上,其中触点508延伸穿过电介质层504并且将金属-1层506的一部分耦合到衬底502中的下面组件(未具体示出)。电介质层510覆盖金属-1层506。电阻器512形成在电介质510的顶部上,在电介质510之后已经沉积附加电介质层514。穿过电介质层514的开口提供空间,可在形成电阻器517的同时在该空间中形成电阻器头部516。电介质层518覆盖电阻器517和电阻器头部516。通孔520被同时蚀刻以接触三个单独的层:电阻器头部516、电阻器517和金属-1层506。为了提供可到达金属化层506的蚀刻过程,必须注意防止过度蚀刻接触电阻器头部516和电阻器517的通孔。
图5A描绘芯片500A,其中未优化的通孔蚀刻过程被用于同时蚀刻通孔520,尽管仅示出被蚀刻到电阻器512的通孔中的一个。使用为金属-1连接提供良好导通特性的参数执行该过程,但是如芯片500A所示,蚀刻过程已完全穿透电阻器512和电阻器头部516。解决此问题的一种方法是依靠为薄膜电阻器材料提供很高选择性的蚀刻过程。图5B描绘芯片500B,在该芯片上使用对薄膜电阻器材料具有高度选择性的蚀刻过程蚀刻金属-1通孔。尽管该过程相对于先前的通孔1蚀刻示出改善,但是该蚀刻过程仍会穿透或显著蚀刻进入电阻器头部516和电阻器512中。另一种解决方案是使用蚀刻停止层,其覆盖沉积的薄膜电阻器材料以形成电阻器头部516和电阻器517。然而,使用蚀刻停止层需要额外的步骤,以在蚀刻过程完成之后,一旦位于通孔下面,就要去除蚀刻停止层。更重要地,随后的蚀刻停止层的去除不会提供允许期望的电阻器匹配层级的在薄膜电阻器材料上的着陆。
图1示出根据一个实施例的IC芯片100的一部分。IC芯片100含有半导体衬底102,其上已经形成电介质层104。可以是硅晶片或任何其他半导体材料的半导体衬底102包含未具体示出的集成电路器件。作为参考,金属-1层106被示出并且通过触点108与形成在半导体衬底102中的器件(未具体示出)接触。ILD 110覆盖金属-1层106,并且在ILD 110的表面上形成电阻器112。电阻112是HSR,通常具有的电阻在500-2000Ω/cm2的范围内。在一个实施例中,电阻器112的电阻为1000Ω/cm2。在电阻器112的相对端形成两个电阻器头部116。电阻器117已经形成有与形成电阻器头部116的薄膜电阻器材料相同的层,如下所述。电阻器117是LSR,其具有在50-300Ω/cm2范围内的电阻。在一个实施例中,电阻器117的电阻为100Ω/cm2。为了防止在通孔蚀刻期间形成电阻器头部116和电阻器117的薄膜电阻器材料的穿通或消耗,在电阻器头部116和电阻器117上提供一层蚀刻阻滞剂118。ILD 120覆盖电阻器头部116、电阻器117和ILD 114并且通孔122A、122B延伸穿过ILD 120,以接触电阻器头部116、电阻器117和金属-1层106。尽管未具体示出,但金属-2层将形成在ILD 120的表面上。
蚀刻停止材料(如在现有技术中使用的)和蚀刻阻滞材料(如在示例实施例中使用的)之间的差异主要在于层的厚度以及使用这些层的方式。蚀刻停止层被设计为足够厚,以使得蚀刻过程不会穿透蚀刻停止层,而是在蚀刻停止层的一部分完好无损的情况下停止以保护下面的层。由于通孔蚀刻过程不会去除蚀刻停止,因此然后可使用单独的过程来去除通孔底部的蚀刻停止层。相比之下,蚀刻阻滞剂层118被精心设计成一定厚度,该蚀刻阻滞剂层118将减慢通过蚀刻阻滞剂层的蚀刻过程的进行,但是将被蚀刻过程基本上完全去除,同时基本上防止下面的薄膜电阻器材料的消耗。鉴于在晶片制造中使用的特定堆叠的情况下,对蚀刻阻滞剂层118的仔细设计允许蚀刻过程基本同时地轻轻地着陆在电阻器头部116、电阻器117和金属-1层106中的每个上。
图1A-1G描绘形成芯片100的方法中的各个阶段。出于示例实施例的目的,在半导体衬底已经被处理以创建多个器件,电介质层104已经形成,金属-1层106和触点108已经形成并且已经沉积ILD 110之后开始该方法。虽然上述层中的每个对于整个IC芯片都是重要的,但是用于形成这些层的具体过程与所描述的方法无关,并且因此不再详细描述。所描述的方法从沉积将形成电阻器112的薄膜电阻器材料112A的层开始。在一个实施例中,薄膜电阻器材料112A是硅铬(SiCr)。在一个实施例中,薄膜电阻器材料112A为镍铬(NiCr)。可用作薄膜电阻器材料112A的其他材料包括结合有碳和/或氧的SiCr和NiCr的合金。薄膜电阻器材料的通用公式可写为CrVCWSiXNYOZ,其中V、W、X、Y和Z分别在零和四(含)之间。薄膜电阻器材料112A的厚度可在20-100埃的范围内。在一个实施例中,薄膜电阻器材料112A的厚度为32埃。
在已经沉积薄膜电阻器材料112A之后,沉积光刻胶层130并对其进行图案化以仅覆盖薄膜电阻器材料112A中需要薄膜电阻器的那些部分。如芯片100A中所示,晶片准备好进行蚀刻过程以去除未被光刻胶130覆盖的薄膜电阻器材料112A的部分。在蚀刻过程完成之后,已经形成电阻器112并且沉积限定电阻器112的头部厚度的ILD 114。如图1B所示,光刻胶层132已经沉积在芯片100B的ILD 114上并且经图案化以暴露电阻器112的相对端上的头部区域,随后是在电阻器112的表面上停止的蚀刻过程。
在完成对电阻器112的头部区域的蚀刻过程之后,去除光刻胶132并沉积薄膜电阻器材料116A。在已经通过ILD 114蚀刻用于头部区域的开口的那些位置处,薄膜电阻器材料116A将沿触点开口的边缘排布;在ILD 114的表面的所有其他区域中,薄膜电阻器材料116A形成平坦层。如在电阻器112中,薄膜电阻器材料116A可为SiCr、NiCr或这两种材料的结合碳和/或氧的任何合金。薄膜电阻器材料116A的厚度可在250-500埃的范围内。在一个实施例中,薄膜电阻器材料116A的厚度为400埃。然后,覆盖层114沉积蚀刻阻滞剂层118;然后,蚀刻阻滞剂层118遵循薄膜电阻器材料116A的轮廓。在一个实施例中,蚀刻阻滞剂层118包括三层材料夹层,其中,蚀刻阻滞剂的薄层夹在两个电介质层之间。
图1D描绘形成蚀刻阻滞剂层118的三层材料100D的一个实施例。在此实施例中的最低层级上,电介质层119直接覆盖薄膜电阻器材料116A,并防止蚀刻阻滞剂层121与薄膜电阻器材料接触,以防止蚀刻阻滞剂层121和薄膜电阻器材料116A之间的任何不希望反应。电介质层123可为任何适当的电介质诸如氧化物或氮化物,并且可具有0-500埃范围内的厚度。在一个实施例中,电介质层119为厚度为100埃的氧化物。蚀刻阻滞剂层121形成中间的三层,并且可由对蚀刻过程具有选择性的相同性质的氮化物、碳化硅或其他电介质形成。在至少一个实施例中,蚀刻阻滞剂层121对于蚀刻过程具有高度选择性。蚀刻阻滞剂层121的厚度可在50-700埃的范围内。在一个实施例中,蚀刻阻滞剂层121包含400埃的氮化硅。蚀刻阻滞剂层121的确切厚度基于所使用的堆叠和特定的蚀刻过程。三层100D的第三层是用作硬掩模的电介质层123。在一个实施例中,电介质层123包含150埃的氧化物。
图1E描绘由图1C中的虚线140包围的区域并且仅包括一些层,为清楚起见已对其进行了放大。在沉积包括层119、121、123的蚀刻阻滞剂层118之后,沉积光刻胶层134并对其图案化以去除在所需电阻器116之外的薄膜电阻器材料116A的部分。如图1E所示,蚀刻阻滞剂层118的层119、121、123已经被蚀刻,但是下面的层116A尚未被蚀刻。在所描述的实施例中,在用于去除蚀刻阻滞剂层118的蚀刻过程之后,灰化光刻胶134的其余部分并且清洁晶片。进行灰化和清洁以防止某些不希望的装置影响。接着沉积光刻胶层136,该光刻胶层136被图案化并用于蚀刻掉薄膜电阻器材料116A的不需要的部分以形成电阻器头部116和电阻器117,随后去除光刻胶136。尤其地,在图1E中用于蚀刻的掩模和在图1F中用于蚀刻的掩模是相同掩模。
然后,覆盖电阻器117和电阻器头部116沉积ILD 120。所描述的方法中的最终元件是形成通孔120。光刻胶138被沉积在ILD 120上并被图案化以用于蚀刻过程。通常,通孔蚀刻化学过程使用氟化的等离子体,诸如CF4,CXFY,CXHYFZ,其中X=1-4,Y=1-4并且Z=1-4。通孔蚀刻化学过程也可使用氩等离子体或氧等离子体。层间电介质层的厚度可在约4000埃至约1微米之间变化,并且可在层级与层级之间变化。用于ILD层104、110、114的材料可包括电介质,诸如使用等离子体激发化学气相沉积(PECVD)、等离子体激发TEOS沉积(PETEOS)而沉积的二氧化硅,或者可为氟化的或低k电介质。层120的电介质可为氧化物、掺杂的氧化物、低k电介质或氟硅酸盐玻璃(FSG)。通孔的临界尺寸可在0.15微米至1.0微米的范围内。蚀刻阻滞剂的厚度将已经被仔细地校准,使得蚀刻阻滞剂通过蚀刻过程被去除,但是不允许蚀刻过程实质上消耗任何薄膜电阻器材料116A。所描述的过程允许通孔蚀刻过程基本同时地轻轻地着陆在三个不同的层级上。尤其地,将两种类型的电阻器添加到过程流程仅需要三个附加的掩模:提供如图1A所示的光刻胶布局的第一掩模,提供如图1B所示光刻胶布局的第二掩模,和用于如图1E所示光刻胶布局和图1F所示光刻胶布局的第三掩模。(用于针对通孔图案化图1G中的芯片的掩模对于芯片的其他部分是必需的,而不是添加的元件。)此外,当仅将单一类型的TFR添加到过程中时,可使用所述方法;TFR的单一类型可为HSR或LSR。在这种情况下,不需要用于定义第二电阻器所需的掩模,也不需要用于定义下面的电阻器的头部的掩模。
图2描绘与所探索的其他方法相比,所描述的方法的LSR匹配。X轴描绘单独的方法,而Y轴描绘匹配号,其表示芯片上电阻器之间的差(Δ)的累加(∑)。理想情况下,ΣΔ为零。BSL0是起点,并且较差的ΣΔ值约为8000。其他测试过程BSL1、BSL2、BSL3提供的ΣΔ值介于3500和5200之间。所描述的过程(如BSL4所示)是使ΣΔ降至3000以下的唯一过程,达到值约2600。现在可探索电阻器匹配的其他元件的改善,以进一步降低ΣΔ的值。
图3描绘IC芯片300的一部分,其使用所描述的过程但仅包含一种类型的电阻器,该电阻器在此实施例中是LSR。IC芯片300含有半导体衬底302,在其上已经形成器件但未具体示出。ILD 304覆盖半导体衬底302并含有触点308,该触点308延伸穿过ILD 304以将金属-1层306耦合到内置在衬底302中的器件(未具体示出)。第二ILD层310覆盖金属-1层306并且支撑电阻器317。再次可为三层的蚀刻阻滞剂层318覆盖电阻器317的顶表面,但是被通孔322刺穿;还存在其他通孔322以提供与金属-1层的电接触。ILD 320覆盖电阻器317。当仅使用LSR电阻器时,图1A中所示的用于蚀刻电阻器112的掩模和图1B所示用于蚀刻到电阻器112的触点的掩模均不必要,因此提供单一类型的电阻器仅需要单个附加掩模,即用于蚀刻电阻器117的边界。使用蚀刻阻滞剂层318允许蚀刻过程基本同时轻轻着陆在电阻器304和金属-1层106两者上。
图4A-D示出描绘用于改善IC芯片上的TFR匹配的方法400的一系列流程图。该方法针对在芯片上形成两种不同类型的电阻器,尽管指出仅形成一种类型的电阻器时省去的元件。在图4A中,流程图400A以提供(405)其上已经形成半导体器件的半导体衬底开始过程。如上所述,在半导体衬底中和上形成的器件的确切性质与所描述的方法无关。可在任何类型的半导体衬底中形成任何类型的电子器件。该方法以沉积(410)直接覆盖半导体衬底的第一ILD层继续。形成(415)触点,该触点延伸穿过第一ILD层;通常,在单个芯片上形成数百或数千个这样的触点。还形成(420)耦合到触点的金属化层。所使用的特定金属过程或金属可为任何已知或未知的过程。在上述示例中,此层是金属-1层,使得在金属-1层和金属-2层之间形成电阻器;然而,放置在其他金属化层之间的电阻器也将落入示例实施例的范围内。接下来,沉积(425)第二ILD层,其覆盖金属化层。
在图4B中,方法400B以在第二ILD层上沉积(430)第一薄膜电阻器材料而继续。图案化并蚀刻(435)薄膜电阻器材料的此层以形成第一电阻器,即,以限定电阻器的边界。然后覆盖第一电阻器沉积(440)第三ILD层;图案化和蚀刻(445)此第三ILD层以形成用于第一电阻器的头部区域。当对于特定实施例仅需要一种类型的电阻器时,可消除由流程图400B表示的包括元件430-445的方法。
图4C通过在第三ILD层上沉积(450)第二薄膜电阻器材料来继续流程图400C。此第二薄膜电阻器材料将被沉积在第三ILD层的表面上,并且(在提供两种类型的电阻器的情况下)还将被沉积在被蚀刻到第一电阻器的头部区域的表面上。覆盖第二薄膜电阻器材料沉积(455)蚀刻阻滞剂层。在一个实施例中,蚀刻阻滞剂层是三层的硬掩模,其沉积需要三个单独的沉积过程,如图4D所示。在过程400D中,沉积(480)第一电介质,然后沉积(482)蚀刻阻滞剂材料。最后,第二电介质沉积(484)在蚀刻阻滞剂材料上。
再次参考方法400C,在已经沉积蚀刻阻滞剂层之后,图案化和蚀刻(460)蚀刻阻滞剂层和第二薄膜电阻器材料两者,以形成第二电阻器和第一电阻器头部。在图4E中更详细地示出此过程的一个实施例,其中方法400E包括使用第一掩模沉积和图案化(488)覆盖蚀刻阻滞剂层的第一光刻胶层,然后蚀刻(490)该蚀刻阻滞剂层。灰化(492)第一光刻胶层的其余部分,并清洁IC芯片。随后,也使用第一掩模沉积并图案化(494)第二光刻胶层,其覆盖蚀刻阻滞剂层和第二薄膜电阻器材料。蚀刻(496)第二导电材料。随后,将第二光刻胶层的其余部分灰化(498)并清洁IC芯片。再次参考方法400C,覆盖第二电阻器沉积(465)第四ILD层,随后图案化(470)第四ILD层以形成到第一电阻器的头部、第二电阻器和触点的通孔。然后,该方法使用第一蚀刻化学过程同时蚀刻到第一电阻器的头部、第二电阻器和触点的通孔。因为蚀刻阻滞剂层对第一蚀刻化学过程具有选择性并且蚀刻阻滞剂层的厚度是精心选择的,所以通孔蚀刻过程去除蚀刻阻滞剂层的基本上所有暴露的部分并且基本上防止下面的第一薄膜电阻器材料的消耗。这结束所描述的方法,尽管在认为芯片完成之前将对IC芯片执行进一步的处理,诸如沉积金属-2层。
所描述的用于改善IC芯片上的TFR匹配的装置和方法,由于通孔在薄膜电阻器上的着陆的改善而表现出改进的电阻器匹配。所描述的过程提供到TFR或TFR头部更平滑和受控的欧姆触点。蚀刻阻滞剂层,其可为SiN、SiON、SiC或对蚀刻过程提供期望选择性的其他化合物,该蚀刻阻滞剂层覆盖顶部导电层,该顶部导电层限定TFR并且还可限定下面TFR的头部。相对于所使用的特定蚀刻以及蚀刻必须通过其起作用的层来确定蚀刻阻滞剂层的厚度,并且对蚀刻阻滞剂层的厚度进行仔细地调整以实现在电阻器和电阻器头部上的平缓着陆。
在权利要求的范围内,可对所描述的布置进行修改,并且可进行其他附加布置。
Claims (15)
1.一种制造集成电路即IC芯片的方法,所述方法包括:
在第一层间电介质层即第一ILD层上沉积第一薄膜电阻器材料;
在所述第一薄膜电阻器材料上沉积蚀刻阻滞剂层;
图案化并蚀刻所述蚀刻阻滞剂层和所述第一薄膜电阻器材料以形成第一电阻器;
在所述第一电阻器上沉积第二ILD层;和
使用第一蚀刻化学过程图案化和蚀刻所述第二ILD层,以形成穿过所述第二ILD层和所述蚀刻阻滞剂层到所述第一电阻器的通孔,其中,所述蚀刻阻滞剂层对所述第一蚀刻化学过程具有选择性,并且所述蚀刻阻滞剂层的厚度使得所述通孔蚀刻去除所述蚀刻阻滞剂层的基本上所有暴露的部分,并且基本上防止所述下面的第一薄膜电阻器材料的消耗。
2.根据权利要求1所述的方法,其中,图案化和蚀刻所述蚀刻阻滞剂层和所述第一薄膜电阻器材料包括:
使用第一掩模沉积并图案化覆盖所述蚀刻阻滞剂层的第一光刻胶层;
蚀刻所述蚀刻阻滞剂层;
灰化所述第一光刻胶层的其余部分并清洁所述IC芯片;
使用所述第一掩模沉积并图案化覆盖所述蚀刻阻滞剂层和所述第一薄膜电阻器材料的所述第二光刻胶层;
蚀刻所述第一薄膜电阻器材料;和
灰化所述第二光刻胶层的其余部分并清洁所述IC芯片。
3.根据权利要求1所述的方法,其中,沉积所述蚀刻阻滞剂层包括沉积第一电介质,沉积蚀刻阻滞剂材料以及沉积第二电介质。
4.根据权利要求1所述的方法,其中,所述蚀刻阻滞剂材料选自包括氮化硅和碳化硅的组。
5.根据权利要求3所述的方法,其中,所述蚀刻阻滞剂材料的厚度在大约50埃至700埃之间的范围内。
6.根据权利要求1所述的方法,还包括在沉积所述第一薄膜电阻器材料之前:
在覆盖金属化层的第三ILD层上沉积第二薄膜电阻器材料;
图案化并蚀刻所述第二薄膜电阻器材料以形成第二电阻器;
覆盖所述第二电阻器沉积所述第一ILD层;和
图案化和蚀刻所述第一ILD层以形成用于所述第二电阻器的头部区域;
其中:沉积所述第一薄膜电阻器材料包括在所述头部区域中沉积所述第一薄膜电阻器材料;所述蚀刻阻滞剂层和所述第一薄膜电阻材料的所述图案化和蚀刻还形成用于所述第二电阻器的电阻器头部;并且所述第二ILD层的所述图案化和蚀刻还形成穿过所述第一ILD层和所述蚀刻阻滞剂到用于所述第二电阻器的所述头部区域的通孔。
7.根据权利要求6所述的方法,其还包括在沉积所述第二薄膜电阻器材料之前:
提供其上已经形成半导体器件的半导体衬底;
覆盖所述半导体衬底直接沉积第四ILD层;
形成延伸穿过所述第四ILD层的触点;
形成耦合到所述触点的所述金属化层;和
沉积所述第三层间电介质;
其中所述第二ILD层的所述图案化和蚀刻还形成穿过所述第一ILD层、第二ILD层和第三ILD层到所述触点的通孔。
8.根据权利要求1所述的方法,其中,所述第一薄膜电阻器材料和所述第二薄膜电阻器材料各自包括选自包括以下的组的材料:硅铬、镍铬、铬硅氧化物、氮氧化硅和CrVCWSiXNYOZ,其中V、W、X、Y和Z在零和四(含)之间。
9.根据权利要求1所述的方法,其中所述第一蚀刻化学过程选自包括氩、氧、CFY、CXFY和CXHYFZ的组,其中X、Y和Z中的每个等于1和4(含)之间的数字。
10.一种集成电路即IC芯片,包括:
金属化层;
直接覆盖所述金属化层的第一电介质层;
在所述第一电介质层上形成的薄膜电阻器;
覆盖所述薄膜电阻器的蚀刻阻滞剂层;
覆盖所述电阻器的第二电介质层;
第一通孔,其位于所述电阻器的第一端附近并延伸穿过所述第一电介质层和所述蚀刻阻滞剂层并与所述薄膜电阻器接触;
第二通孔,其位于所述电阻器的与所述第一通孔的相对端,并延伸穿过所述第一电介质层和所述蚀刻阻滞剂层并接触所述薄膜电阻器;和
第三通孔,其延伸穿过所述第一电介质层和所述第二电介质层以接触所述金属化层。
11.根据权利要求10所述的IC芯片,其中,所述第一薄膜电阻器材料包括选自包括包括以下的组的材料:硅铬、镍铬、铬硅氧化物、氧氮化硅和CrVCWSiXNYOZ,其中V、W、X、Y和Z介于0和4(含)之间。
12.根据权利要求10所述的IC芯片,其中,所述蚀刻阻滞剂层包括三层:第一电介质、蚀刻阻滞剂材料和第二电介质。
13.根据权利要求10所述的IC芯片,其中,所述蚀刻阻滞剂材料包括选自包括SiN、SiON、SiC的组的材料。
14.根据权利要求10所述的IC芯片,其中,所述蚀刻阻滞剂材料的厚度在大约50埃至700埃之间的范围内。
15.一种制造集成电路即IC芯片的方法,所述方法包括:
提供其上已经形成半导体器件的半导体衬底;
直接覆盖所述半导体衬底沉积第一层间电介质层即第一ILD层;
形成延伸穿过所述第一ILD层的触点;
形成耦合到所述触点的金属化层;和
沉积第二ILD;
在所述第二ILD层上沉积第一薄膜电阻器材料;
图案化并蚀刻所述第一薄膜电阻器材料以形成第一电阻器;
覆盖所述第一电阻器沉积第三ILD层;
图案化并蚀刻所述第三ILD层以形成用于所述第一电阻器的头部区域;
在所述第三ILD层上沉积第二薄膜电阻器材料;
覆盖所述第二薄膜电阻器材料沉积蚀刻阻滞剂层;
图案化并蚀刻所述蚀刻阻滞剂层和所述第二薄膜电阻器材料,以形成第二电阻器和用于所述第一电阻器的电阻器头部;
覆盖所述第二电阻器沉积第四ILD层;
图案化所述第四ILD层,以形成到所述第一电阻器的所述头部、所述第二电阻器和所述触点的通孔;和
使用第一蚀刻化学过程同时蚀刻穿过(在必要时)所述第四ILD、所述第三ILD、所述第二ILD和所述蚀刻阻滞剂层到所述第一电阻器、所述第二电阻器的所述头部以及所述触点的通孔,其中所述蚀刻阻滞剂层对所述通孔蚀刻具有选择性,并且所述蚀刻阻滞剂层的厚度使得所述通孔蚀刻去除所述蚀刻阻滞剂层的基本上所有暴露的部分,并且基本上防止所述下面的第一薄膜电阻器材料和第二薄膜电阻器材料的消耗。
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- 2018-07-11 WO PCT/US2018/041539 patent/WO2019014287A1/en unknown
- 2018-07-11 JP JP2020501462A patent/JP7216463B2/ja active Active
- 2018-07-11 CN CN201880055813.7A patent/CN111033718B/zh active Active
- 2018-07-11 EP EP18831844.8A patent/EP3652779A4/en active Pending
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
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CN1873952A (zh) * | 2005-06-01 | 2006-12-06 | 海力士半导体有限公司 | 制造半导体器件的方法 |
US20100237467A1 (en) * | 2009-03-18 | 2010-09-23 | International Business Machines Corporation | Interconnect Structures, Methods for Fabricating Interconnect Structures, and Design Structures for a Radiofrequency Integrated Circuit |
CN102129965A (zh) * | 2009-11-30 | 2011-07-20 | 英特赛尔美国股份有限公司 | 薄膜电阻器 |
Also Published As
Publication number | Publication date |
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CN111033718B (zh) | 2023-10-13 |
EP3652779A4 (en) | 2020-06-24 |
WO2019014287A1 (en) | 2019-01-17 |
US10211278B2 (en) | 2019-02-19 |
JP2020527859A (ja) | 2020-09-10 |
JP7216463B2 (ja) | 2023-02-01 |
EP3652779A1 (en) | 2020-05-20 |
US20190019858A1 (en) | 2019-01-17 |
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