CN111009537A - 图像传感器芯片级封装 - Google Patents

图像传感器芯片级封装 Download PDF

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Publication number
CN111009537A
CN111009537A CN201910922670.1A CN201910922670A CN111009537A CN 111009537 A CN111009537 A CN 111009537A CN 201910922670 A CN201910922670 A CN 201910922670A CN 111009537 A CN111009537 A CN 111009537A
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Prior art keywords
substrate
top surface
dam
image sensor
cover glass
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CN201910922670.1A
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CN111009537B (zh
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范纯圣
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Omnivision Technologies Inc
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Omnivision Technologies Inc
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Abstract

一种图像传感器芯片级封装包括像素阵列、覆盖像素阵列的防护玻璃、坝和粘合层。像素阵列嵌入在半导体基板的基板顶表面中。半导体基板包括围绕像素阵列的半导体基板的外围区域中的多个导电焊盘。坝至少部分地围绕像素阵列并且位于(i)防护玻璃和半导体基板之间，以及(ii)像素阵列和多个导电焊盘之间的基板顶表面的区域上。粘合层(i)位于防护玻璃和半导体基板之间，(ii)至少部分地围绕坝，并且(iii)被配置为将防护玻璃粘合到半导体基板。

Description

图像传感器芯片级封装
技术领域
本申请涉及图像传感器领域，尤其涉及一种图像传感器芯片级封装。
背景技术
诸如独立数码相机、移动设备、汽车部件和医疗设备之类的消费者设备中的相机模块通常包括透镜组件和图像传感器。由相机模块捕获的图像的质量部分取决于透镜组件与图像传感器的正确对准。
发明内容
本文公开了旨在促进透镜组件与图像传感器的准确且可再现的对准的实施例。
在第一方面，图像传感器芯片级封装包括像素阵列、覆盖像素阵列的防护玻璃、坝(dam)和粘合层。像素阵列嵌入在半导体基板的基板顶表面中。半导体基板包括围绕像素阵列的半导体基板的外围区域中的多个导电焊盘。坝至少部分地围绕像素阵列并且位于(i)防护玻璃和半导体基板之间，以及(ii)像素阵列和多个导电焊盘之间的基板顶表面的区域上。粘合层(i)位于防护玻璃和半导体基板之间，(ii)至少部分地围绕坝，并且(iii)被配置为将防护玻璃粘合到半导体基板。
在第二方面，图像传感器芯片级封装包括绝缘基板、图像传感器、集成电路和第一再分布层。绝缘基板包括穿过其中的第一多个导电通孔。集成电路位于绝缘基板和图像传感器之间，并且在绝缘基板的顶表面上方的第一高度处具有顶表面。第一再分布层(i)将集成电路电连接到第一多个导电通孔中的每个导电通孔，以及(ii)跨越图像传感器和绝缘基板的顶表面之间的距离。该距离超过第一高度。
在第三方面，一种用于制造图像传感器芯片级封装的方法包括利用粘合剂将防护玻璃粘结到半导体基板。粘合剂占据围绕嵌入在半导体基板的基板顶表面中的第一像素阵列的坝间区域。坝间区域至少部分地由以下界定：(i)至少部分地围绕第一像素阵列的坝，(ii)至少部分地围绕与第一像素阵列相邻的相应像素阵列的相邻坝，以及(iii)基板顶表面的坝间表面。
附图说明
图1描绘了包括图像传感器封装的实施例的相机。
图2是图像传感器封装的示意性剖视图，图像传感器封装是图1的图像传感器封装的实施例。
图3是在实施例中图示图2的图像传感器封装的一部分的平面示意图。
图4是第一图像传感器芯片级封装的示意性剖视图，该第一图像传感器芯片级封装是图1的图像传感器封装的实施例。
图5是第二图像传感器芯片级封装的示意性剖视图，该第二图像传感器芯片级封装是图1的图像传感器封装的实施例。
图6是在实施例中的包括多个图像传感器的器件晶圆的俯视图。
图7是在实施例中的在绝缘基板上包括图6的器件晶圆的晶圆组件的剖视图。
图8是在实施例中在从图6的器件晶圆移除材料之后的图7的晶圆组件的剖视图。
图9是在实施例中在添加再分布层之后的图8的晶圆组件的剖视图。
图10是在实施例中在添加围绕每个图像传感器的坝之后的图9的晶圆组件的剖视图。
图11是在实施例中的晶圆组件的剖视图，该晶圆组件是图10的晶圆组件，在相邻的坝之间其上具有粘合层。
图12是图示在实施例中用于制造图4的图像传感器芯片级封装的方法的流程图。
图13是在实施例中其上具有多个间隔元件的防护玻璃组件的剖视图。
图14是在实施例中的封装器件晶圆的剖视图，该封装器件晶圆包括图13的防护玻璃组件和图9的晶圆组件。
图15是第三图像传感器芯片级封装的示意性剖视图，该第三图像传感器芯片级封装是图1的图像传感器封装的实施例。
图16是图示在实施例中用于制造图15的图像传感器芯片级封装的方法的流程图。
具体实施方式
图1描绘了对场景成像的相机190。相机190包括图像传感器芯片级封装100。这里，为了简洁起见，“图像传感器芯片级封装”被简化为“CSP”。
图2是作为CSP 100的实施例的图像传感器芯片级封装200的示意性剖视图。图2的示意图的剖面平行于包括正交方向298X和298Z的平面，所述正交方向298X和298Z各自与方向298Y正交。CSP 200包括半导体基板220、坝240、粘合层250和防护玻璃260。图3是半导体基板220和坝240的平面示意图。在下面的描述中最好一起查看图2和图3。图2的剖视图在例如图3的剖面2中。
半导体基板220具有底表面221、侧表面225、顶表面229和嵌入在其中的像素阵列227。像素阵列227是图像传感器226的一部分。半导体基板220包括在围绕像素阵列227的半导体基板220的外围区域中的多个导电焊盘228。每个导电焊盘228电连接到图像传感器226，并且可以但不必暴露在顶表面229上，顶表面229可以包括导电焊盘228的表面。导电焊盘228可以是图像传感器226的一部分。
坝240至少部分地围绕像素阵列227并且位于防护玻璃260和半导体基板220之间，在像素阵列227和导电焊盘228之间的顶表面229的区域上。防护玻璃260覆盖像素阵列227并且在坝240的顶表面249上方。
CSP 200还可以包括绝缘基板210，绝缘基板210具有底表面211和顶表面219。绝缘基板210包括多个导电焊盘216，每个导电焊盘216例如通过穿过绝缘基板210的多个导电通孔214的相应一个导电通孔电连接到多个底部导电焊盘212中的相应一个底部导电焊盘。导电焊盘216和212可以分别暴露在顶表面219和底表面211上。每个导电焊盘228通过相应的引线接合224电连接到导电焊盘216和底部导电焊盘212中的至少一个。任何一个导电通孔214可以是贯穿通孔、盲通孔或掩埋通孔。
绝缘基板210可以包括选自包括以下材料的组的至少一种材料，这些材料包括但不限于氧化物、焊接掩膜材料、碳化硅、二氧化硅、氮化硅、氧化铝、苯并环丁烯(BCB)、电介质、聚酰亚胺、树脂及其组合。绝缘基板210可以是印刷电路板。坝240可以包括选自包括以下材料的组的至少一种材料，这些材料包括但不限于环氧丙烯酸酯、低聚物、聚丙烯酸甲酯、丙烯酸、硅石(silica)、聚二甲基硅氧烷、环氧树脂、二氧化硅及其任何组合。半导体基板220可以包括选自包括以下材料的组的至少一种材料，这些材料包括但不限于硅、锗及其任何组合。粘合层250可以包括选自包括以下材料的组的至少一种材料，这些材料包括但不限于巯基酯、丙烯酸、环氧、聚酰亚胺和聚二甲基硅氧烷及其任意组合。防护玻璃260包括选自包括以下材料的组的至少一种材料，这些材料包括但不限于铝硅酸盐玻璃、无碱玻璃、硼硅酸盐玻璃、石英玻璃及其组合。
粘合层250将防护玻璃260粘结到半导体基板220，并且在适用时，粘结到绝缘基板210。粘合层250还保护引线接合224。粘合层250可以由环氧树脂形成，并且具有顶表面259。粘合层250的缺点在于它在固化时收缩，使得顶表面259在表面229和/或表面219上方可能具有不均匀的高度。CSP 200的平面顶表面便于CSP 200与透镜组件的组装，透镜组件例如搁置在顶表面259上。为了获得最佳图像质量，透镜组件必须与CSP 200对准，使得其光轴正交于像素阵列227的平面。当顶表面259具有不均匀的高度时，这种对准受到阻碍。
图4是作为CSP 100的实施例的图像传感器芯片级封装400的示意性剖视图。CSP400弥补了CSP 200的上述问题。图4的示意图的剖面平面与包括正交方向298X和298Z的平面平行。CSP 400包括半导体基板220、坝240、粘合层450和防护玻璃460。用于粘合层450和防护玻璃460的候选材料分别与用于粘合层250和防护玻璃260的候选材料相同。CSP还可以包括在半导体基板220下方的绝缘基板210。
半导体基板220、坝240和防护玻璃460可以在图像传感器226上方形成腔体463。腔体可以由半导体基板220的顶表面229、坝240的内侧表面245和防护玻璃460的防护玻璃底表面461形成。腔体可以具有对应于防护玻璃底表面461和顶表面229之间的最小距离462的最小高度。最小距离462可以大于或等于坝240的高度。例如，最小距离462可以等于坝240的高度与坝240和防护玻璃460之间的任何粘合剂(例如，粘合层450)的厚度之和。最小距离462在例如30微米到50微米之间。
粘合层450(i)位于防护玻璃460和半导体基板220之间，(ii)至少部分地围绕坝240，以及(iii)被配置为将防护玻璃460粘合到半导体基板220。粘合层450可以跨越防护玻璃底表面461和顶表面229之间。当CSP 400包括绝缘基板210时，粘合层450可以跨越绝缘基板210的顶表面219和防护玻璃底表面461之间。
CSP 400具有封装顶表面409。封装顶表面409包括位于像素阵列227、坝240和粘合层450上方的相应区域。防护玻璃460具有防护玻璃底表面461和顶表面469。封装顶表面409包括顶表面469的至少一部分。封装顶表面409具有相对于防护玻璃底表面461的在3微米内均匀的高度408。这种均匀性有利于上述透镜组件与像素阵列227的对准。封装顶表面409可以是图像传感器芯片级封装的最顶层表面。
CSP 400可以在防护玻璃顶表面469上包括不透明掩膜470。不透明掩膜470位于坝240和粘合层450中的至少一个上方。例如，不透明掩膜470包括区域474和区域475中的至少一个，区域474和区域475分别直接在坝240和粘合层450上方。不透明掩膜470具有顶表面479。当CSP 400包括不透明掩膜470时，封装顶表面409包括顶表面479的一部分。
构成粘合层450的材料可以与构成不透明掩膜470的材料不同。不透明掩膜470可以包括选自包括以下材料的组的至少一种材料，这些材料包括但不限于钨、钼、光致抗蚀剂材料及其任何组合。不透明掩膜470具有厚度478，其可以小于3微米。
CSP 400可以包括再分发层425。再分布层425包括多个导电段，每个导电段电连接到相应的导电焊盘228并且从基板顶表面229朝底表面221延伸。当CSP 400包括绝缘基板210时，再分布层425的每个导电段可以将相应的导电焊盘228电连接到相应的导电焊盘216。
CSP 400可以包括在侧表面225和再分布层425之间的隔离层424。隔离层424的部分可以在顶表面229和再分布层425之间。隔离层424可以包括选自包括以下材料的组的至少一种材料，这些材料包括但不限于聚酰亚胺、碳化硅、氧化物及其任何组合。隔离层424例如经由等离子体增强化学气相沉积形成。
图5是图像传感器芯片级封装500的示意性剖视图，图像传感器芯片级封装500是包括集成电路535的CSP 100的实施例。CSP 500弥补了CSP 200的上述问题。图5的示意图的剖面平面与包括正交方向298X和298Z的平面平行。
CSP 500包括绝缘基板210、图像传感器226、集成电路530和再分布层535。集成电路530位于绝缘基板210和图像传感器226之间，并且在绝缘基板的顶表面上方的高度539H处具有顶表面539。除了多个导电通孔214之外，绝缘基板210可以包括多个导电通孔514。任何一个导电通孔514可以是贯穿通孔，盲通孔或掩埋通孔。集成电路530可以包括数字信号处理器，诸如图像信号处理器。
再分布层535将集成电路530电连接到绝缘基板210的多个导电通孔514中的每一个。例如，集成电路530可以包括多个导电焊盘538，每个导电焊盘通过再分布层535电连接到相应的导电通孔214。再分布层535可以将图像传感器226电连接到集成电路530，例如，当集成电路530包括图像信号处理器时。
再分布层535跨越图像传感器和绝缘基板的顶表面539之间的距离535H。距离535H超过高度539H表面539和221之间的间隙厚度537。间隙厚度537在例如5微米和25微米之间。距离535H可以对应于绝缘基板210的顶表面219和半导体基板220的底表面221之间的再分布层535的厚度。
CSP 500可以包括再分布层525，再分布层525将图像传感器226电连接到多个导电通孔214中的每一个。再分布层525包括多个导电段，每个导电段电连接到相应的导电焊盘228并且从基板顶表面229朝绝缘基板210的顶表面219延伸。当CSP 500包括绝缘基板210时，再分布层525的每个导电段可以将相应的导电焊盘228电连接到相应的导电焊盘216。再分布层535的至少一部分可以在绝缘基板210和再分布层525之间。
CSP 500可以包括再分布层525和半导体基板220之间的隔离层524。CSP 500可以包括再分布层535和集成电路530之间的隔离层534。隔离层524和534类似于隔离层424。隔离层534的至少一部分可以在集成电路530的侧表面533上。
图6是在平行于x-y平面—即，由方向298X和298Y张成的平面—的平面中的器件晶圆600的俯视图。器件晶圆600具有直径614，该直径可以在一百毫米到五百毫米之间，例如，三百毫米或四百五十毫米。器件晶圆600包括多个晶圆接合(wafer-bound)图像传感器626，并且可以被单体化，使得每个晶圆接合图像传感器626成为相应的图像传感器226。为了清楚说明，图6将器件晶圆600描绘为包括少于五十个图像传感器226。器件晶圆600可以包括比图6中描绘的更多或更少的图像传感器226。
器件晶圆600包括多个器件间区域625。每个器件间区域625位于至少一对相邻的晶圆接合图像传感器626之间。例如，器件晶圆600包括第一列611的图像传感器626、第二列612的图像传感器626，以及它们之间的器件间区域625。
图7是晶圆组件700的剖视图，晶圆组件700包括在绝缘基板710上的器件晶圆600。图7的剖视图在例如图6的剖面平面7中。器件晶圆600包括顶表面629；半导体基板220的顶表面229对应于顶表面629的区域。可以将基板710单体化以产生多个绝缘基板210。因此，基板710包括多个导电焊盘216。绝缘基板710包括顶表面719；绝缘基板210的顶表面219对应于顶表面719的区域。
器件晶圆600包括导电焊盘228，每个导电焊盘228电连接到晶圆接合图像传感器626。每个导电焊盘228可以暴露在顶表面629上，顶表面629可以包括导电焊盘228的表面。绝缘基板710包括多个导电焊盘216。导电焊盘216可以暴露在顶表面719上。
顶表面719包括在相邻导电焊盘216之间的焊盘间区域716。焊盘间区域716可以对应于顶部表面719的直接位于器件间区域625下方的区域。焊盘间区域716可以包括顶表面719的部分但不是全部，并且不包括例如一个或多个导电焊盘216的任何表面。
图8是晶圆组件800的剖视图。晶圆组件800可以通过去除对应于器件间区域625的器件晶圆600的材料而暴露焊盘间区域716来产生。这种材料去除可以用于单体化器件晶圆600以产生多个半导体基板220。晶圆组件800包括沟槽820，沟槽820部分地由相邻半导体基板220的相对侧表面225和对应于焊盘间区域716的顶表面719界定。沟槽820具有由相对侧表面225确定的宽度821，其可以在方向298Z上变化。
图9是晶圆组件900的剖视图，晶圆组件900是晶圆组件800的修改，其中每个半导体基板220在其上包括相应的再分布层425。在晶圆组件900中，每个半导体基板220还可以包括相应的隔离层，使得隔离层424位于侧表面225和再分布层425之间。如在图4的CSP400中那样，隔离层424的一部分可以在顶表面229和再分布层425之间。
图10是晶圆组件1000的剖视图，晶圆组件1000是晶圆组件900另外加上对于每个半导体基板220的至少部分地围绕每个像素阵列227的坝240。为了清楚起见，图10中所示的晶圆组件1000的两个像素阵列227由附图标记227(1)和227(2)表示，并且围绕像素阵列227(1,2)的坝240由相应的附图标记240(1,2)表示。晶圆组件1000包括至少部分地由坝240(1)、坝240(2)和焊盘间区域716界定的坝间区域1045。
图11是晶圆组件1100的剖视图，晶圆组件1100是在坝间区域1045中具有粘合层1150的晶圆组件1000。用于粘合层1150的候选材料与用于粘合层250的材料相同。粘合层1150具有顶表面1159，其至少一部分可以在坝240的顶表面249上方延伸。
图12是图示用于制造图像传感器芯片级封装的方法1200的流程图。方法1200包括步骤1240，并且可以包括步骤1210、1220和1230中的至少一个。
步骤1230包括用粘合剂将防护玻璃粘结到半导体基板。粘合剂占据围绕嵌入在半导体基板的基板顶表面中的第一像素阵列的坝间区域。坝间区域至少部分地由以下限定：(i)至少部分地围绕第一像素阵列的坝，(ii)至少部分地围绕与第一像素阵列相邻的相应像素阵列的相邻坝，以及(iii)基板顶表面的坝间表面。在步骤1230的示例中，防护玻璃晶圆经由粘合层1150粘结到晶圆组件1100。
当半导体基板附着到其下的绝缘基板时以及当坝间区域包括电连接到第一像素阵列的导电元件时，方法1200可以包括步骤1210。步骤1210包括暴露位于坝间表面下方的绝缘基板的基板区域。在步骤1210的示例中，暴露绝缘基板710的焊盘间区域716以产生晶圆组件800。
步骤1210可以包括步骤1212、1214和1216中的至少一个。步骤1212包括形成穿过坝间区域的沟槽，半导体基板的两个相对侧壁限定沟槽的宽度。在步骤1212的示例中，晶圆组件700(图7)的沟槽820穿过坝间区域716形成，以产生晶圆组件800(图8)。
步骤1214包括用隔离层涂覆两个相对侧壁中的每一个。在步骤1214的示例中，晶圆组件800的侧表面225(图8)涂覆有隔离层424，以产生晶圆组件900(图9)。步骤1216包括在隔离层上设置导电元件。在示例步骤1216中，再分布层425设置在晶圆组件900的隔离层424上(图9)。
当坝和相邻坝各自具有高于基板顶表面的坝高度时，方法1200可以包括步骤1220。步骤1220包括用粘合剂填充坝间区域，使得基板顶表面上方的粘合剂的最大高度超过坝高度。在步骤1220中，可以经由光刻、冲压、纳米压印工艺或其任何组合来施加粘合剂。在步骤1220的示例中，焊盘间区域716填充有粘合层1150(图11)。步骤1220可以包括步骤1222，该步骤包括用粘合剂覆盖基板区域和导电元件。在步骤1222的示例中，焊盘间区域716和再分布层425被粘合层1150覆盖(图11)。
图13是在平行于x-y平面的平面中的防护玻璃组件1300的剖视图。防护玻璃组件1300包括防护玻璃晶圆1360和附着到其的多个间隔元件1380。防护玻璃晶圆1360是上述方法1200，步骤1230的防护玻璃晶圆的示例。防护玻璃晶圆1360具有直径1314，该直径可以等于图6的器件晶圆600的直径614。防护玻璃组件1300可以与器件晶圆600对准，使得每个间隔元件1380与器件晶圆600的相应器件间区域625对准。防护玻璃晶圆1360具有底表面1361。图13图示了切割平面1302，每个切割平面1302可以与底表面1361正交。切割平面1302可以与间隔元件1380相交。
间隔元件1380可以是形成网格图案的单片间隔元件的部件。间隔元件1380可以包括选自包括以下材料的组的至少一种材料，这些材料包括但不限于钨、钼、光致抗蚀剂材料及其任何组合。
图14是封装器件晶圆1400的示意性剖视图。图14的剖视图在例如图13的剖平面14中。封装器件晶圆1400包括经由粘合层1450附着到晶圆组件900的防护玻璃组件1300。用于粘合层1450的候选材料与用于图2的粘合层250的候选材料相同。半导体基板220、间隔元件1380、防护玻璃晶圆1360和粘合剂1450可以形成图像传感器226上方的腔体1463。腔体可以由半导体基板220的顶表面229、粘合层1450的侧表面1455、间隔元件1380的侧表面1355和防护玻璃晶圆1360的底表面1361界定。腔体可以具有对应于底表面1361和顶表面229之间的最小距离1362的最小高度。最小距离1362可以等于图4的最小距离462。
图15是CSP 1500的示意性剖视图，CSP 1500可以从沿着图13的切割平面1302单体化封装器件晶圆1400产生。CSP 1500包括绝缘基板210、半导体基板220、粘合层1550、间隔层1580和防护玻璃1560。粘合层1550、间隔层1580和防护玻璃1560分别对应于封装器件晶圆1400的粘合层1450、间隔元件1380和防护玻璃晶圆1360。
图16是图示用于制造图像传感器芯片级封装的方法1600的流程图。方法1600包括步骤1610、1620和1630中的至少一个。
步骤1630包括用粘合剂将防护玻璃粘结到器件晶圆。防护玻璃包括附着到其的多个间隔元件。器件晶圆包括多个图像传感器和多个器件间区域。相应体积的粘合剂将多个间隔元件中的每个间隔元件粘结到多个器件间区域中的相应一个器件间区域。每个器件间区域包括多个导电元件中电连接到器件晶圆的多个图像传感器中的一个图像传感器的相应一个导电元件。器件间区域中的每一个可以在一对相邻的图像传感器之间。在步骤1620的示例中，防护玻璃晶圆1360被粘结到器件晶圆600以产生封装器件晶圆1400。
步骤1610可以在步骤1630之前执行，并且包括在防护玻璃上形成多个间隔元件。在步骤1610的示例中，间隔元件1380形成在防护玻璃晶圆1360上或附着到防护玻璃晶圆1360。
当器件晶圆被安装在包括位于多个器件间区域中的相应一个内的多个基板区域的绝缘基板上时，可以应用步骤1620。步骤1620包括用粘合剂覆盖多个导电元件中的每个导电元件和多个基板区域中的每个基板区域。在步骤1620的示例中，晶圆组件900的再分布层425和基板区域716用粘合层1450覆盖。
特征的组合
在不脱离本发明的范围的情况下，可以以各种方式组合上述特征以及下面要求保护的特征。以下列举的示例说明了一些可能的非限制性组合：
(A1)一种图像传感器芯片级封装(CSP)包括像素阵列、覆盖像素阵列的防护玻璃、坝和粘合层。像素阵列嵌入在半导体基板的基板顶表面中。半导体基板包括在围绕像素阵列的半导体基板的外围区域中的多个导电焊盘。坝至少部分地围绕像素阵列并且位于(i)防护玻璃和半导体基板之间，以及(ii)像素阵列和多个导电焊盘之间的基板顶表面的区域上。粘合层(i)位于防护玻璃和半导体基板之间，(ii)至少部分地围绕坝，以及(iii)被配置为将防护玻璃粘合到半导体基板。
(A2)CSP(A1)可以具有封装顶表面，封装顶表面(i)位于像素阵列、坝和粘合层中的每一个上方，(ii)包括防护玻璃的防护玻璃顶表面的至少一部分，以及(iii)相对于防护玻璃的与防护玻璃顶表面相对的底表面具有在3微米内的均匀的高度。
(A3)在CSP(A2)中，封装顶表面可以是图像传感器芯片级封装的最顶部表面。
(A4)任何CSP(A2)和(A3)还可以包括在防护玻璃顶表面上并且在坝和粘合层中的至少一个上方的不透明掩膜，封装顶表面包括不透明掩膜的顶表面的一部分。
(A5)在任何CSP(A4)中，不透明掩膜和粘合层可以由不同的材料形成。
(A6)在任何CSP(A1)-(A5)中，粘合层可以跨越基板顶表面和防护玻璃的底表面之间。
(A7)任何CSP(A1)-(A6)还可以包括再分布层，所述再分布层包括多个导电段，每个导电段电连接到多个导电焊盘中的相应一个并且从基板顶表面朝半导体基板的与基板顶表面相对的基板底表面延伸。
(A8)任何CSP(A7)还可以包括基板侧表面和再分布层之间的隔离层，基板侧表面位于基板顶表面和与其相对的基板底表面之间。
(A9)任何CSP(A1)-(A8)还可以包括在半导体基板的与基板顶表面相对的基板底表面上的隔离层。隔离层包括穿过其中的多个导电通孔，每个导电通孔电连接到像素阵列。
(A10)在任何CSP(A1)-(A9)中，粘合层可以包括巯基酯、丙烯酸、环氧、聚酰亚胺和聚二甲基硅氧烷中的至少一种。
(A11)在任何CSP(A1)-(A10)中，坝可以包括环氧丙烯酸酯、低聚物、聚丙烯酸甲酯、硅石、聚二甲基硅氧烷、环氧树脂和二氧化硅中的至少一种。
(B1)一种图像传感器芯片级封装(CSP)包括绝缘基板、图像传感器、集成电路和第一再分布层。绝缘基板包括穿过其中的第一多个导电通孔。集成电路位于绝缘基板和图像传感器之间，并且在绝缘基板的顶表面上方的第一高度处具有顶表面。第一再分布层(i)将集成电路电连接到第一多个导电通孔中的每个导电通孔，以及(ii)跨越图像传感器和绝缘基板的顶表面之间的距离；该距离超过第一高度。
(B2)任何CSP(B1)还可以包括第二再分布层，该第二再分布层将图像传感器电连接到穿过绝缘基板的第二多个导电通孔中的每个导电通孔。
(C1)一种用于制造图像传感器芯片级封装的方法包括用粘合剂将防护玻璃粘结到半导体基板。粘合剂占据围绕嵌入在半导体基板的基板顶表面中的第一像素阵列的坝间区域。坝间区域至少部分地由以下界定：(i)至少部分地围绕第一像素阵列的坝，(ii)至少部分地围绕与第一像素阵列相邻的相应像素阵列的相邻坝，以及(iii)基板顶表面的坝间表面。
(C2)任何方法(C1)，其中坝和相邻坝各自具有在基板顶表面上方的坝高度，可以包括用粘合剂填充坝间区域，使得基板顶表面上方的粘合剂的最大高度超过坝高度。
(C3)任何方法(C2)，其中半导体基板附着到其下方的绝缘基板，坝间区域包括电连接到第一像素阵列的导电元件，还可以包括(i)暴露位于坝间表面下方的绝缘基板的基板区域；并且，在填充的步骤中，(ii)用粘合剂覆盖基板区域和导电元件。
(C4)在任何方法(C2)中，暴露基板区域的步骤可以包括：(i)形成穿过坝间区域的沟槽，半导体基板的两个相对侧壁限定沟槽的宽度；(ii)用隔离层涂覆两个相对侧壁中的每个侧壁；以及(iii)将导电元件设置在隔离层上。
(D1)一种用于制造图像传感器芯片级封装的方法包括用粘合剂将防护玻璃粘结到器件晶圆。防护玻璃包括附着到其的多个间隔元件。器件晶圆包括多个图像传感器和多个器件间区域。相应体积的粘合剂将多个间隔元件中的每个间隔元件粘结到多个器件间区域中的相应一个器件间区域。每个器件间区域包括多个导电元件中电连接到器件晶圆的多个图像传感器中的一个图像传感器的相应一个导电元件。多个器件间区域中的每个器件间区域可以位于多个图像传感器中的一对相邻图像传感器之间。
(D2)任何方法(D1)还可以包括：在粘结的步骤之前，在防护玻璃上形成多个间隔元件。
(D3)任何方法(D1)和(D2)，其中器件晶圆安装在包括位于多个器件间区域中的相应一个器件间区域内的多个基板区域的绝缘基板上，还可以包括：在粘结的步骤之前，用粘合剂覆盖多个导电元件中的每个导电元件和多个基板区域中的每个基板区域。
在不脱离本发明的范围的情况下，可以在上述方法和系统中进行改变。因此应当注意的是，包含在上面的描述中或者在附图中示出的内容应该被解释为说明性的而不是限制意义的。在本文中，除非另有说明，否则形容词“示例性”意味着用作示例、实例或图示。以下权利要求旨在涵盖本文描述的所有一般和具体特征，以及在语言方面可以被说成介于其间的本方法和系统的范围的所有陈述。

Claims (17)

1.一种图像传感器芯片级封装，包括：
像素阵列，嵌入在半导体基板的基板顶表面中，所述半导体基板包括围绕所述像素阵列的所述半导体基板的外围区域中的多个导电焊盘；
防护玻璃，覆盖所述像素阵列；
坝，至少部分地围绕所述像素阵列并且位于(i)所述防护玻璃和所述半导体基板之间，以及(ii)所述像素阵列和所述多个导电焊盘之间的基板顶表面的区域上；以及
粘合层，(i)位于所述防护玻璃和所述半导体基板之间，(ii)至少部分地围绕所述坝，以及(iii)被配置为将所述防护玻璃粘合到所述半导体基板。
2.根据权利要求1所述的图像传感器芯片级封装，具有封装顶表面，所述封装顶表面(i)位于所述像素阵列、所述坝和所述粘合层中的每一个上方，(ii)包括所述防护玻璃的防护玻璃顶表面的至少一部分，并且(iii)相对于所述防护玻璃的与所述防护玻璃顶表面相对的底表面具有在3微米内的均匀的高度。
3.根据权利要求2所述的图像传感器芯片级封装，所述封装顶表面是所述图像传感器芯片级封装的最顶部表面。
4.根据权利要求2所述的图像传感器芯片级封装，还包括在所述防护玻璃顶表面上并且在所述坝和所述粘合层中的至少一个上方的不透明掩膜，所述封装顶表面包括所述不透明掩膜的顶表面的一部分。
5.根据权利要求4所述的图像传感器芯片级封装，所述不透明掩膜和所述粘合层由不同的材料形成。
6.根据权利要求1所述的图像传感器芯片级封装，所述粘合层跨越所述基板顶表面和所述防护玻璃的所述底表面之间。
7.根据权利要求1所述的图像传感器芯片级封装，还包括：
再分布层，包括多个导电段，每个导电段电连接到所述多个导电焊盘中的相应一个导电焊盘，并且从所述基板顶表面朝所述半导体基板的与所述基板顶表面相对的基板底表面延伸。
8.根据权利要求7所述的图像传感器芯片级封装，还包括基板侧表面和所述再分布层之间的隔离层，所述基板侧表面位于所述基板顶表面和与其相对的基板底表面之间。
9.根据权利要求1所述的图像传感器芯片级封装，还包括：
隔离层，在所述半导体基板的与所述基板顶表面相对的基板底表面上，并且包括穿过其中的多个导电通孔，每个导电通孔电连接到所述像素阵列。
10.根据权利要求1所述的图像传感器芯片级封装，所述粘合层包括巯基酯、丙烯酸、环氧、聚酰亚胺和聚二甲基硅氧烷中的至少一种。
11.根据权利要求1所述的图像传感器芯片级封装，所述坝包括环氧丙烯酸酯、低聚物、聚丙烯酸甲酯、硅石、聚二甲基硅氧烷、环氧树脂和二氧化硅中的至少一种。
12.一种图像传感器芯片级封装，包括：
绝缘基板，包括穿过其中的第一多个导电通孔；
图像传感器；
集成电路，在所述绝缘基板和所述图像传感器之间并且在所述绝缘基板的顶表面上方的第一高度处具有顶表面；以及
第一再分布层，(i)将所述集成电路电连接到所述第一多个导电通孔中的每个导电通孔，以及(ii)跨越所述图像传感器和所述绝缘基板的所述顶表面之间的距离，所述距离超过所述第一高度。
13.根据权利要求12所述的图像传感器芯片级封装，还包括第二再分布层，所述第二再分布层将所述图像传感器电连接到穿过所述绝缘基板的第二多个导电通孔中的每个导电通孔。
14.一种用于制作图像传感器芯片级封装的方法，包括：
用粘合剂将防护玻璃粘结到半导体基板，所述粘合剂占据围绕嵌入在所述半导体基板的基板顶表面中的第一像素阵列的坝间区域，所述坝间区域至少部分地通过以下界定：(i)至少部分地围绕所述第一像素阵列的坝，(ii)至少部分地围绕与所述第一像素阵列相邻的相应像素阵列的相邻坝，以及(iii)所述基板顶表面的坝间表面。
15.根据权利要求14所述的方法，所述坝和所述相邻坝各自具有基板顶表面上方的坝高度，并且所述方法还包括：
用所述粘合剂填充所述坝间区域，使得所述基板顶表面上方的粘合剂的最大高度超过坝高度。
16.根据权利要求15所述的方法，所述半导体基板附着到其下方的绝缘基板，所述坝间区域包括与所述第一像素阵列电连接的导电元件，所述方法还包括：
暴露位于所述坝间表面下方的所述绝缘基板的基板区域；并且在填充的步骤中，
用所述粘合剂覆盖所述基板区域和所述导电元件。
17.根据权利要求16所述的方法，暴露所述基板区域的步骤包括：
形成穿过所述坝间区域的沟槽，所述半导体基板的两个相对侧壁限定所述沟槽的宽度；
用隔离层涂覆所述两个相对侧壁中的每个侧壁；以及
将所述导电元件设置在所述隔离层上。
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