CN110957365A - 半导体结构和半导体电路 - Google Patents

半导体结构和半导体电路 Download PDF

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Publication number
CN110957365A
CN110957365A CN201910909570.5A CN201910909570A CN110957365A CN 110957365 A CN110957365 A CN 110957365A CN 201910909570 A CN201910909570 A CN 201910909570A CN 110957365 A CN110957365 A CN 110957365A
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layer
fin
polarity
type
sidewall surface
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CN110957365B (zh
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麦特西亚斯·帕斯拉克
荷尔本·朵尔伯斯
彼得·拉姆瓦尔
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

本发明描述了半导体结构,该半导体结构包括来自未掺杂半导体材料的衬底和设置在衬底上的鳍。该鳍包括非极性顶面和两个相对的第一和第二极性侧壁表面。该半导体结构还包括位于第一极性侧壁表面上的极化层、位于极化层上的掺杂半导体层、位于掺杂半导体层和第二极性侧壁表面上的介电层,以及位于介电层和第一极性侧壁表面上的栅电极层。本发明的实施例还涉及半导体电路。

Description

半导体结构和半导体电路
技术领域
本申请的实施例涉及半导体结构和半导体电路。
背景技术
金属氧化物半导体场效应晶体管(MOSFET)已按比例缩小成为提高硅互补金属氧化物半导体(CMOS)技术性能的首选设计选择。随着器件按比例缩小产生更小的晶体管,产生的更大器件密度已经产生了100W/cm2的量级的功率密度。进一步按比例缩小还将增加功率密度并且导致晶体管损坏。
发明内容
本申请的一些实施例提供了一种半导体结构,包括:鳍,包括非极性顶面和两个相对的第一极性侧壁表面和第二极性侧壁表面;第一极性层,位于所述第一极性侧壁表面上;第二极性层,位于所述第二极性侧壁表面上;以及栅电极层,位于所述第一极性层和所述第二极性层上。
本申请的另一实施例提供了一种半导体结构,包括:衬底,包括未掺杂半导体材料;鳍,位于所述衬底上,并具有非极性顶面和两个相对的第一极性侧壁表面和第二极性侧壁表面,其中,所述鳍包括所述未掺杂半导体材料;极化层,位于所述第一极性侧壁表面上;掺杂半导体层,位于所述极化层上;介电层,位于所述掺杂半导体层和所述第二极性侧壁表面上;以及栅电极层,位于所述介电层和所述第一极性侧壁表面上。
本申请的又一实施例提供了一种半导体电路,包括:鳍式场效应晶体管(finFET)反相器结构,包括:第一鳍,具有两个相对的第一极性侧壁表面和第二极性侧壁表面;第一介电层,位于所述第一鳍的所述第一极性侧壁表面上;第二介电层,位于所述第一鳍的所述第二极性侧壁表面上;以及栅电极材料,所述栅电极材料位于所述第一介电层和所述第二介电层上;以及遂穿鳍式场效应晶体管(TFET),包括:第二鳍,具有两个相对的第一极性侧壁表面和第二极性侧壁表面;极化层,位于所述第二鳍的所述第一极性侧壁表面上;掺杂半导体层,位于所述极化层上;第三介电层,位于所述掺杂半导体层和所述第二鳍的所述第二极性侧壁表面上;以及所述栅电极材料,位于所述第三介电层上,所述第三介电层位于所述第二鳍的所述第一极性侧壁表面上。
附图说明
当结合附图进行阅读时,从以下详细描述可最佳理解本发明的各个方面。应该注意,根据工业中的标准实践,各个部件未按比例绘制。实际上,为了清楚的讨论,各个部件的尺寸可以任意地增大或减小。
图1是根据一些实施例的用于在氮化镓鳍上形成n型和p型场效应晶体管的方法的流程图。
图2A是根据一些实施例的氮化镓衬底上的氮化镓鳍的等轴视图。
图2B是根据一些实施例的氮化镓衬底上的氮化镓鳍沿x轴的截面图。
图3A是根据一些实施例的氮化镓衬底上的氮化镓鳍沿x轴的截面图,其中,氮化镓鳍上形成有介电层。
图3B是根据一些实施例的在偏置条件下形成在单个氮化镓鳍上的整个反相器结构的模拟能带图与相应的氮化镓鳍的特定电阻率图。
图4是根据一些实施例的氮化镓衬底上的氮化镓鳍沿x轴的截面图,其中,氮化镓鳍上形成有栅电极层。
图5是根据一些实施例的氮化镓衬底上的氮化镓鳍与图案化的栅电极层的沿y轴截面图。
图6是根据一些实施例的氮化镓衬底上的氮化镓鳍沿y轴的截面图,其中,间隔件形成在图案化的栅电极层的侧壁上。
图7是根据一些实施例的氮化镓衬底上的氮化镓鳍沿x轴的截面图,其中,间隔件位于介电层上。
图8是根据一些实施例的其上具有介电层的部分形成的场效应晶体管结构沿y轴的截面图。
图9是根据一些实施例的在具有用于n型场效应晶体管的接触开口的单个鳍上的部分形成的n型和p型场效应晶体管的顶视图。
图10是根据一些实施例的在单个鳍上的部分形成的n型和p型晶体管的顶视图,其中,在n型场效应晶体管的接触开口中具有n掺杂氮化镓层。
图11是根据一些实施例的单个鳍上的部分形成的n型和p型晶体管的顶视图,其中,源极/漏极接触电极用于n型场效应晶体管。
图12是根据一些实施例的反相器配置中的n型晶体管和p型晶体管的顶视图。
图13是根据一些实施例的用于形成n型和p型遂穿场效应晶体管的方法的流程图。
图14是根据一些实施例的在沉积氮化铟极化层之后氮化镓层上的氮化镓鳍沿x轴的截面图。
图15是根据一些实施例的在沉积n掺杂氮化镓层之后氮化镓层上的氮化镓鳍沿x轴的截面图。
图16是根据一些实施例的n型遂穿场效应晶体管沿x轴的截面图。
图17是根据一些实施例的p型遂穿场效应晶体管沿x轴的截面图。
图18是根据一些实施例的具有间隔件的n型遂穿场效应晶体管的顶视图。
图19是根据一些实施例的具有接触开口的n型遂穿场效应晶体管的顶视图。
图20是根据一些实施例的具有接触件的n型遂穿场效应晶体管的顶视图。
图21和图22是根据一些实施例的在导通状态期间的相应的n型和p型TFET结构的模拟能带图。
具体实施方式
以下公开内容提供了许多用于实现本所提供主题的不同特征的不同实施例或实例。下面描述了组件和布置的具体实例以简化本发明。当然,这些仅仅是实例,而不旨在限制本发明。例如,以下描述中,在第二部件上方或者上形成第一部件可以包括第一部件和第二部件直接接触形成的实施例,并且也可以包括在第一部件和第二部件之间可以形成额外的部件,从而使得第一部件和第二部件可以不直接接触的实施例。
而且,为便于描述,在此可以使用诸如“在…之下”、“在…下方”、“下部”、“在…之上”、“上部”等空间相对术语,以描述如图所示的一个元件或部件与另一个(或另一些)原件或部件的关系。除了图中所示的方位外,空间相对术语旨在包括器件在使用或操作中的不同方位。装置可以以其他方式定向(旋转90度或在其他方位上),而本文使用的空间相对描述符可以同样地作出相应的解释。
本文使用的术语“标称”是指在产品或工艺的设计阶段期间设定的组件或工艺操作的特征或参数的期望值或目标值,以及高于/或低于期望值的值和范围。值的范围通常由于制造工艺中的微小变化或公差引起。
本文使用的术语“基本上”表示可以基于与主题半导体器件相关联的特定技术节点而变化的给定量的值。在一些实施例中,基于特定技术节点,术语“基本上”可表示在例如目标(或预期)值的±5%内变化的给定量的值。
本文使用的术语“约”表示可以基于与主题半导体器件相关联的特定技术节点而变化的给定量的值。在一些实施例中,基于特定技术节点,术语“约”可表示在例如值的10-30%(例如,值的±10%、±20%或±30%)内变化的给定量的值。
本文使用的术语“垂直”意味着标称垂直于衬底的表面。
在每单位面积具有高密度晶体管的移动应用中,发热和散热问题可能具有挑战性。一种控制具有大器件密度的电路中的发热的方法是减少金属氧化物场效应晶体管(MOSFET)消耗的功率。由于MOSFET的驱动电压表现出二次功率依赖性,因此减小驱动电压会降低MOSFET的功耗。然而,降低驱动电压也将减小导通电流并降低导通状态电流与截止状态电流之间的比率。一种降低MOSFET驱动电压但保持晶体管导通状态与截止状态电流比率的方法是减小MOSFET的亚阈值摆幅。然而,在室温下,亚阈值摆幅固定在60mV/decade,并对功率缩放构成了基本限制。
隧穿场效应晶体管(TFET)是一种结构类似于MOSFET的结构的晶体管。然而,两种结构之间的切换机制是不同的,使得TFET成为低功率电子器件的有希望的候选者。TFET通过屏障调制量子隧穿而不是像MOSFET那样调制屏障上的热电子发射来切换。因此,TFET不受载流子热尾的限制,载流子热尾将MOSFET的亚阈值摆幅在室温下限制为约60mV/decade。TFET可实现低于60mV/decade(例如,约40mV/decade)的亚阈值电压摆幅。因此可缩放TFET驱动电压以减小功耗,而不会减小导通状态与截止状态电流比。
使用III-V族材料(如砷化铟(InAs)和镓锑(GaSb))与硅MOSFET的集成TFET可能具有挑战性,因为III-V族材料具有低的热容差(例如,低于200℃),且产生的TFET结构可能具有差的机械稳定性。同时,硅基TFET不提供可观的电流特性。
本文描述的实施例针对通过使用III族氮化物材料(诸如氮化镓、氮化铝和氮化铝镓)来集成FET和TFET结构。因此,产生的FET结构可用于高驱动电压操作(例如,在约0.6V和约1.2V之间),且产生的TFET结构可用于低驱动电压操作(例如,约0.3V)。FET和TFET结构均采用基于鳍的架构来制造,该架构可提供:(i)适用于超小型器件的机械稳定性,(ii)FET和TFET之间的无缝集成,和(iii)增加的器件密度。在一些实施例中,制造的FET和TFET包括极性界面,该界面用作局部界面极化电荷平面,该平面在鳍内引起相应的表层电荷密度。因此,通过使用极性界面,可在单个鳍上形成p沟道FET和n沟道FET,这可进一步减小产生的FET结构的占用面积。根据一些实施例,未掺杂的蚀刻氮化镓鳍是FET和TFET结构的起始点。此外,使用单晶介电材料作为栅极电介质有效地减小了TFET中的界面态密度(Dit)并改善了截止电流限制。
图1是用于制造具有减小的占用面积的反相器的示例性方法100的流程图。更具体地,该反相器包括形成在单个鳍上的p型FET结构和n型FET结构。该p型和n型FET结构使用III族氮化物材料制造,并可在约0.7V和约1.2V之间的驱动电压下操作。可在方法100的各种操作之间实施其他制造操作并可仅为了清楚起见而省略其他制造操作。本发明的实施例不限于方法100。
制造方法100开始于操作110并在未掺杂GaN层上形成氮化镓(GaN)鳍。在一些实施例中,在晶圆(诸如硅晶圆、蓝宝石晶圆或碳化硅晶圆)上外延生长未掺杂GaN层。在一些实施例中,生长GaN层以使其顶面平行于m平面
Figure BDA0002214312770000061
根据一些实施例,m平面
Figure BDA0002214312770000062
是非极性平面,例如,净极化为零。作为示例而非限制,可通过在GaN层的顶面上沉积和图案化光刻胶层来形成鳍,并通过干蚀刻工艺蚀刻暴露的GaN层来形成GaN鳍。在上述干蚀刻工艺期间,图案化的光刻胶层可用作蚀刻掩模。在一些实施例中,干蚀刻工艺是各向异性的,使得鳍形成有基本垂直的侧面(侧壁)。在干蚀刻工艺之后,可以利用湿蚀刻工艺来去除图案化的光刻胶。
根据一些实施例,图2A是操作110产生的结构的等轴视图,其中,鳍210形成在蚀刻的GaN层200上。在图2A中,为简单起见,未示出支撑GaN层200的晶圆。由于鳍210由GaN层200形成,所以其顶面210T具有与GaN层200的顶面200T相同的晶体取向(例如,平行于m平面
Figure BDA0002214312770000063
)。在一些实施例中,图案化的光刻胶沿x-y平面的取向使得当形成鳍210时,鳍的侧壁表面210S可平行于c-平面{0001},因为c-平面{0001}是极性平面,这意味着沿c-平面的净极化是非零的并存在局部极化电荷。更具体地,一个侧壁表面210S可平行于(0001)平面,并且相对的侧壁表面210S可平行于
Figure BDA0002214312770000064
平面。
图2B是横跨切割线220的鳍210的截面图,其中,鳍侧壁表面210S(A)平行于(0001)平面,并且表面210S(B)平行于
Figure BDA0002214312770000065
平面。
参考图2A,鳍210的高度210h介于约30nm和约50nm之间(例如,约30nm和约40nm之间、约35nm和约45nm之间、约40nm和约50nm之间)。此外,鳍210的宽度210w介于约5nm和约10nm之间(例如,约5nm、约8nm、约9nm、约10nm等)。作为示例而非限制,鳍210的长度可为约80nm。更高和更窄的鳍是可能的;然而,这种鳍结构的机械刚性可能较差。此外,较宽的鳍(例如,宽于10nm)可能影响器件密度,因为较宽的鳍将占据GaN层200的较大表面积。
出于示例目的,将使用横跨切割线220和230的鳍210沿x轴的截面图以及沿y轴的截面图来描述后续的制造操作。
参考图1,方法100继续操作120,其中,在鳍210的每个侧壁表面210S上生长极性层(例如,介电层)。图3A是横跨图2A的切割线220的鳍210的截面图。作为示例而非限制,将在介电层的上下文中描述生长在鳍210的每个侧壁表面210S上的极性层。例如,在图3A中,在鳍210的侧壁表面210S(A)上生长介电层300A,且在鳍210的相对侧壁表面210S(B)上生长介电层300B。在一些实施例中,介电层300A和300B被称为“介电壳”并包括氮化铝镓(AlGaxN),其中,Ga‘x’的量可等于或大于零(例如,x≥0)。
在一些实施例中,AlGaxN介电层300A和300B相同或具有不同的摩尔分数比(例如,Al与N的组成比和/或Ga浓度)。此外,AlGaxN介电层300A和300B可生长成相同或不同的厚度。作为示例而非限制,在AlGaxN介电层300A和300B具有相同的厚度和摩尔分数比的情况下,它们可在单个沉积中沉积。另一方面,如果AlGaxN介电层300A和300B具有不同的厚度和/或摩尔分数比,则它们可以依次沉积。例如,牺牲层(图3A中未示出)可覆盖鳍210的一个侧壁表面210S(例如,侧壁表面210S(B)),而暴露鳍210的相对侧壁表面210S(例如,侧壁表面210S(A))。然后可将AlGaxN沉积在鳍210的暴露的侧壁表面210S上。随后,覆盖鳍210的沉积的侧壁表面210S,并暴露鳍210的未沉积的侧壁表面210S。然后将AlGaxN沉积在鳍210的未沉积的侧壁表面210S上。在一些实施例中,AlGaxN介电层300A和300B覆盖鳍210的所有表面,包括顶面210T
在每次沉积期间,可通过沉积工艺参数控制AlGaxN介电层300A和300B中的每个的厚度和摩尔分数比。在一些实施例中,AlGaxN介电层300A和300B通过金属有机化学气相沉积(MOCVD)来沉积。在一些实施例中,AlGaxN介电层300A和300B的厚度在约1nm至约3nm之间(例如,约1nm、约1.5nm、约2nm、约2.5nm、约3nm)的范围。在一些实施例中,AlGaxN介电层300A和300B具有约9.5的介电常数(k值)。在一些实施例中,介电层300A和300B具有晶体结构,该晶体结构减小每个介电层与它们相应的鳍侧壁表面之间的界面态密度Dit。这进而可促进所形成的晶体管的低功率操作。
根据一些实施例,由于在每种材料(例如,GaN和AlGaxN)的主体中具有不同量的自发和压电极化,所以在GaN鳍210和AlGaxN介电层300A和300B之间的界面处形成局部电荷。产生的局部界面极化电荷是两种材料中的主体极化差异。根据一些实施例,235A和235B分别是GaN鳍210和AlGaxN介电层300A和300B之间的界面处的局部界面极化电荷密度。例如,每个局部界面极化电荷密度235A和235B可被认为是在y-z平面上延伸的二维(2-D)平面(例如,侧壁表面210S(A)和210S(B))而没有x轴分量(例如,x=0)。作为示例而非限制,GaN和AlGaxN之间的界面处的局部极化电荷密度可定义为GaN极化和AlGaxN极化之间的差异。例如,假设GaN是未应变的且AlGaxN介电层300A和300B是拉伸应变的,则局部界面极化电荷密度235A在210S(A)(例如,沿(0001)平面)处可为约0.104C/cm2(例如,等于约+6.5x1013/cm2)且局部界面极化电荷密度235B在210S(B)(例如,沿
Figure BDA0002214312770000081
平面)处可为约-0.104C/cm2(例如,等于约-6.5x1013/cm2)。界面极化电荷的相反符号允许在单个未掺杂GaN鳍上形成nFET和pFET。每个局部界面极化电荷密度(例如,235A和235B)可包括自发极化和压电极化分量,其中,压电极化分量取决于每个相应层(例如,GaN和AlGaxN)中是否存在应变。作为示例而非限制,随着AlGaxN层中Ga‘x’的量增加,GaN和AlGaxN之间的晶格失配也增加。由于晶格失配有助于应变,且本文讨论的材料是极性半导体,因此应变产生极化电荷。此外,极化电荷的量可随着应变量(例如,随着AlGaxN中的Ga‘x’的量)的增加而增加。随后,极化电荷量并且因此应变可用于调制FET的阈值电压。在一些实施例中,约0.104C/cm2的绝对局部界面极化电荷密度235A和235B可根据栅极偏压条件来诱导相应的GaN绝对表面表层电荷密度236A和236B大于约5x1012/cm2。例如,根据栅极偏压条件,相应侧壁表面210S(A)和210S(B)上的GaN表面表层电荷密度236A和236B可分别大于约-5x1012/cm2和约+5x1012/cm2。表面表层电荷密度236A和236B可被认为是“准2D”,这是因为它们沿y-z平面(例如,侧壁表面210S(A)和210S(B))延伸并包括小的x轴分量(例如,X≠0)。因此,顾名思义,表面表层电荷密度236A和236B形成具有非零x轴值的表层。因此,每个GaN表面表层电荷密度236A和236B的“厚度”(例如,x轴值)可在约
Figure BDA0002214312770000091
和约
Figure BDA0002214312770000092
之间(例如,约
Figure BDA0002214312770000093
Figure BDA0002214312770000094
Figure BDA0002214312770000095
Figure BDA0002214312770000096
Figure BDA0002214312770000097
等)的范围,其中,厚度是指从每个侧壁表面210S沿x轴朝向鳍210的中心所测量的距离d,如图3A所示。在一些实施例中,可通过结合在介电层300A和300B中的Ga‘x’的厚度和/或量来调制GaN和AlGaxN之间的界面处的局部极化电荷密度235A和235B。在一些实施例中,每个介电层300A和300B与鳍210之间的界面处的局部极化电荷密度235A和235B分别由AlGaxN介电层中的Ga‘x’的量控制。因此,AlGaxN中的Ga的量可基于期望的局部界面极化电荷密度(例如,235A和235B)以及最佳nFET或pFET操作和性能所需的相应GaN表面表层电荷密度(例如,236A和236B)来定制。
GaN/AlGaxN界面处的正极化局部极化电荷235A(例如,在侧壁表面210S(A)处)和GaN/AlGaxN界面处的负极化局部极化电荷235B(例如,在侧壁表面210S(B))分别针对形成在GaN鳍210上的n型(n沟道)和p型(p沟道)FET而以类似于供体平面和受体平面的方式起作用。因此,根据一些实施例,n型(或n沟道)FET(以下也称为“nFET”)可形成在鳍侧壁表面210S(A),并且p型(或p沟道)FET(以下也称为“pFET”)可形成在鳍侧壁表面210S(B)上。
根据一些实施例,横跨鳍210的主体(例如,在GaN表面表层电荷密度236A和236B之间)存在最小电流或没有电流流动。这是因为GaN/AlGaxN界面处(例如,侧壁表面210S(A)和210S(B)上)的局部极化电荷具有相反的符号(例如,分别为正和负),这进而产生横跨鳍210的电场,该电场(a)将产生的移动表面表层电荷限制在GaN/AlGaxN界面处的GaN中,以及(b)耗尽来自鳍210主体的电荷。
图3B示出了沿线AA’(例如,横跨介电层300A、鳍210、介电层300B)的图3A所示的结构的模拟能带图310,此时,在介电层300A上施加正电压(例如,+1伏特),并没有在介电层300B上施加电压(例如,0伏特)。作为示例而非限制,假设鳍的宽度210W为约8nm且介电层300A和300B的等效氧化物厚度(EOT)为约0.87nm,则已生成模拟能带图310。
由于上述偏置条件,形成在鳍侧壁表面210S(A)上的nFET将处于导通状态(例如,在强反相下)且形成在鳍侧壁表面210S(B)上的pFET将处于截止状态。由于在介电层300A上施加正电压(例如,+1伏特),所以与300A接触的电极的费米能级(EF)被向下“推动”,如箭头330所示。同时,GaN鳍210的EF是恒定的,且GaN鳍210的导带(EC)向下弯曲到其与EF交叉的点处。因此,如阴影区域340所示,负表面表层电荷累积在鳍210和介电层300A之间的界面处。在一些实施例中,阴影区域340对应于图3A中所示的表面表层电荷密度236A。此外,阴影区域340沿x轴的宽度对应于图3A中所示的GaN表面表层电荷密度236A的距离d,并示出了表面表层电荷是准2D的,例如,限制在鳍210和介电层300A之间的界面附近并具有非零的x轴值。
图3B还包括沿AA’线的图3A的鳍210的对数刻度的特定电阻率曲线320。两条曲线(例如,模拟能带图310和特定电阻率图320)共享相同的x轴,该轴对应于图3A的x轴。根据特定电阻率曲线320,GaN鳍210内的特定电阻率增加到鳍中心的约1023Ωcm。这意味着鳍210的主体是高电阻的,并且因此存在横跨鳍210的主体(例如,在图3A中所示的GaN表面表层电荷密度236A和236B之间)的最小电流或没有电流流动。如上所述,这是因为GaN/AlGaxN界面处(例如,侧壁表面210S(A)和210S(B)上)的局部极化电荷具有相反的符号(例如,分别为正和负),这进而产生横跨鳍210的电场,该电场(a)将产生的移动表面表层电荷限制在GaN/AlGaxN界面处的GaN中,以及(b)耗尽来自鳍210主体的电荷。为了进行比较,特定电阻率曲线320还包括未掺杂硅的固有电阻率极限(例如,约4x105Ωcm),如线350所示。
由于鳍210的顶面210T平行于非极性m平面
Figure BDA0002214312770000101
因此不存在极化电荷,在鳍210的顶面210T上没有形成FET(n型或p型)。
如上所述,根据介电层300A和300B的厚度和成分,nFET和pFET可形成为分别具有不同的局部界面极化电荷密度。这种灵活性使得可基于电路要求来形成具有不同规格的nFET和pFET。
界面极化电荷的存在消除了对GaN鳍210中的注入工艺和/或化学掺杂区域的需要。此外,与注入相比,界面极化电荷是有利的,原因如下:(i)界面极化电荷非常局部化;(ii)它们相应的密度(例如,235A和235B)可通过介电层300A和300B的生长来控制;以及(iii)它们不需要激活退火或额外处理。相比之下,即使在室温下,由于掺杂剂倾向于扩散,所以注入工艺也不能在鳍210的侧壁表面复制这种极端的掺杂分布。
参考图1,方法100继续操作130,并在AlGaxN介电层300A和300B上沉积栅电极层。在一些实施例中,栅电极层在侧壁表面210S(A)/210S(B)之间是共用的,并可用原子层沉积(ALD)在AlGaxN介电层300A和300B上沉积约3nm的厚度。在一些实施例中,栅电极层400在侧壁表面210S(A)和210S(B)之间是不同的,并以类似于上述在侧壁表面210S(A)和210S(B)上形成不同的介电层300A和300B的方式依次沉积在相应的侧壁表面210S(A)和210S(B)上。在一些实施例中,栅电极层可包括一种或多种金属、一种或多种金属合金、一个或多个金属层或它们的组合。作为示例而非限制,栅电极层可包括钨、铝-钛合金、氮化钛、氮化钽、钛、其他金属、其他合金、金属氮化物或它们的组合。图4示出了在沉积栅电极层400之后的产生的结构。虽然未在图4中示出,但是栅电极层400覆盖整个鳍210。
在一些实施例中,通过光刻和蚀刻操作来图案化鳍210和介电层300A和300B上沉积的栅电极层400,以形成覆盖鳍210的部分(例如,鳍210的中间部分)的栅极结构。由于图案化工艺,鳍210的其他部分由介电层300A和300B覆盖。图5是沿鳍210的长度(例如,沿y轴)的鳍210的截面图,其示出了在上述图案化工艺之后产生的栅极结构500。在图5中,由AlGaxN介电层300A覆盖的鳍210的轮廓由虚线示出。
参考图1,方法100继续操作140并形成间隔件以覆盖图5中所示的栅极结构500的侧壁表面。作为示例而非限制,间隔件材料可包括氮化硅、氧化硅或氧化铝。此外,可以通过在栅极结构500上沉积间隔件材料并在鳍210上沉积介电层300A和300B,图案化该间隔件材料使得间隔件材料覆盖栅极结构500和介电层300A和300B中与栅极结构500相邻的部分,以及通过各向异性蚀刻工艺来从栅极结构500的顶面去除间隔件材料,该各向异性蚀刻工艺在水平表面上(例如,在栅极结构500和介电层300A和300B的顶部上)更快地去除,并在垂直表面上(例如,在栅极结构500的侧壁上)更慢地去除间隔件材料,来形成间隔件结构。根据一些实施例,产生的间隔件600如图6所示。图7是图6沿x轴的截面图。在图7的示例中,栅极结构500位于间隔件600后面并且是不可见的。上述间隔件形成工艺是示例性的而非限制性的。因此,可使用可选的间隔件形成工艺,并且这些工艺均在本公开的精神和范围内。
参考图1,方法100继续操作150并形成接触开口。作为示例而非限制,可以如下形成接触开口。可沉积诸如氧化硅、氮化硅、氧化铝或它们的组合的介电层并随后平坦化介电层,使得鳍210和栅极结构500嵌入介电层中。上述材料清单并非详尽无遗,并且可使用其他材料。这种材料还可包括介电常数低于约3.9的低k介电材料。根据一些实施例,图8是在形成和随后平坦化介电层800之后鳍210的沿y轴的截面图,其中“覆盖的”结构和层(例如,鳍210、栅极结构500、介电层300A和间隔件600)由虚线表示。作为示例而非限制,可在栅极结构500和间隔件600上形成硬掩模层(图8中未示出),以用作用于介电层800的平坦化操作的抛光停止层。作为示例而非限制,介电层800的顶面可与栅极结构500的顶面基本上共面。根据一些实施例,介电层800与间隔件600的材料不同。例如,如果间隔件600的材料是氮化硅,则介电层800的材料是除氮化硅之外的材料(例如,氧化硅或低k电介质)。
在一些实施例中,可以在介电层800中形成接触开口,以依次暴露鳍210的侧壁表面210S(A)和210S(B),以形成用于每个nFET和pFET的源极/漏极接触件。在介电层800中形成接触开口,以暴露例如侧壁表面210S(A)上的介电层300A。介电层800中的接触开口可通过对图案化的硬掩模层或图案化的光刻胶层的干蚀刻工艺形成。图9是在形成接触开口900之后的图8的平面图,该接触开口900暴露了侧壁表面210S(A)上的介电层300A。为简单起见,图9中未示出图案化的硬掩模层或图案化的光刻胶层。随后可使用干蚀刻工艺从鳍210的侧壁表面210S(A)选择性地去除暴露的AlGaxN介电层300A。在一些实施例中,干蚀刻工艺不会去除介电层300A的由栅极结构500和间隔件600覆盖的部分。
一旦去除暴露的AlGaxN介电层300,并且参考图1和操作160,则沉积n掺杂GaN层。作为示例而非限制,沉积的n掺杂GaN层在其生长期间用n型掺杂剂(供体)化学掺杂。在一些实施例中,掺杂GaN中的n型掺杂剂包括硅或锗,并具有约1019原子/cm3至约5x1019原子/cm3的掺杂浓度。作为示例而非限制,可用MOCVD工艺沉积厚度在约1nm和约5nm之间的n掺杂或n型GaN。在一些实施例中,n掺杂GaN层覆盖接触开口900的侧壁和鳍210的暴露的侧壁表面210S(A),如图10所示。
参考图1和操作170,可将“n型接触电极”沉积至接触开口900。根据一些实施例,如本文所用的,术语“n型接触电极”是指用于nFET的金属,nFET将与pFET不同。图11是在操作160和在接触开口900中沉积n型接触电极1100之后的图10的顶视图。作为示例而非限制,可用ALD工艺沉积厚度在约1nm和约5nm之间的n型接触电极1100。在一些实施例中,n型接触电极可包括(i)钛和铝的堆叠件或(ii)钪。然而,上述金属不是限制性的并且可使用其他合适的金属。
在一些实施例中,操作170结束nFET的形成。一旦形成用于nFET的接触件,就可遵循如上所述的类似工艺以形成用于pFET的接触件。例如,可在介电层800中形成接触开口(如接触开口900),以暴露鳍210的侧壁表面210S(B)上的介电层300B。随后,去除暴露的介电层300B以暴露鳍210的侧壁表面210S(B)的未由栅极结构500和间隔件600覆盖的部分。
参考图1和操作180,沉积p型GaN层以覆盖鳍210的接触开口和侧壁表面210S(B)的侧壁。根据一些实施例,可用MOCVD工艺沉积厚度在约1nm和约5nm之间的p掺杂GaN层。如在n掺杂GaN的情况下,p掺杂GaN在其生长期间化学掺杂。根据一些实施例,用于p掺杂GaN的p型掺杂剂(受体)包括镁并具有约1x1018原子/cm3的掺杂浓度。在一些实施例中,p掺杂GaN层覆盖接触开口的侧壁和鳍210的暴露的侧壁表面210S(B)
参考图1和操作190,可在接触开口中沉积“p型接触电极”。根据一些实施例,术语“p型接触电极”是指用于pFET的金属,pFET将与nFET不同。
图12是在操作170和180以及分别沉积p掺杂GaN 1200和p型接触电极1220之后的图11的顶视图。作为示例而非限制,可用ALD工艺沉积厚度在约1nm和约5nm之间的p型接触电极1220。在一些实施例中,p型接触电极包括钯或铂。然而,上述金属不是限制性的,并且可使用其他合适的金属。根据一些实施例,方法100的操作170和180结束pFET的形成。
根据一些实施例,图12中所示的nFET和pFET配置是具有减小的占用面积的反相器结构1230,其中,形成横跨鳍210的侧壁表面210S(A)的nFET,且形成横跨鳍210的侧壁表面210S(B)的pFET。图12中所示的反相器结构1230的nFET和pFET的电流沿着y轴限制在GaN鳍的相应表面区域,沿着侧壁表面210S(A)和210S(B)。在同一GaN鳍210上形成nFET和pFET的制造方法100的优势是形成具有约30%的面积密度增益的反相器。反相器结构1230可改善芯片中每单位面积的晶体管封装密度。根据一些实施例,图12的nFET和pFET可在约0.7V和约1.2V之间的驱动电压范围内操作。
图13是用于制造可在约0.3V的低驱动电压下操作的n型TFET或p型TFET的方法1300的流程图。利用方法1300制造的TFET可具有低功耗。更具体地,用方法1300制造的n型和p型TFET使用AlN/GaN/InGaxN/GaN(例如,III族氮化物)架构,其中x等于或大于零(例如,x≥0)。可在方法1300的各个操作之间实施其他制造操作,并可仅为了清楚起见而省略其他制造操作。本发明公开的实施例不限于方法1300。
参考图13,方法1300开始于操作1310并在未掺杂GaN层上形成GaN鳍。在一些实施例中,操作1310与图1中所示的方法100的操作110相同。因此,来自操作1310的产生的GaN鳍与图2A和图2B中的鳍210相同。例如,来自操作1310的GaN鳍具有与图2A和图2B中所示的GaN鳍210相同的尺寸和晶体取向。
方法1300继续操作1320并在GaN层的侧壁表面上生长氮化铟镓(InGaxN,其中,x≥0)极化层。如上所述,通过覆盖鳍的不期望沉积的侧壁表面并暴露鳍的期望沉积的侧壁表面,可实现在GaN鳍210的侧上选择性沉积或形成层。
在一些实施例中,局部极化电荷存在于InGaxN极化层和GaN鳍210之间的界面处,例如,类似于先前讨论的AlGaxN介电层和GaN鳍210之间的界面处的局部极化电荷。然而,在这种情况下的局部界面极化电荷密度可与AlGaxN介电层的情况不同。作为示例而非限制,InGaxN/GaN界面处的局部界面极化电荷密度的绝对值可在约5x1012/cm2和约5x1014/cm2之间。参考图2B,对于n型(n沟道)TFET,InGaxN极化层沉积在侧壁表面210S(A)上,该侧壁表面210S(A)平行于GaN极化(0001)平面。相反地,对于p型(p沟道)TFET,InGaxN极化层沉积在侧壁表面210S(B)上,该侧壁表面210S(B)平行于极化GaN
Figure BDA0002214312770000151
平面。因此,根据FET的类型,InGaxN极化层可形成在侧壁表面210S(A)或210S(B)上。作为示例而非限制,使用MOCVD工艺生长厚度在约1nm和约3nm之间的InGaxN层。在一些实施例中,可通过InGaxN介电层1400的Ga‘x’的厚度和量来调制GaN和InGaxN之间的界面处的局部极化电荷密度。
作为示例而非限制,将使用图14至图17以及方法1300的操作来描述n型TFET的形成。方法1300的操作也可用于形成p型TEFT。
图14示出了在侧壁表面210S(A)上沉积InGaxN极化层1400之后的图2B的鳍210,该侧壁表面210S(A)平行于GaN极化(0001)平面。如上所述,例如,在InGaxN极化层1400和GaN鳍210之间的界面处,侧壁表面210S(A)上存在负极局部界面极化电荷。在一些实施例中,顶面210T平行于m平面
Figure BDA0002214312770000152
该平面是非极性平面,因此顶面210T上不存在极化电荷。
在一些实施例中,如果需要p型TFET,则可在侧壁表面210S(B)而不是在侧壁表面210S(A)上沉积InGaxN极化层。在一些实施例中,p型TFET结构是沿z轴的n型TFET结构的镜像。
参考图13,方法1300继续操作1330并在InGaxN极化层上生长掺杂GaN层。在一些实施例中,基于TFET的类型(例如,nFET或pFET)来选择用于GaN层的掺杂剂(n型或p型)。例如,在图14的n型TFET的情况下,GaN层掺杂有n型掺杂剂。在一些实施例中,掺杂GaN层用作形成的TFET的“漏极”,而GaN鳍则用作形成的TFET的“源极”。
作为示例而非限制,沉积的GaN层在其生长期间用n型掺杂剂(供体)或p型掺杂剂(受体)化学掺杂。在一些实施例中,使用硅或锗掺杂剂来形成n掺杂GaN层,其中,活化的掺杂浓度在约1019电子/cm3和约5x1019电子/cm3之间。类似地,使用镁掺杂剂形成p掺杂GaN层,其中,镁掺杂剂具有约1x1018孔/cm3的活化掺杂浓度。上述n掺杂和p掺杂GaN层的活化掺杂浓度是示例性的。因此,更高的活化掺杂浓度(例如,高于约5x1019电子/cm3且高于约1x1018孔/cm3)也是期望的并在本发明的精神和范围内。作为示例而非限制,可用MOCVD工艺沉积厚度在约2nm和约5nm之间的n掺杂和p掺杂GaN。
作为示例而非限制,图15示出了在InGaxN极化层1400上沉积n型掺杂GaN层1500之后的图14。在n型掺杂GaN层1500和InGaxN极化层1400的沉积或生长期间,侧壁表面210S(B)保持被硬掩模覆盖(图15中未示出),因此没有在GaN鳍210的侧壁表面210S(B)上沉积。在形成p型TFET的情况下,掺杂GaN层可掺杂有p型掺杂剂,且其可沉积在侧壁表面210S(B)上。
参考图13,方法1300继续操作1340,其中,在GaN鳍210的两个侧壁表面(例如,侧壁表面210S(A)和侧壁表面210S(B))上沉积AlN介电层。对于该操作,暴露侧壁表面210S(B),使得AlN介电层也可沉积在侧壁表面210S(B)上。作为示例而非限制,牺牲硬掩模层或牺牲覆盖层可沉积在顶面210T上的掺杂GaN层1500上,以防止AlN介电层沉积在鳍210顶面210T上的掺杂GaN层1500上。
类似地,在形成p型TFET的情况下,可暴露侧壁表面210S(A),使得AlN介电层可沉积在GaN鳍210的两个侧壁表面上。
参考图13,方法1300继续操作1350并在AIN介电层和InGaxN极化层上沉积栅电极层。换句话说,在GaN鳍210的侧壁表面上选择性地沉积栅电极层。例如,这可通过用硬掩模覆盖侧壁表面的AlN介电层的不期望沉积栅极层的位置来实现。例如,在图15的n型TFET中,可在侧壁表面210S(A)上沉积栅电极。图16示出了操作1340和1350且在GaN鳍210的侧壁表面210S(A)和210S(B)上沉积AIN介电层1600以及在InGaxN极化层1400和侧壁表面210S(A)上的AIN介电层1600上沉积栅电极层1610之后产生的n型TFET结构。在图16中,为简单起见,未示出侧壁表面210S(B)上的硬掩模层。
图17是根据一些实施例的具有p掺杂GaN层1700的p型TFET结构的截面图。图17中所示的p型(p沟道)TFET结构可以是图16中所示的n型(n沟道)TFET的镜像结构。
在一些实施例中,并参考图16,图案化侧壁表面210S(A)上的包括有栅电极层1610、AlN介电层1600、n掺杂GaN层1500和InGaxN极化层1400的堆叠件以在例如鳍210的中间部分上形成结构。在图案化工艺期间,从鳍210的其他部分去除栅电极层1610、AlN介电层1600、n掺杂GaN层1500和InGaxN极化层1400,并暴露这些部分的侧壁表面210S(A)。在一些实施例中,并在上述图案化工艺期间,不从侧壁表面210S(B)去除AlN介电层1600。
作为示例而非限制,图18是在上述图案化工艺之后的鳍210的顶视图。在图18中,InGaxN极化层1400由n掺杂GaN层1500覆盖[该层未在图18中正确地表示]并用虚线表示。
类似于图18所示的n型TFET,也图案化图17中所示的侧壁表面210S(B)上具有栅电极层1610、AlN介电层1600、p掺杂GaN层1700和InGaxN极化层1400的堆叠件以在例如鳍210的中间部分上形成结构。在图案化工艺期间,从鳍210的其他部分去除栅极层1610、AlN介电层1600、p掺杂GaN层1700和InGaxN极化层1400,并暴露这些部分的侧壁表面210S(B)。在一些实施例中,在上述图案化工艺期间,不去除侧壁表面210S(A)上的AlN介电层1600。
在一些实施例中,在图案化结构的侧壁上形成间隔件,该图案化结构包括栅电极层、AlN介电层、掺杂GaN层和InGaxN极化层。间隔件的形成类似于图6中所示的间隔件600的形成,间隔件600的形成已经在上面针对图1中所示的方法100的操作140进行了描述。作为示例而非限制,图18包括覆盖图案化的栅极层1610、AlN介电层1600、掺杂GaN层1500和InGaxN极化层1400堆叠件的侧壁表面的间隔件1800。在一些实施例中,基于与图1中所示的方法100的操作140所描述的相同的制造操作,可在n型和p型TFET上形成间隔件。
参考图13,TFET制造方法1300继续操作1360并形成用于n型TFET或p型TFET的源极和漏极接触件。在一些实施例中,在鳍210的侧壁上形成源极接触件,其工艺类似于图1中所示的方法100的操作150至180。然而,在一个实施例中,在TFET的情况下,将操作160的n掺杂GaN层和操作180的p掺杂GaN层替换为InGaxN极化层,该极化层对于n型TFET和p型TFET可以是共用的。分别在用于nTFET的n-GaN层1500的顶面上以及用于pTFET的p-GaN层1700的顶面上形成漏极接触件。
作为示例而非限制,将为图18的n型TFET提供源极接触件形成工艺。然而,用于p型TFET的源极接触件形成工艺类似于图18的n型TFET的源极接触件形成工艺,除了使用n接触电极,而不是p接触电极之外。
根据图13的操作1360,可以在沉积在图18的n型TFET结构上的介电层中形成源极接触开口。作为示例而非限制,介电层可类似于图8至图12中所示的介电层800,并可沉积在衬底200上方,使得其顶面基本上与栅极层1610的顶面共面。在一些实施例中,沉积的介电层完全覆盖栅极层1610。此外,介电层可以与间隔件1800的材料不同。例如,如果间隔件1800的材料是氮化硅,则用于介电层的材料不是氮化硅(例如,氧化硅或低k电介质)。介电层中的源极接触开口暴露鳍210的侧壁表面210S(A)。例如可通过蚀刻掩模(诸如图案化的硬掩模或图案化的光刻胶)使用干蚀刻工艺形成介电层中的源极接触开口。图19是在介电层1910中形成源极接触开口1900之后的图18的平面图,该源极接触开口1900暴露介电侧壁表面210S(A),如上所述。在一些实施例中,如图19所示,源极接触开口1900形成在间隔件1800附近。
在一些实施例中,在开口1900中生长另一个InN极化层。InN极化层覆盖开口1900的侧壁表面和GaN鳍210的暴露的侧壁表面210S(A)。接下来,在源极接触开口1900中沉积p型接触电极以形成源极金属接触件。在p型TFET中,沉积n型源极接触电极而不是p型源极接触电极。图20是在接触开口1900中沉积InN极化层2000和p型接触电极2010之后的图19所示的顶视图。
作为示例而非限制,可用ALD工艺沉积厚度在约2nm和约5nm之间的n型和p型接触电极。在一些实施例中,n型接触电极包括(i)钛和铝或(ii)钪的堆叠件,且p型接触电极包括钯或铂。上述金属是示例性的而非限制性的,并且其他合适的金属也是可能的。
如上所述,p型TFET结构可以是n型TFET的沿z轴的镜像结构,且它们的制造也可用方法1300来描述。在一些实施例中,可以与图12中所示的反相器结构的nFET和pFET同时形成n型和p型TFET。因此,如本文所述,在同一电路中集成FET和TFET是可能的。此外,利用方法1300制造的TFET可在约0.3V的低驱动电压下操作,并且因此具有减小的功耗和发热。
如上所述,分别在用于nTFET的n-GaN层1500的顶面上以及用于pTFET的p-GaN层1700的顶面上形成漏极接触件。例如并参考图20,可在n-GaN层1500的顶面上形成漏极接触件2020。作为示例而非限制,漏极接触件2020的形成可描述如下。例如,通过蚀刻掩模(例如图案化的硬掩模或图案化的光刻胶)使用干蚀刻工艺来在介电层1910中形成漏极接触开口,以暴露n-GaN层1500的顶面。随后,可在漏极开口中沉积n型接触电极以形成漏极接触件2020,如图20所示。如果介电层1910的顶面与GaN层1500的顶面共面,则可在介电层1910上方沉积第二电介质,使得可在第二介电层上形成漏极开口。与n型接触电极相反,可使用p型接触电极以类似的方式形成pTFET的漏极接触件。如上所述,可用ALD工艺沉积厚度在约2nm和约5nm之间的n型和p型接触电极。在一些实施例中,n型接触电极包括(i)钛和铝或(ii)钪的堆叠件,且p型接触电极包括钯或铂。上述金属是示例性的而非限制性的,其他合适的金属也是可能的。
根据一些实施例,图21是导通状态期间的nTFET的模拟能带图,图22是导通状态期间的pTFET的模拟能带图。作为示例而非限制,图21可以是图16中所示的nTFET分隔线BB’的能带图,且图22可以是图17中所示的分隔线CC’的pTFET结构。局部界面极化电荷qb+和qb-也显示在GaN鳍、InGaxN极化层和掺杂GaN层之间的相应界面上。
对于在导通状态期间发生的带间隧穿情况,图21中的源极的价带(Ev)中的电子必须在不借助阱(例如,中间能级)的情况下隧穿到漏极的导带(EC)。因此,对于发生的带间隧穿情况,图22中的漏极的价带(EV)中的电子必须在不借助阱(例如,中间能级)的情况下隧穿到图22中的源极的导带(EC)。
本发明描述的实施例针对使用III族氮化物材料(诸如,氮化镓、氮化铝、氮化铝镓和氮化铟)来集成用于FET和TFET鳍式结构的制造工艺。产生的FET可用于高驱动电压操作(例如,在约0.6V和约1.2V之间),且TFET结构可用于低驱动电压操作(例如,约0.3V)。FET和TFET结构均采用鳍式架构来制造,该架构可提供:(i)适用于超小型器件的机械稳定性,(ii)FET和TFET之间的无缝集成和(iii)增加的器件密度。根据一些实施例,制造的FET和TFET具有极性界面,该极性界面提供局部界面极化电荷平面。通过使用极性和非极性界面,可在单个鳍上制造n型和p型FET,这可进一步减小产生的FET结构的占用面积并消除注入掺杂的使用。根据一些实施例,未掺杂的蚀刻氮化镓鳍是FET和TFET结构的起始点。此外,使用单晶AlN或AlGaxN高k电介质可减小界面态密度(Dit)并可改善截止电流限制。
在一些实施例中,半导体结构包括鳍,该鳍包括非极性顶面和两个相对的第一和第二极性侧壁表面。半导体结构还包括位于第一极性侧壁表面上的第一极性层、位于第二极性侧壁表面上的第二极性层,以及位于第一和第二极性层上的栅电极层。
在一些实施例中,第一极性侧壁表面和第二极性侧壁表面包括具有相反极性的局部界面极化电荷。在一些实施例中,第一极性层和第二极性层中的每个均包括具有相同或不同摩尔分数比的氮化铝或氮化铝镓。在一些实施例中,第一极性层和第二极性层中的每个均具有相同或不同的厚度。在一些实施例中,第一极性层和第二极性层的厚度在1nm和3nm之间。在一些实施例中,鳍包括未掺杂氮化镓,未掺杂氮化镓的高度在30nm和50nm之间并且宽度在8nm和10nm之间。在一些实施例中,第一极性侧壁表面、第一极性层和第一极性层上的栅电极层形成第一类型的场效应晶体管,并且第二极性侧壁表面、第二极性层和第二极性层上的第二栅电极层形成第二类型的场效应晶体管,第二类型的场效应晶体管与第一类型的场效应晶体管不同。在一些实施例中,第一类型的场效应晶体管是n型,并且第二类型的场效应晶体管是p型。在一些实施例中,半导体结构还包括:第一掺杂半导体材料层,位于鳍的未由第一极性层覆盖的第一极性侧壁表面上;第二掺杂半导体材料层,位于鳍的未由第二极性层覆盖的第二极性侧壁表面上;第一电极,位于第一掺杂半导体材料上;以及第二电极,位于第二掺杂半导体材料上,其中,第一电极与第二电极不同。在一些实施例中,第一掺杂半导体材料包括n掺杂氮化镓,并且第二掺杂半导体材料包括p掺杂氮化镓。
在一些实施例中,半导体结构,该半导体结构包括来自未掺杂半导体材料的衬底和设置在衬底上的鳍。该鳍包括非极性顶面和两个相对的第一和第二极性侧壁表面,并由未掺杂半导体材料制成。半导体结构还包括位于第一极性侧壁表面上的极化层、位于极化层上的掺杂半导体层、位于掺杂半导体层和第二极性侧壁表面上的介电层,以及位于介电层和第一极性侧壁表面上的栅电极层。
在一些实施例中,未掺杂半导体材料包括氮化镓,并且第一极性侧壁表面平行于(0001)平面,第二极性侧壁表面平行于
Figure BDA0002214312770000211
平面,并且非极性顶面平行于
Figure BDA0002214312770000212
平面。在一些实施例中,未掺杂半导体材料包括氮化镓,并且第一极性侧壁表面平行于
Figure BDA0002214312770000213
平面,第二极性侧壁表面平行于(0001)平面,并且非极性顶面平行于
Figure BDA0002214312770000214
平面。在一些实施例中,极化层包括氮化铟或氮化铟镓,并且掺杂半导体层包括n掺杂氮化镓或p掺杂氮化镓。在一些实施例中,第一极性侧壁表面、极化层、掺杂半导体层、介电层和栅电极层形成遂穿场效应晶体管。在一些实施例中,极化层与鳍的第一极性侧壁表面之间的界面包括在5x1012/cm2和5x1014/cm2之间的范围内的绝对局部界面极化电荷密度。
在一些实施例中,电路包括finFET反相器结构和TFET。该finFET反相器结构包括第一鳍,该第一鳍具有两个相对的第一和第二极性侧壁表面;第一介电层,位于第一鳍的第一极性侧壁表面上;第二介电层,位于第一鳍的第二极性侧壁表面上;以及栅电极材料,位于第一和第二介电层上。该TFET包括第二鳍,该第二鳍具有两个相对的第一和第二极性侧壁表面;极化层,位于第二鳍的第一极性侧壁表面上;掺杂半导体层,位于极化层上;第三介电层,位于掺杂半导体层和第二鳍的第二极性侧壁表面上;以及栅电极材料,位于第三介电层上,第三介电层位于第二鳍的第一极性侧壁表面上。
在一些实施例中,掺杂半导体层包括n型掺杂氮化镓和p型掺杂氮化镓,并且第一介电层、第二介电层和第三介电层中的每个均包括氮化铝或氮化铝镓。在一些实施例中,第二鳍的第一极性侧壁表面包括n沟道遂穿鳍式场效应晶体管或p沟道遂穿鳍式场效应晶体管。在一些实施例中,第一鳍的第一极性侧壁表面包括n沟道鳍式场效应晶体管,并且第一鳍的第二极性侧壁表面包括p沟道鳍式场效应晶体管。
应当理解,具体实施方式而不是本发明的摘要部分旨在用于解释权利要求。本发明的摘要部分可阐述发明人所预期的本发明的一个或多个但不是所有可能的实施例,因此,并不旨在以任何方式限制所附权利要求。
上面概述了若干实施例的特征,使得本领域人员可以更好地理解本发明的方面。本领域人员应该理解,他们可以容易地使用本发明作为基础来设计或修改用于实施与本文所介绍实施例相同的目的和/或实现相同优势的其他工艺和结构。本领域技术人员也应该意识到,这种等同构造并不背离本发明的精神和范围,并且在不背离本发明的精神和范围的情况下,本文中他们可以做出多种变化、替换以及改变。

Claims (10)

1.一种半导体结构,包括:
鳍,包括非极性顶面和两个相对的第一极性侧壁表面和第二极性侧壁表面;
第一极性层,位于所述第一极性侧壁表面上;
第二极性层,位于所述第二极性侧壁表面上;以及
栅电极层,位于所述第一极性层和所述第二极性层上。
2.根据权利要求1所述的半导体结构,其中,所述第一极性侧壁表面和所述第二极性侧壁表面包括具有相反极性的局部界面极化电荷。
3.根据权利要求1所述的半导体结构,其中,所述第一极性层和所述第二极性层中的每个均包括具有相同或不同摩尔分数比的氮化铝或氮化铝镓。
4.根据权利要求1所述的半导体结构,其中,所述第一极性层和所述第二极性层中的每个均具有相同或不同的厚度。
5.根据权利要求1所述的半导体结构,其中,所述第一极性层和所述第二极性层的厚度在1nm和3nm之间。
6.根据权利要求1所述的半导体结构,其中,所述鳍包括未掺杂氮化镓,所述未掺杂氮化镓的高度在30nm和50nm之间并且宽度在8nm和10nm之间。
7.根据权利要求1所述的半导体结构,其中,所述第一极性侧壁表面、所述第一极性层和所述第一极性层上的所述栅电极层形成第一类型的场效应晶体管,并且所述第二极性侧壁表面、所述第二极性层和所述第二极性层上的所述第二栅电极层形成第二类型的场效应晶体管,所述第二类型的场效应晶体管与所述第一类型的场效应晶体管不同。
8.根据权利要求7所述的半导体结构,其中,第一类型的场效应晶体管是n型,并且第二类型的场效应晶体管是p型。
9.一种半导体结构,包括:
衬底,包括未掺杂半导体材料;
鳍,位于所述衬底上,并具有非极性顶面和两个相对的第一极性侧壁表面和第二极性侧壁表面,其中,所述鳍包括所述未掺杂半导体材料;
极化层,位于所述第一极性侧壁表面上;
掺杂半导体层,位于所述极化层上;
介电层,位于所述掺杂半导体层和所述第二极性侧壁表面上;以及
栅电极层,位于所述介电层和所述第一极性侧壁表面上。
10.一种半导体电路,包括:
鳍式场效应晶体管(finFET)反相器结构,包括:
第一鳍,具有两个相对的第一极性侧壁表面和第二极性侧壁表面;
第一介电层,位于所述第一鳍的所述第一极性侧壁表面上;
第二介电层,位于所述第一鳍的所述第二极性侧壁表面上;以及
栅电极材料,位于所述第一介电层和所述第二介电层上;以及遂穿鳍式场效应晶体管(TFET),包括:
第二鳍,具有两个相对的第一极性侧壁表面和第二极性侧壁表面;
极化层,位于所述第二鳍的所述第一极性侧壁表面上;
掺杂半导体层,位于所述极化层上;
第三介电层,位于所述掺杂半导体层和所述第二鳍的所述第二极性侧壁表面上;以及
所述栅电极材料,位于所述第三介电层上,所述第三介电层位于所述第二鳍的所述第一极性侧壁表面上。
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