TW202002293A - 半導體裝置 - Google Patents

半導體裝置 Download PDF

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TW202002293A
TW202002293A TW108112371A TW108112371A TW202002293A TW 202002293 A TW202002293 A TW 202002293A TW 108112371 A TW108112371 A TW 108112371A TW 108112371 A TW108112371 A TW 108112371A TW 202002293 A TW202002293 A TW 202002293A
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Taiwan
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layer
conductive
dielectric layer
source
channel layer
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TW108112371A
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English (en)
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綦振瀛
鄒承翰
陳仕鴻
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台灣積體電路製造股份有限公司
國立臺灣大學
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Publication of TW202002293A publication Critical patent/TW202002293A/zh

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Abstract

本揭露提供半導體接觸結構、包含半導體接觸結構的半導體裝置及其製造方法。在實施方式中，半導體裝置包含基板上的通道層；通道層上的介面層，其中介面層包含鈦(Ti)且接觸通道層；以及在介面層上的接觸金屬層，其中接觸金屬層包含鋁矽銅合金(AlSiCu)。

Description

半導體裝置
本揭露是關於一種半導體裝置。
半導體裝置用於各種電子應用，例如個人電腦、手機、數位相機和其他電子設備。通常通過在半導體基板上依序沉積絕緣或介電層、導電層和半導體材料層，並使用光刻微影來圖案化各種材料層，以在其上形成電路元件和部件，來製造半導體裝置。
半導體工業通過不斷縮小最小特徵尺寸，持續提高各種電子元件(例如電晶體、二極體、電阻、電容等)的積體密度，從而允許更多元件集積到給定區域中。但是，隨著最小特徵尺寸的縮小，出現了應該解決的其他問題。
根據部分實施方式，半導體裝置包含在基板上的通道層；通道層上的介面層，介面層包括鈦(Ti)，介面層與通道層接觸；介面層上的接觸金屬層，接觸金屬層包括鋁矽銅合金(AlSiCu)。
102‧‧‧基板
104‧‧‧緩衝層
106‧‧‧通道層
108‧‧‧第一介電層
110‧‧‧第一光阻
112‧‧‧離子注入製程
114‧‧‧源極/汲極區
115‧‧‧通道區
116‧‧‧第二介電層
118‧‧‧第二光阻
120‧‧‧閘極介電層
122‧‧‧金屬閘極
124‧‧‧第三介電層
126‧‧‧開口
128‧‧‧導電襯層
129‧‧‧導電層
130‧‧‧導電填充材料
根據以下詳細說明並配合閱讀附圖，使本揭露的態樣獲致較佳的理解。須注意的是，根據業界的標準作法，圖式的各種特徵並未按照比例繪示。事實上，為了進行清楚的討論，特徵的尺寸可以經過任意的縮放。
圖1繪示根據本揭露之部分實施方式之半導體基板的剖面示意圖。
圖2繪示根據本揭露之部分實施方式之形成介電層及圖案化光阻的剖面示意圖。
圖3繪示根據本揭露之部分實施方式之離子植入製程的剖面示意圖。
圖4繪示根據本揭露之部分實施方式之移除屏蔽層以及圖案化光阻的剖面示意圖。
圖5繪示根據本揭露之部分實施方式之形成硬式遮罩層與圖案化光阻的剖面示意圖。
圖6繪示根據本揭露之部分實施方式之蝕刻通道層以及緩衝層的剖面示意圖。
圖7繪示根據本揭露之部分實施方式之移除硬式遮罩層與圖案化光阻的剖面示意圖。
圖8繪示根據本揭露之部分實施方式之形成閘極介電層的剖面示意圖。
圖9繪示根據本揭露之部分實施方式之形成金屬閘極層的剖面示意圖。
圖10繪示根據本揭露之部分實施方式之形成金屬堆疊 的剖面示意圖。
圖11繪示根據本揭露之部分實施方式之形成層間介電層的剖面示意圖。
圖12A至圖12B繪示根據本揭露之部分實施方式之在層間介電層中形成開口的剖面示意圖。
圖13繪示根據本揭露之部分實施方式之形成導電襯層的剖面示意圖。
圖14繪示根據本揭露之部分實施方式之形成導電填充材料的剖面示意圖。
圖15A至圖15C繪示根據本揭露之部分實施方式之形成導電接觸的剖面示意圖。
圖16繪示根據本揭露之部分實施方式之包含導電接觸的電晶體的立體示意圖。
以下揭露提供許多實施方式或實施例，以實施所提供之發明標的的不同特徵。以下敘述之成份及排列方式的特定例示是為了簡化本揭露。這些當然僅是做為例示，其目的不在構成限制。舉例而言，第一特徵形成在第二特徵之上或上方的描述包含第一特徵及第二特徵有直接接觸的實施例，也包含有其他特徵形成在第一特徵與第二特徵之間，以致第一特徵及第二特徵沒有直接接觸的實施例。此外，在各種實施方式中，本揭露可重複相關元件符號以及/或用字。此重複僅為了簡單和清楚起見，並不表示所討論的各種 實施方式和/或配置之間的關係。
再者，空間相對性用語，例如「下方(beneath)」、「在...之下(below)」、「低於(lower)」、「在...之上(above)」、「高於(upper)」等，是為了易於描述圖式中所繪示的元素或特徵及其他元素或特徵的關係。空間相對性用語除了圖式中所描繪的方向外，還包含元件在使用或操作時的不同方向。裝置可以其他方式定向(旋轉90度或在其他方向)，而本文所用的空間相對性描述也可以如此解讀。
各種實施方式提供導電接觸，其可用於平面式金屬氧化物半導體場效電晶體(metal-oxide-semiconductor field-effect transistors；MOSFETs)、鰭式場效電晶體(field-effect transistors；FinFETs)、閘極全環場效電晶體(gate-all-around field-effect transistors；GAA FETs)或其相似物，以及其形成的製程。導電接觸可包含鈦(Ti)層以及鈦層上的鋁矽銅(AlSiCu)層。導電接觸可以與通道層接觸，其中通道層設置於過度層上，其中過度層設置於半導體基板上。通道層可包含砷化銦鎵(InGaAs)，緩衝層可以包含砷化銦鋁(InAlAs)，並且半導體基板可以包含磷化銦(InP)。根據本申請實施方式，導電接觸可以由與互補金屬氧化物半導體(complementary metal-oxide-semiconductor；CMOS)製造程序以及矽基的MOSFET製造程序兼容的材 料形成。因為本申請的導電接觸是無金的，所以降低了導電接觸的製造成本。此外，此導電接觸可以具有低的特徵接觸電阻(specific contact resistivity)並以提供歐姆接觸。此導電接觸可用於穿隧式場效電晶體(tunneling field-effect transistors；TFET)、平面金屬氧化物半導體場效電晶體(MOSFET)、鰭式場效電晶體(FinFET)、閘極全環場效電晶體(GAA FET)及其相似物。
參照圖1，基板102具有緩衝層104以及設置於其上的通道層106。基板102可包含半導體材料，且可以例如是塊狀矽晶圓、塊狀鍺晶圓、絕緣層上半導體(semiconductor-on-insulator；SOI)基板或應變絕緣層上半導體(strained semiconductor-on-insulator；SSOI)基板。基板102的半導體材料可包含第一半導體材料，例如四族元素，如鍺或矽。在部分實施方式中，基板102的半導體材料可包含磷化銦(InP)、矽鍺(SixGe(1-x))、矽(Si)、鍺(Ge)、碳化矽(SiC)、藍寶石(Al2O3)、其組合或相似物。基板102可以是多層的或梯度基板。
緩衝層104可由具有高電阻率的材料製成，且可用於將通道層106以及後續形成的電晶體隔絕於基板102以及基板102上的其他裝置。舉例而言，緩衝層104的電阻率可以大於大約105Ω．cm，例如大約106Ω．cm。緩衝層104的材料可例如為AlxGa(1-x)Sb、InxGa(1-x)As、InxGa(1-x)P、InxAl(1-x)As、InxGa(1-x)N、AlxGa(1-x)N、SixGe(1-x)、AlxSb(1-x)、GaxSb(1-x)、其合金、組合 或多個層體；或相似材料。在至少一實施方式中，緩衝層104可包含InAlAs。緩衝層104可藉由磊晶成長、化學氣相沉積(chemical vapor deposition；CVD)、其組合或任何適當的沉積製程形成於基板102上，磊晶成長可例如分子束磊晶(molecular beam epitaxy；MBE)、氣相磊晶(vapor-phase epitaxy；VPE)或液相磊晶(liquid-phase epitaxy；LPE)；化學氣相沉積可例如金屬有機化學氣相沉積(metalorganic CVD；MOCVD)、低壓化學氣相沉積(low pressure CVD；LPCVD)、原子層沉積(atomic layer deposition；ALD)、超高真空化學氣相沉積(ultrahigh vacuum CVD；UHVCVD)、減壓化學氣相沉積(reduced pressure CVD；RPCVD)。緩衝層104可具有大約0.5微米至大約2.0微米之間的厚度，例如大約0.6微米。
如下面將更詳細討論的，在各種實施方式中，通道層106的一部分可用於形成電晶體的通道。通道層106可以包含半導體材料，包含砷化銦鎵(InxGa(1-x)As)、磷化銦鎵(InxGa(1-x)P)、砷化銦鋁(InxAl(1-x)As)、氮化銦鎵(InxGa(1-x)N)、氮化鋁鎵(AlxGa(1-x)N)、矽鍺(SixGe(1-x))、砷化銦(InxAs(1-x))、其組合或多個層體等。通道層106可以通過磊晶生長(例如分子束磊晶、氣相磊晶或液相磊晶)或化學氣相沉積(例如金屬有機化學氣相沉積、低壓化學氣相沉積、原子層沉積、超高真空化學氣相沉積、減壓化學氣相沉積)、其組合或任何其他適 當沉積製程形成在基板102上。通道層106可具有小於大約200奈米的厚度，例如大約190奈米或大約167.9奈米，或小於大約100奈米的厚度，例如大約50奈米。
通道層106的材料可以是未摻雜的。在部分實施方式中，通道層106可以是輕微摻雜的(例如，通道層106可以具有小於大約1017cm-3的摻雜濃度)。舉例而言，在基板102上形成n型裝置的實施方式中，通道層106可以是輕微p型摻雜的。在基板102上形成p型裝置的實施方式中，通道層106可以是輕微n型摻雜的。可注入通道層106中的n型摻雜離子包含矽(Si)、鍺(Ge)、錫(Sn)等，且可注入通道層106中的p型摻雜劑離子包括鈹(Be)、鋅(Zn)、碳(C)等。
在至少一個實施方式中，基板102可以包含磷化銦(InP)，緩衝層104可以包含砷化銦鋁(InAlAs)，通道層106可以包括砷化銦鎵(InGaAs)。如此一來，基板102、緩衝層104和通道層106的材料可以是晶格匹配的。
在圖2中，在通道層106上形成第一介電層108和第一光阻110。第一介電層108可用於防止在後續離子注入期間(舉例而言，下面參考圖3描述的離子注入製程112)對下面的通道層106的損壞。第一介電層108可以由二氧化矽(SiO2)或相似物形成。可以使用諸如原子層沉積(ALD)、物理氣相沉積(physical vapor deposition；PVD)、化學氣相沉積(CVD)、其組合等的沉積製程來沉積第一介電層108。第一介電層108可具有介於大約10 奈米與大約50奈米之間的厚度，例如大約20奈米。
如圖2所示，然後在第一介電層108上形成第一光阻110。可以使用旋塗技術等沉積第一光阻110。可以使用圖案化的能量源(例如圖案化的光源、電子束(electron beam；e-beam)源等)對第一光阻110暴光，且將圖案化的第一光阻110暴露於顯影劑來圖案化第一光阻110。如圖2所示，可以第一光阻110可經圖案化而形成露出第一介電層108的開口。
在圖3中，在第一光阻110和第一介電層108上進行離子注入製程112。離子可以穿過第一介電層108並且可以注入通道層106中以形成源極/汲極區114。設置在源極/汲極區114之間的通道層106的部分可以形成通道區115。在基板102上形成n型裝置的實施方式中，離子注入製程112可以注入諸如矽(Si)、硒(Se)、錫(Sn)等的n型摻雜離子至通道層106。在基板102上形成p型裝置的實施方式中，離子注入製程112可以將諸如鈹(Be)、鋅(Zn)等的p型摻雜劑離子注入到通道層106中。
離子注入製程112可以使用大約7.5keV至大約37.5keV範圍內的能量進行，例如大約15keV或大約25keV，劑量範圍為大約5×1013離子/cm2至大約7.5×1014離子/cm2，例如大約1×1014離子/cm2或大約5×1014離子/cm2。離子注入製程112可以在大約500℃至大約800℃的溫度下進行。在部分實施方式中，通道層106暴露於離子注入製程112的區域中的摻雜濃度可以在大約2.0×1018cm-3 和大約6.2×1018cm-3之間的範圍內，例如大約4.1×1018cm-3。在至少一個實施方式中，可以在通道層106中注入矽，使得通道層的暴露部分中的矽離子濃度在大約1×1018cm-3和大約1×1020cm-3之間。
因此，使用離子注入製程112以形成源極/汲極區114。在離子注入製程112之後，與通道層106的未暴露部分相比，源極/汲極區114可具有增加的電子濃度和降低的接觸電阻。設置在源極/汲極區114之間的通道區115可以用作隨後形成的電晶體的通道。
在離子注入製程112之後，可以通過快速熱退火(rapid thermal annealing；RTA)製程(未單獨示出)激活注入的離子。快速熱退火製程可以在大約500℃至大約800℃的溫度下進行，例如大約650℃，持續大約5秒至大約100秒的時間，例如大約30秒。快速熱退火製程可以在氮氣(N2)周圍環境中進行。
在圖4中，在快速熱退火製程之後，從通道層106上方去除第一介電層108和第一光阻110。可以通過合適的蝕刻製程移除第一介電層108和第一光阻110。在部分實施方式中，蝕刻製程可以是各向同性蝕刻製程，例如濕法蝕刻製程或化學蝕刻製程。在其他實施方式中，蝕刻製程可以是各向異性蝕刻製程，例如乾蝕刻製程。在至少一個實施方式中，可以使用包括氫氟酸(HF)的蝕刻劑(例如稀釋的氫氟酸(diluted HF；dHF))通過濕蝕刻製程去除第一介電層108和第一光阻110。在稀釋的氫氟酸中，氫氟酸 可以以約1：10(HF：DIW)的比例在去離子水(deionized water；DIW)中稀釋。
在圖5中，在通道層106和源極/汲極區114上，形成第二介電層116和第二光阻118。第二介電層116可以是硬式遮罩層。第二介電層116可以由二氧化矽(SiO2)、氮化矽(SiN)、其組合或多個層體等形成。可以使用諸如原子層沉積、物理氣相沉積、化學氣相沉積(CVD)、其組合或相似的沉積製程，將第二介電層116沉積在通道層106和源極/汲極區114上。第二介電層116可具有介於大約20奈米與大約60奈米之間的厚度，例如大約40奈米。
第二光阻118可以採用旋塗技術等沉積在第二介電層116上。可以通過將第二光阻118暴露於圖案化的能量源(例如，圖案化的光源、電子束源等)並將圖案化的第二光阻118暴露於顯影劑來圖案化第二光阻118。如圖5所示，第二光阻118可以被圖案化以覆蓋源極/汲極區114以及在源極/汲極區114之間形成的溝道區。
在圖案化第二光阻118之後，可以通過在第二光阻118中形成的開口蝕刻第二介電層116。可以通過任何合適的蝕刻製程蝕刻第二介電層116，例如乾蝕刻製程。在部分實施方式中，可以通過乾蝕刻製程蝕刻第二介電層116，例如反應離子蝕刻(reactive-ion etching；RIE)、中性束蝕刻(neutral-beam etching；NBE)、其組合等。用於蝕刻第二介電層116的蝕刻製程可以是各向異性的。
在圖6中，蝕刻通道層106和緩衝層104。如圖 6所示，可以蝕刻通道層106，以保留源極/汲極區114和通道區115。可以使用任何合適的蝕刻製程來蝕刻通道層106和緩衝層104。蝕刻製程可以是各向異性蝕刻製程，例如乾蝕刻製程。在部分實施例中，通道層106和緩衝層104可以通過乾蝕刻製程蝕刻，例如反應離子蝕刻、中性束蝕刻、其組合等。可以通過與第二介電層116相同的蝕刻製程來蝕刻通道層106和緩衝層104，並且在部分實施方式中，可以同時蝕刻第二介電層116、通道層106和緩衝層104。
如圖6所示，緩衝層104的一部分可以維持在基板102上方，處於暴露於蝕刻製程的區域，且位於第二光阻118和第二介電層116覆蓋的區域之外。設置於第二光阻118覆蓋的區域之外的該緩衝層104的部分，可用於將隨後形成的裝置與在基板102上形成的其他裝置隔離。
在圖7中，移除通道層106上方的第二介電層116和第二光阻118。第二介電層116和第二光阻118可以通過與第一介電層108和第一光阻110相同的蝕刻製程或類似的蝕刻製程移除。用於移除第二介電層116和第二光阻118的蝕刻製程也可以用於清潔圖7中所示結構的表面並去除形成在圖7所示結構表面上的自然氧化物。舉例而言，使用包含氫氟酸的蝕刻劑(例如dHF)的濕蝕刻製程可用於去除第二介電層116、第二光阻118以及通道層106或緩衝層104上的形成的任何自然氧化物。在dHF中，氫氟酸可以在去離子水中以約1：10(HF：DIW)的比例稀釋。
在部分實施方式中，通道層106可以由鍺(Ge) 或其相似物形成。在通道層106包括鍺的實施例中，通道層106可以經受快速熱氧化製程，以在通道層106和緩衝層104的表面上形成共形氧化物層(未單獨示出)。此步驟可以是可選的。
然後，可以對通道層106和緩衝層104的表面進行電漿處理，例如氮氣電漿。氮氣電漿可用於氮化通道層106和緩衝層104的表面。此氮化通道層106和緩衝層104的表面的步驟減小了通道層106和緩衝層104之間的介面能態密度(interface state density)，並且隨後形成閘極介電層120(下面參考圖8討論)，改善通道層106與緩衝層104和閘極介電層120之間的介面。
在圖8中，在通道層106和緩衝層104上形成閘極介電層120。閘極介電層120可以是高k(介電常數)介電層，如HfO2、Al2O3、LaO2、TiO2、HfZrO、Ta2O3、HfSiO4、ZrO2、ZrSiO2、其組合或其他合適的材料。如圖8所示，可以通過共形沉積製程沉積閘極介電層120。舉例而言，可以通過化學氣相沉積、原子層磊晶等沉積閘極介電層120。閘極介電層120可具有介於大約2.5奈米與大約7.5奈米之間的厚度，例如大約5奈米。
在圖9中，在閘極介電層120上形成金屬閘極122。金屬閘極122可以由氮化鈦(TiN)形成。在部分實施方式中(未單獨示出)，金屬閘極122可以包含功函數調整層和在功函數調整層上形成的導電材料。功函數調整層可以由TiN、TSN、WN、WCN、AlN、TaAlC、TiAl、TiAlN、 WAlN、其他合適的材料或其組合形成。導電材料可以由W、Co、Ru、Al或其他合適的材料形成。金屬閘極122可以通過物理氣相沉積製程形成，例如濺射。金屬閘極122可具有介於大約37.5奈米與大約112.5奈米之間的厚度，例如大約75奈米。
在沉積金屬閘極122之後，所得結構可進行金屬後退火(post metal anneal；PMA)製程。金屬後退火製程可以在大約200℃至大約400℃的溫度下進行，例如大約300℃。金屬後退火製程可以在包含合成氣體(例如氮氣(N2)和氫氣(H2)的混合物)等的空氣中進行。金屬後退火製程通過減少閘極介電層120的介面附近的邊界陷阱來改善所得結構的特性。
在圖10中，移除金屬閘極122和閘極介電層120的部分，以形成閘極堆疊。閘極堆疊包括金屬閘極122和閘極介電層120。可以通過在金屬閘極122上沉積光阻(未單獨示出)、以圖案化的能量源(例如圖案化的光源、電子束源等)來對光阻曝光、使光阻顯影、並通過光阻蝕刻金屬閘極122和閘極介電層120，來圖案化閘極堆疊。可以通過乾蝕刻製程蝕刻金屬閘極122和閘極介電層120，例如反應離子蝕刻、中性束蝕刻、其組合或其他相似製程。用於蝕刻金屬閘極122和閘極介電層120的蝕刻製程可以是各向異性的。
在圖11中，在閘極堆疊、通道層106和緩衝層104上，形成第三介電層124。第三介電層124可以是層間 介電(inter-layer dielectric；ILD)層。第三介電層124可以由具有低介電常數的介電材料(例如，低k材料)形成。舉例而言，第三介電層124可以由二氧化矽(SiO2)、氮化矽(Si3N4)、其組合或多個層體等形成。可以使用共形沉積製程來沉積第三介電層124，例如原子層沉積、物理氣相沉積、化學氣相沉積、其組合或相似製程。第三介電層124可具有介於大約40奈米與大約120奈米之間的厚度，例如大約80奈米。
在圖12A中，在第三介電層124中，形成開口126。開口126可以延伸穿過第三介電層124以露出部分的源極/汲極區114。可以在第三介電層124上沉積光阻(未單獨示出)、以圖案化能量源(例如圖案化光源、電子束源等)對光阻曝光、使光阻顯影、並通過光阻蝕刻第三介電層124，而形成開口126。可以通過乾蝕刻製程蝕刻第三介電層124，例如反應離子蝕刻、中性束蝕刻、其組合或其他相似製程。用於蝕刻第三介電層124的蝕刻製程可以是各向異性的。開口126可以具有介於大約1微米和大約3微米之間的寬度W1，例如大約2微米。開口126還可具有介於大約1.5微米和大約4.5微米之間的長度(未單獨示出)，例如大約3微米。
如圖12B所示，在部分實施方式中，開口126可具有傾斜側壁(tapered sidewalls)。在其他實施方式中，開口126的側壁可以是反向傾斜的(reverse tapered)、具有彎曲的側壁等。開口126可以在俯視圖中具有正方形形 狀、矩形形狀、圓形形狀、橢圓形形狀等。
在圖13中，在第三介電層124上和開口126中，沉積導電襯層128。導電襯層128可包含導電材料，例如鈦(Ti)。可以通過共形沉積製程沉積導電襯層128。舉例而言，導電襯層128可以通過物理氣相沉積製程沉積，例如濺射。導電襯層128可具有介於大約0.1奈米與大約100奈米之間的厚度，例如大約10奈米或大約16.94奈米。
在圖14中，在導電襯層128上，沉積導電填充材料130。導電填充材料130可填充開口126的其餘部分，如圖14所示。導電填充材料130可包含導電材料，如鋁矽銅(AlSiCu)。可以通過共形沉積製程來沉積導電填充材料130。舉例而言，導電填充材料130可以通過物理氣相沉積製程沉積，例如濺射。導電填充材料130可具有介於大約0.1奈米與大約1000奈米之間的厚度，例如大約200奈米或大約115.20奈米。
在部分實施方式中，導電填充材料130可以由AlSiCu形成，其具有式Al(1-x-y)SixCuy，其中x在大約1原子百分比和大約2原子百分比之間，y在大約0.5原子百分比和大約4原子百分比之間。在其他實施方案中，x大約為0原子百分比，y大約為0.5原子百分比至約4原子百分比。增加導電填充材料130中的銅濃度可降低填充材料130的電阻率，同時降低導電填充材料130的熱穩定性。同樣，增加導電填充材料130中的矽濃度可增加填充材料130的電阻率，同時增加導電填充材料130的熱穩定性。
更進一步的實施例可以包含附加導電層(圖15C中示為導電層129)，例如鎳(Ni)層或其他導電材料的層體，該附加導電層設置在導電襯層128和導電填充材料130。可以通過共形沉積製程而沉積該附加導電層。舉例而言，可以通過物理氣相沉積製程沉積附加導電層，例如濺射。此附加導電層可具有介於大約0.1奈米和大約100奈米之間的厚度。附加導電層可以增加隨後形成的源極/汲極接觸的熱穩定性(下面參考圖15C討論)。
在圖15A中，移除導電襯層128和導電填充材料130的部分，以形成源極/汲極接觸。源極/汲極接觸包含導電襯層和導電填充材料(在部分實施方式中，還包含附加導電層)。可以通過在導電填充材料130上沉積光阻(未單獨示出)、以圖案化能量源(例如圖案化光源、電子束源等)對光阻曝光、顯影光阻、通過光阻蝕刻導電填充材料130和導電襯層128，來圖案化源極/汲極接觸。導電填充材料130和導電襯層128可以通過乾蝕刻製程蝕刻，例如反應離子蝕刻、中性束蝕刻、其組合等。用於蝕刻導電填充材料130和導電襯層128的蝕刻製程可以是各向異性的。
源極/汲極接觸可能具有低接觸電阻。舉例而言，源極/汲極接觸可以具有介於大約0.0195Ω．mm和大約0.0585Ω．mm之間的接觸電阻，例如大約0.039Ω．mm。源極/汲極接觸還可以具有低的特徵接觸電阻率。舉例而言，源極/汲極接觸可以具有在大約1.425×10-7Ω．cm2和大約4.275×10-7Ω．cm2之間的特徵接觸電阻率，例如大約2.85 ×10-7Ω．cm2。如圖15A所示，源極/汲極接觸的上部分(例如設置在第三介電層124上方的源極/汲極接觸的部分)，可以具有大於開口126的寬度W1的寬度。如上所述，源極/汲極接觸的上部分還可以具有大於開口126的長度的長度(未單獨示出)。
在部分實施例中，在形成導電襯層128和導電填充材料130之前，可不沉積第三介電層124，且可以將導電襯層128和導電填充材料130直接沉積在源極/汲極區114上。在這些實施方式中，可以蝕刻導電襯層128和導電填充材料130，以形成源極/汲極接觸，並且可以在源極/汲極接觸周圍，沉積層間介電層。在更進一步的實施方式中，源極/汲極接觸還可以包括沉積在導電填充材料上的一層或多層鉑(Pt)。
如圖15B所示，包括導電襯層128和導電填充材料130的源極/汲極接觸可以具有任何合適的形狀，例如在延伸穿過第三介電層124的區域中具有錐形形狀。在各種其他實施方式中，延伸穿過第三介電層124的源極/汲極接觸部分可以具有倒錐形形狀、彎曲側壁等。在第三介電層124上方延伸的源極/汲極接觸的頂部分可以具有圓角、傾斜側壁、彎曲側壁、反向傾斜側壁等。此外，源極/汲極接觸的頂部可以在俯視圖中具有任何合適的形狀，例如正方形、矩形、圓形、橢圓形等。
如圖15C所示，源極/汲極接觸還可以包含設置在導電填充材料130和導電襯層128之間的導電層129。導 電層129可以由鎳(Ni)或類似材料形成。導電層129可以具有介於大約0.1奈米和大約100奈米之間的厚度，並且可以增加源極/汲極接觸的熱穩定性。
圖16示出了圖15A的電晶體結構的立體圖。如圖16所示，電晶體結構包括基板102、基板102上方的緩衝層104、緩衝層104上方的通道層106(包含源極/汲極區114和通道區115)、通道層106上方的閘極堆疊(包括閘極介電層120和金屬閘極122)。第三介電層124在緩衝層104的頂表面上延伸，並沿著緩衝層104、通道層106和閘極堆疊的側壁延伸。源極/汲極接觸包括導電襯層128和導電填充材料130，源極/汲極接觸延伸穿過第三介電層以接觸源極/汲極區114。
根據上述實施方式，形成半導體裝置，產生無金(無Au)、低特徵接觸電阻率的源極/汲極接觸，其可以與InGaAs半導體材料一起使用。因為源極/汲極接觸是無金的，所以降低了接觸的製造成本。此外，由於鈦和鋁矽銅是矽基製造技術中常用的材料，上述源極/汲極接觸可以與現有的製造技術整合(例如，源極/汲極接觸可以與矽MOSFET)技術、CMOS技術等兼容)。源極/汲極接觸可以具有低的特徵接觸電阻率，並且在形成源極/汲極接觸之後，可以不需要金屬後退火。
根據部分實施方式，半導體裝置包含在基板上的通道層；通道層上的介面層，介面層包括鈦(Ti)，介面層與通道層接觸；介面層上的接觸金屬層，接觸金屬層包括 鋁矽銅合金(AlSiCu)。在一實施方式中，通道層包含砷化銦鎵(InGaAs)。在一實施方式中，通道層包括砷化銦(InAs)、磷化銦鎵(InGaP)、砷化銦鋁(InAlAs)，氮化鎵(GaN)、氮化銦鎵(InGaN)、氮化鋁鎵(AlGaN)或矽鍺(SiGe)。在一個實施方式中，基板包括磷化銦(InP)。在一個實施方式中，基板包括矽鍺(SiGe)、砷化鎵(GaAs)、矽(Si)、鍺(Ge)、碳化矽(SiC)或藍寶石(Al2O3)。在一個實施方式中，接觸金屬層的材料由式Al(1-x-y)SixCuy表示，x為大約1原子百分比至大約2原子百分比，y在大約0.5原子百分比至大約4原子百分比之間。在一實施方式中，接觸金屬層的材料由式Al(1-x-y)SixCuy表示，x為大約0原子百分比，y在大約0.5原子百分比至大約4原子百分比之間。
根據另一實施方式，一種半導體裝置包含基板；基板上方的緩衝層；緩衝層上的通道層；導電接觸與通道層接觸，導電接觸包括導電襯層和導電填充材料，導電襯層包含鈦(Ti)，導電填充材料包括鋁矽銅合金(AlSiCu)。在一個實施方式中，半導體裝置還包含在通道層上方的閘極堆疊，閘極堆疊包括閘極介電層和閘極電極。在一個實施方式中，閘極介電層包括氧化鋁(Al2O3)，閘極包括氮化鈦(TiN)。在一個實施方式中，通道層包含在閘極堆疊的第一側上的第一源極/汲極區，第一源極/汲極區摻雜有矽(Si)摻雜物，並且導電接觸與第一源極/汲極區接觸。在一個實施方式中，第一源極/汲極區的該矽摻雜物的摻雜濃度在 1x1018cm-3至1x1020cm-3之間。在一個實施方式中，基板包括磷化銦(InP)，緩衝層包括砷化銦鋁(InAlAs)，通道層包括砷化銦鎵(InGaAs)。在一個實施方式中，導電襯層的厚度在0.1奈米和100奈米之間，導電填充材料的厚度在0.1奈米和1000奈米之間。
根據又一實施方式，一種方法包括在基板上形成通道層；在通道層上形成閘極堆疊；在通道層和閘極堆疊上形成層間介電層；在層間介電層中形成開口，以露出通道層；以及在開口中形成導電接觸，導電接觸包括導電襯層和導電填充材料，導電襯層包括鈦(Ti)，導電填充材料包括鋁矽銅合金(AlSiCu)。在一個實施方式中，形成導電接觸包含在開口中沉積導電襯層；以及在導電襯層上沉積導電填充材料，導電襯層和導電填充材料填滿開口。在一個實施方式中，通過濺射方式沉積導電襯層和導電填充材料。在一個實施方式中，導電襯層的厚度在0.1奈米和100奈米之間，導電填充材料的厚度在0.1奈米和1000奈米之間。在一個實施方式中，該方法還包括在基板上形成緩衝層，其中通道層是形成在緩衝層上，通道層包括砷化銦鎵(InGaAs)，緩衝層包括砷化銦鋁(InAlAs)。在一個實施方式中，層間介電層包括二氧化矽(SiO2)。
上述摘要了許多實施方式或實施例的特徵，以使所屬技術領域中具有通常知識者能了解本揭露的多個態樣。所屬技術領域中具有通常知識者應理解，在本揭露的基礎上，可設計或修飾其他製程及結構，以達到與這些實施方 式或實施例中相同的目的及/或實現相同的優點。所屬技術領域具有通常知識者也應了解，上述均等的架構並未脫離本揭露的精神及範圍，且在不脫離本揭露的精神及範圍下，可做出各種改變、替換及取代。
102‧‧‧基板
104‧‧‧緩衝層
106‧‧‧通道層
114‧‧‧源極/汲極區
115‧‧‧通道區
120‧‧‧閘極介電層
122‧‧‧金屬閘極
124‧‧‧第三介電層
128‧‧‧導電襯層
130‧‧‧導電填充材料

Claims (1)

  1. 一種半導體裝置，包含：一通道層，位於一基板上；一介面層，位於該通道層上，其中該介面層包含鈦(Ti)且接觸該通道層；以及一接觸金屬層，位於該介面層上，其中該接觸金屬層包含鋁矽銅合金(AlSiCu)。
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