CN110957361A - 半导体器件及其形成方法 - Google Patents

半导体器件及其形成方法 Download PDF

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Publication number
CN110957361A
CN110957361A CN201811124624.9A CN201811124624A CN110957361A CN 110957361 A CN110957361 A CN 110957361A CN 201811124624 A CN201811124624 A CN 201811124624A CN 110957361 A CN110957361 A CN 110957361A
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side wall
forming
layer
fin
fin part
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CN201811124624.9A
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CN110957361B (zh
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周飞
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Priority to CN201811124624.9A priority Critical patent/CN110957361B/zh
Priority to US16/536,766 priority patent/US11063052B2/en
Publication of CN110957361A publication Critical patent/CN110957361A/zh
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Abstract

一种半导体器件及其形成方法，方法包括：提供衬底，所述衬底上具有相邻的第一鳍部和第二鳍部，所述第一鳍部具有相对的第一侧壁和第二侧壁，第一侧壁朝向第二鳍部，所述衬底上还具有覆盖第一鳍部和第二鳍部部分侧壁的隔离层，且所述隔离层表面低于第一鳍部顶部表面和第二鳍部顶部表面；在第一鳍部的第一侧壁表面形成第一侧墙；形成第一侧墙后，在第一鳍部内形成第一掺杂层，所述第一侧墙覆盖第一掺杂层部分侧壁；在第二鳍部内形成第二掺杂层。所述方法提高了半导体器件的性能。

Description

半导体器件及其形成方法
技术领域
本发明涉及半导体制造领域，尤其涉及一种半导体器件及其形成方法。
背景技术
随着半导体制造技术的飞速发展，半导体器件朝着更高的元件密度，以及更高的集成度的方向发展。器件作为最基本的半导体器件，目前正被广泛应用，传统的平面器件对沟道电流的控制能力变弱，产生短沟道效应而导致漏电流，最终影响半导体器件的电学性能。
为了克服器件的短沟道效应，抑制漏电流，现有技术提出了鳍式场效应晶体管(Fin FET)，鳍式场效应晶体管是一种常见的多栅器件，鳍式场效应晶体管的结构包括：位于衬底表面的鳍部和隔离层，所述隔离层覆盖部分所述鳍部的侧壁，且隔离层表面低于鳍部顶部；位于隔离层表面，以及鳍部的顶部和侧壁表面的栅极结构；位于所述栅极结构两侧的鳍部内的源区和漏区。
然而，现有技术形成的半导体器件的性能较差。
发明内容
本发明解决的技术问题是提供一种半导体器件及其形成方法，以提高半导体器件的性能。
为解决上述技术问题，本发明提供一种半导体器件的形成方法，包括：提供衬底，所述衬底上具有相邻的第一鳍部和第二鳍部，所述第一鳍部具有相对的第一侧壁和第二侧壁，第一侧壁朝向第二鳍部，所述衬底上还具有覆盖第一鳍部和第二鳍部部分侧壁的隔离层，且所述隔离层表面低于第一鳍部顶部表面和第二鳍部顶部表面；在第一鳍部的第一侧壁表面形成第一侧墙；形成第一侧墙后，在第一鳍部内形成第一掺杂层，所述第一侧墙覆盖第一掺杂层部分侧壁；在第二鳍部内形成第二掺杂层。
可选的，所述第二鳍部具有相对的第三侧壁和第四侧壁，所述第三侧壁朝向第一鳍部；所述半导体器件的形成方法还包括：在第二鳍部的第四侧壁形成第二侧墙；在第二鳍部内形成第二掺杂层，所述第二侧墙覆盖第二掺杂层部分侧壁。
可选的，形成所述第一侧墙后，形成第二侧墙；形成所述第二侧墙后，形成所述第一侧墙。
可选的，形成所述第一侧墙过程中形成所述第二侧墙。
可选的，所述第一侧墙和第二侧墙的形成方法包括：在衬底上形成侧墙材料层，所述侧墙材料层覆盖第一鳍部顶部和侧壁以及第二鳍部顶部和侧壁；对所述第一鳍部第二侧壁的侧墙材料层和第二鳍部第三侧壁的所述侧墙材料层进行改性处理，使得位于第一鳍部第二侧壁和位于第二鳍部的第三侧壁的侧墙材料层具有掺杂离子，所述具有掺杂离子的侧墙材料层和无掺杂的侧墙材料层的刻蚀选择比不同；回刻蚀所述侧墙材料层，直至暴露出第一鳍部和第二鳍部顶部表面，在第一鳍部第一侧壁形成第一侧墙，在第一鳍部第二侧壁形成第一改性层，在第二鳍部第四侧壁形成第二侧墙，在第二鳍部第三侧壁形成第二改性层，所述第一改性层和第二改性层内具有掺杂离子；去除所述第一改性层和所述第二改性层，在第一鳍部第一侧壁形成所述第一侧墙，在第二鳍部第四侧壁形成所述第二侧墙。
可选的，所述第一侧墙和第二侧墙的形成方法包括：在第一鳍部侧壁形成初始第一侧墙；在第二鳍部侧壁形成初始第二侧墙；对第一鳍部第二侧壁的初始第一侧墙和第二鳍部第四侧壁的初始第二侧墙进行改性处理，分别在第一鳍部第二侧壁和第二鳍部第四侧壁形成第一改性层和第二改性层，所述第一改性层和第二改性层内具有掺杂离子，所述第一改性层和第二改性层和初始第一侧墙和初始第二侧墙的刻蚀选择比不同；去除所述第一改性层和所述第二改性层，在第一鳍部第一侧壁形成所述第一侧墙，在第二鳍部第四侧壁形成所述第二侧墙。
可选的，所述初始第一侧墙和初始第二侧墙的形成方法包括：在衬底上形成侧墙材料层，所述侧墙材料层覆盖第一鳍部顶部和侧壁以及第二鳍部顶部和侧壁；回刻蚀所述侧墙材料层，在第一鳍部侧壁形成初始第一侧墙，在第二鳍部侧壁形成初始第二侧墙。
可选的，所述第一侧墙的形成方法包括：在第二鳍部上形成保护层，所述保护层覆盖第二鳍部顶部和侧壁；形成保护层后，在第一鳍部和保护层上形成侧墙材料层，所述侧墙材料层覆盖第一鳍部顶部和侧壁；对所述第一鳍部第二侧壁的侧墙材料层进行改性处理，使得位于第一鳍部第二侧壁的侧墙材料层具有掺杂离子，所述具有掺杂离子的侧墙材料层和无掺杂的侧墙材料层的刻蚀选择比不同；回刻蚀所述侧墙材料层，直至暴露出第一鳍部顶部表面，在第一鳍部第一侧壁形成第一侧墙，在第一鳍部第二侧壁形成第一改性层，所述第一改性层内具有掺杂离子；去除所述第一改性层，在第一鳍部第一侧壁形成所述第一侧墙。
可选的，所述改性处理为离子掺杂工艺。
可选的，所述掺杂离子包括：氩离子或硅离子。
可选的，所述离子掺杂工艺包括离子注入工艺；所述离子注入工艺的参数包括：所述注入离子为氩离子或者硅离子，所述注入离子的剂量为1.0E14atom/cm2～1.0E17atom/cm2。
可选的，去除所述第一改性层和第二改性层的工艺包括：干法刻蚀工艺或者湿法刻蚀工艺。
可选的，所述湿法刻蚀工艺的参数包括：磷酸的体积百分比浓度为70％～95％，工艺温度为90摄氏度～150摄氏度。
可选的，所述第一掺杂层的形成方法包括：在第一鳍部内形成第一凹槽；在第一凹槽内外延形成第一掺杂层。
可选的，所述第一凹槽的形成方法包括：去除第一改性层前，去除第一侧墙和第一改性层之间的第一鳍部形成初始第一凹槽；去除所述初始第一凹槽侧壁的第一改性层，形成第一凹槽。
可选的，所述第二掺杂层的形成方法包括：在第二鳍部内形成第二凹槽；在第二凹槽内外延形成第二掺杂层。
可选的，所述第二凹槽的形成方法包括：去除第二改性层前，去除第二侧墙和第二改性层之间的第二鳍部形成初始第二凹槽；去除初始第二凹槽侧壁的第二改性层，形成第二凹槽。
可选的，形成所述第一掺杂层后，形成所述第二掺杂层；形成所述第二掺杂层后，形成所述第一掺杂层。
可选的，形成所述第一掺杂层过程中形成所述第二掺杂层。
相应的，本发明还提供一种采用上述任一项方法所形成的半导体器件，包括：衬底，所述衬底上具有相邻的第一鳍部和第二鳍部，所述第一鳍部具有相对的第一侧壁和第二侧壁，第一侧壁朝向第二鳍部，所述衬底上还具有覆盖第一鳍部和第二鳍部部分侧壁的隔离层，且所述隔离层表面低于第一鳍部顶部表面和第二鳍部顶部表面；位于第一鳍部的第一侧壁表面的第一侧墙；位于第一鳍部内的第一掺杂层，所述第一侧墙覆盖第一掺杂层部分侧壁；位于第二鳍部内的第二掺杂层。
与现有技术相比，本发明实施例的技术方案具有以下有益效果：
本发明技术方案提供的半导体器件的形成方法中，第一侧墙位于第一鳍部第一侧壁，第一侧壁朝向第二鳍部；在第一鳍部内形成第一掺杂层，在第二鳍部内形成第二掺杂层；第一侧墙位于第一掺杂层和第二掺杂层之间，将第一掺杂层和第二掺杂层隔离，避免第一掺杂层和第二掺杂层发生桥接。在相邻鳍部间距离一定的情况下，相邻的第一掺杂层和第二掺杂层可以实现体积较大且不会发生桥接，相应的第一掺杂层和第二掺杂层表面积也较大。由于后续制程中形成的插塞与第一掺杂层或第二掺杂层的接触为全覆盖式接触，即插塞全覆盖第一掺杂层或者第二掺杂层的表面，第一掺杂层或第二掺杂层表面积较大，与的插塞的接触面积相应较大，能够降低所形成的晶体管的接触电阻，从而提高器件的性能。
进一步的，在第二鳍部的第四侧壁形成第二侧墙，在第二鳍部内形成第二掺杂层；则可以防止第二掺杂层与第二鳍部的第四侧壁朝向所的相邻鳍部内形成的掺杂层与第二掺杂层发生桥接，从而提高器件的性能。
附图说明
图1至图2是一种半导体器件形成过程的结构示意图；
图3至图11是本发明一实施例中半导体器件形成过程的结构示意图。
具体实施方式
正如背景技术所述，现有技术的半导体器件的性能较差。
一种SRAM器件的形成方法，请参考图1和图2，图2为沿图1中切割线A-a的截面示意图，包括：提供衬底100，衬底100上具有相邻的第一鳍部110和第二鳍部111、以及覆盖第一鳍部110部分侧壁和第二鳍部111部分侧壁的隔离层101；在隔离层上形成横跨第一鳍部110的第一栅极结构130；在第一栅极结构130两侧的第一鳍部110中形成第一源漏掺杂层150；在隔离层上形成横跨第二鳍部111的第二栅极结构140；在第二栅极结构140两侧的第二鳍部111中形成第二源漏掺杂层160，第二源漏掺杂层160和第一源漏掺杂层150相邻。
然而，上述方法形成的SRAM存储器的性能较差，当所述第一栅极结构用于形成上拉晶体管时，所述晶体管的类型为P型，所述第一源漏掺杂层150由于不同晶向的生长速度不同，在<111>晶向上生长最慢，外延晶面会停止在(111)晶面上，而在其他面上会继续生长，从而形成尖端。相应的当第二栅极结构也用于形成上拉晶体管时，第二源漏掺杂层160也会形成尖端。随着半导体器件向着高密集度发展，组成半导体器件的晶体管之间的距离也越来越小，第二源漏掺杂层160和第一源漏掺杂层150之间的空间越来越小，为避免第一源漏掺杂层150与第二源漏掺杂层发生桥接，分别在第一源漏掺杂层150和第二源漏掺杂层160侧壁形成第一侧墙121和第二侧墙122，第一侧墙121和第二侧墙122分别限制第一源漏掺杂层150和第二源漏掺杂层160的形状，使得第一源漏掺杂层250和第二源漏掺杂层160的表面在不易形成尖端，从而不易发生桥接。
然而由于第一侧墙和第二侧墙的限制，第一源漏掺杂层150和第二源漏掺杂层160的体积较小，相应的表面积较小，后续形成的插塞和第一源漏掺杂层150或第二源漏掺杂层160之间的接触电阻较大，进而影响所形成的SRAM器件的性能。
为了解决上述技术问题，本发明技术方案通过在第一鳍部侧壁一侧形成第一侧墙；在第二鳍部同一侧形成第二侧墙；在第一鳍部和第二鳍部内分别形成第一掺杂层和第二掺杂层，第一掺杂层一侧受到第一侧墙限制，不易形成尖端，第一掺杂层不受第一侧墙限制的一侧不受第一侧墙限制形成的体积较大，从而使得第一掺杂层和第二掺杂层之间的距离相对增大，减小了二者之间相连的概率，从而提高了器件的性能。
为使本发明的上述目的、特征和优点能够更为明显易懂，下面结合附图对本发明的具体实施例做详细的说明。
图3至图11是本发明一实施例中半导体器件形成过程的结构示意图。
请参考图3和图4，图4中I区为图3沿M-M1方向的剖面图，图4中对II区为图3沿M2-M3方向的剖面图，提供衬底200。
所述衬底200包括第一区域I和第二区域II，所述第一区域I的衬底200上具有第一鳍部211，所述第二区域II的衬底200上具有第二鳍部212，所述第一鳍部具有相对的第一侧壁和第二侧壁，第一侧壁朝向第二鳍部所述第二鳍部具有相对的第三侧壁和第四侧壁，所述第三侧壁朝向第一鳍部。所述衬底200上还具有隔离层201，所述隔离层201覆盖第一鳍部211和第二鳍部212部分侧壁。
所述第一区域I和第二区域II所形成的半导体器件的类型可以相同，也可以不同。
所述第一区域I和第二区域II所形成的半导体器件的类型不同时，所述第一区域I用于形成P型器件时，第二区域II用于形成N型器件，所述第一区域I用于形成N型器件时，所述第二区域II用于形成P型器件。
本实施例中，所述第一区域I和第二区域II所形成的半导体器件的类型相同，均用于形成N型鳍式场效应晶体管。
所述衬底200的材料包括硅、锗、锗化硅、砷化镓、铟镓砷等半导体材料，其中硅材料包括单晶硅、多晶硅或非晶硅。所述衬底200还能够是绝缘体上半导体结构，所述绝缘体上半导体结构包括绝缘体及位于绝缘体上的半导体材料层，所述半导体材料层的材料包括硅、锗、锗化硅、砷化镓、铟镓砷等半导体材料。
本实施例中，所述衬底200的材料为单晶硅。
本实施例中，所述第一鳍部211和第二鳍部212通过图形化所述衬底200而形成。在其它实施例中，可以是：在所述衬底上形成鳍部材料层，然后图形化所述鳍部材料层，从而形成所述第一鳍部211和第二鳍部212。
本实施例中，所述第一鳍部211和第二鳍部212的材料为单晶硅。在其它实施例中，所述第一鳍部211和第二鳍部212的材料为单晶锗硅或者其它半导体材料。
所述隔离层201的形成步骤包括：在所述衬底200上形成初始隔离膜(未图示)，所述初始隔离膜覆盖所述第一鳍部211和第二鳍部212的顶部表面；平坦化所述初始隔离膜，直至露出第一鳍部211和第二鳍部212顶部的表面；回刻蚀所述初始隔离膜，暴露出所述第一鳍部211和第二鳍部212的部分侧壁，形成隔离层201。所述隔离层201用于电学隔离第一鳍部211和第二鳍部212。
所述初始隔离膜的材料包括氧化硅或氮化硅。
本实施例中，所述隔离层201的材料为氧化硅。
请参考图5，图5和图4剖面方向一致，在所述衬底200第一区域I上形成横跨第一鳍部211的第一栅极结构221，第一栅极结构221横跨第一鳍部211且覆盖第一鳍部211的部分顶部表面和部分侧壁表面；在衬底200第二区域II上形成横跨第二鳍部212的第二栅极结构222，第二栅极结构222横跨第二鳍部212且覆盖第二鳍部212的部分顶部表面和部分侧壁表面。
本实施例中，第一栅极结构221包括横跨第一鳍部211的第一栅介质层、位于第一栅介质层上的第一栅电极层以及位于第一栅电极层顶部的第一栅保护层。第二栅极结构222包括横跨第二鳍部212的第二栅介质层、位于栅介质层上的第二栅电极层以及位于第二栅电极层顶部的第二栅保护层。其他实施例中，不形成第一栅保护层和第二栅保护层。
本实施例中，第一栅介质层和第二栅介质层的材料为氧化硅，所述第一栅电极层和第二栅电极层的材料为多晶硅。所述第一栅保护层和第二栅保护层的材料为氮化硅、氮氧化硅、碳氧化硅、碳氮化硅或碳氮氧化硅。
本实施例中，所述第一栅极结构221和第二栅极结构222作为伪栅结构，后续会形成高K金属栅来替代伪栅结构。其他实施例中，所述第一栅极结构221和第二栅极结构222作为器件的栅极结构。
继续参考图5，形成第一栅极结构221和第二栅极结构222后，在第一栅极结构221的侧壁形成第一偏移侧墙231，在第二栅极结构222的侧壁形成第二偏移侧墙232。
所述第一偏移侧墙231保护所述第一栅极层侧壁，第二偏移侧墙232保护第二栅极层侧壁。
所述第一偏移侧墙231和第二偏移侧墙232的形成方法包括：在所述隔离层201第一鳍部211、第一栅极结构221、第二鳍部212和第二栅极结构222上形成第一偏移侧墙材料层，所述第一偏移侧墙材料层覆盖所述第一鳍部211的部分侧壁表面和部分顶部表面、所述第一栅极结构221的侧壁和顶部表面、第二鳍部212的部分侧壁表面和部分顶部表面以及所述第二栅极结构222的侧壁和顶部表面；回刻蚀所述第一偏移侧墙材料层，直至暴露出所述第一鳍部211、第二鳍部212、第一栅保护层和第二栅保护层的顶部表面，在第一鳍部211上形成覆盖于所述第一栅极结构221侧壁的第一偏移侧墙231，在第二鳍部212上形成覆盖于所述第二栅极结构222侧壁的第二偏移侧墙232。
所述第一偏移侧墙材料层的形成工艺为化学气相沉积工艺、物理气相沉积工艺或原子层沉积工艺中的一种或多种组合。
所述第一偏移侧墙材料层的材料包括氧化硅、氮化硅、氮氧化硅、碳氧化硅、碳氮化硅或碳氮氧化硅。
本实施例中，所述第一偏移侧墙材料层的形成工艺为化学气相沉积工艺。所述第一偏移侧墙231和第二偏移侧墙232的材料为氮化硅。
在第一鳍部的第一侧壁表面形成第一侧墙。
在一实施例中，所述第一侧墙的形成方法包括：在第二鳍部上形成保护层，所述保护层覆盖第二鳍部顶部和侧壁；形成保护层后，在第一鳍部和保护层上形成侧墙材料层，所述侧墙材料层覆盖第一鳍部顶部和侧壁；对所述第一鳍部第二侧壁的侧墙材料层进行改性处理，使得位于第一鳍部第二侧壁的侧墙材料层具有掺杂离子，所述具有掺杂离子的侧墙材料层和无掺杂的侧墙材料层的刻蚀选择比不同；回刻蚀所述侧墙材料层，直至暴露出第一鳍部顶部表面，在第一鳍部侧壁形成相对的第一侧墙和第一改性层，所述第一改性层内具有掺杂离子；去除所述第一改性层，在第一鳍部第一侧壁形成所述第一侧墙。
本实施例中，还包括：在第二鳍部的第四侧壁形成第二侧墙。
在一实施例中，形成所述第一侧墙后，形成第二侧墙。
在另一实施例中，形成所述第二侧墙后，形成所述第一侧墙。
当第一区域I和第二区域II所形成的器件类型不同时，所述第一侧墙和第二侧墙不同时形成。
本实施例中，形成所述第一侧墙的过程中形成所述第二侧墙。
参考图6和图7，图6与图5剖面方向一致，图7为图6沿N-N1方向的剖面图，形成第一偏移侧墙231和第二偏移侧墙232之后，在所述隔离层201第一鳍部211、第一栅极结构221、第二鳍部212和第二栅极结构222上形成侧墙材料层240。
所述侧墙材料层240为后续形成第一侧墙和第二侧墙提供材料层，且决定了后续形成的源漏掺杂层的位置。
当第一区域I和第二区域II所形成的器件不同，第一区域I和第二区域II的源漏掺杂层的材料不同，在其中一个区域形成源漏掺杂层的过程中，所述侧墙材料层作为另一个区域的保护层。
所述侧墙材料层240的材料包括：氧化硅、氮化硅、氮氧化硅、碳氧化硅、碳氮化硅或碳氮氧化硅。
形成侧墙材料层240的工艺为沉积工艺，如原子层沉积工艺或等离子体化学气相沉积工艺。
本实施例中，所述侧墙材料层240的材料为氮化硅。
所述侧墙材料层240的厚度为10埃～30埃。
侧墙材料层240的厚度决定了后续形成的第一侧墙和栅极侧墙的厚度。
所述侧墙材料层240的厚度大于30埃，后续形成的栅极侧墙厚度较厚，后续源漏掺杂层距离沟槽区较远，源漏掺杂层对沟道的应力减小；所述侧墙材料层240的厚度小于10埃，后续形成的栅极侧墙厚度较厚，后续源漏掺杂层距离沟槽区较近，短沟道效应明显。
所述侧墙材料层240的工艺为原子层沉积工艺，所述原子层沉积工艺的参数包括：采用的气体为SiH2Cl2和NH3的混合气体，混合气体的流量为1500sccm～4000sccm，压强为1mtorr～10mtorr，温度为200摄氏度～600摄氏度，沉积次数为30次～300次。
形成侧墙材料层240后，对所述第一鳍部211第二侧壁的侧墙材料层240和第二鳍部212第三侧壁的所述侧墙材料层进行改性处理，使得位于第一鳍部211第二侧壁和位于第二鳍部212的第三侧壁的侧墙材料层240具有掺杂离子，所述具有掺杂离子的侧墙材料层240和无掺杂的侧墙材料层240的刻蚀选择比不同。
所述改性处理的工艺为离子掺杂工艺，所述掺杂离子为掺杂离子。
所述掺杂离子包括：氩离子或硅离子。
所述掺杂离子进入氮化硅的原子结构中，破坏了氮化硅的原子结构，使得掺杂后的氮化硅易于去除。
所述离子掺杂的工艺包括离子注入工艺。
所述离子注入工艺的参数包括：所述注入离子为氩离子或者硅离子，所述注入离子的剂量为1.0E14atom/cm2～1.0E17atom/cm2。
参考图8，图8与图7剖面方向一致，回刻蚀所述侧墙材料层240，直至暴露出第一鳍部211、第二鳍部212和隔离层201顶部表面，在第一鳍部211第一侧壁形成第一侧墙251，在第一鳍部211第二侧壁形成第一改性层202，在第二鳍部212第四侧壁形成第二侧墙252，在第二鳍部212第三侧壁形成第二改性层203。
所述第一改性层202和第二改性层203内具有掺杂离子。
所述侧墙材料层240的材料为氮化硅，所述掺杂离子包括氩离子或硅离子。
本实施例中，所述侧墙材料层240的材料为氮化硅，所述掺杂离子为硅离子。硅离子进入到氮化硅原子的结构中，破坏氮化硅的原子结构，使得氮化硅易于去除，后续使用合适的刻蚀溶液，能够去除第一改性层和第二改性层的同时减少对第一侧墙和第二侧墙的损伤。
在一实施例中，所述第一侧墙和第二侧墙的形成方法包括：在第一鳍部侧壁形成初始第一侧墙；在第二鳍部侧壁形成初始第二侧墙；对第一鳍部第二侧壁的初始第一侧墙和第二鳍部第四侧壁的初始第二侧墙进行改性处理，分别在第一鳍部第二侧壁和第二鳍部第四侧壁形成第一改性层和第二改性层，所述第一改性层和第二改性层内具有掺杂离子，所述第一改性层和第二改性层和初始第一侧墙和初始第二侧墙的刻蚀选择比不同；去除所述第一改性层和所述第二改性层，在第一鳍部第一侧壁形成所述第一侧墙，在第二鳍部第四侧壁形成所述第二侧墙。
所述初始第一侧墙和初始第二侧墙的形成方法包括：在衬底上形成侧墙材料层，所述侧墙材料层覆盖第一鳍部顶部和侧壁以及第二鳍部顶部和侧壁；回刻蚀所述侧墙材料层，在第一鳍部侧壁形成初始第一侧墙，在第二鳍部侧壁形成初始第二侧墙。
形成第一侧墙251和第二侧墙252后，在第一鳍部211内形成第一掺杂层，所述第一侧墙251覆盖第一掺杂层部分侧壁。
本实施例中，还包括：在第二鳍部212内形成第二掺杂层，所述第二侧墙252覆盖第二掺杂层部分侧壁。
当第一区域I和第二区域II所形成的器件类型不同时，所述第一栅极结构221和第二栅极结构222所形成的器件类型不同，所述第一掺杂层和第二掺杂层不同时形成。
在一实施例中，形成所述第一掺杂层后，形成所述第二掺杂层。
在另一实施例中，形成所述第二掺杂层后，形成所述第一掺杂层。
当第一区域I和第二区域II所形成的器件类型相同时，所述第一栅极结构221和第二栅极结构222所形成的器件类型相同，形成所述第一掺杂层过程中形成所述第二掺杂层。
所述第一掺杂层的形成方法包括：在第一栅极结构221两侧的第一鳍部211中形成第一凹槽，在第一凹槽中外延形成第一掺杂层。
所述第二掺杂层的形成方法包括：在第二栅极结构222两侧的第二鳍部212中形成第二凹槽，在第二凹槽中外延形成第二掺杂层。
本实施例中，第一区域I和第二区域II所形成的器件类型相同，形成所述第一掺杂层过程中形成所述第二掺杂层。具体请参考图9至图11。
参考图9，去除第一侧墙251和第一改性层202之间的第一鳍部211形成初始第一凹槽204；去除第二侧墙252和第二改性层203之间的第二鳍部212形成初始第二凹槽205。
所述初始第一凹槽204位于第一栅极结构221两侧的第一鳍部211内所述初始第二凹槽205位于第二栅极结构222两侧的第二鳍部212内。
所述初始第一凹槽204为后续形成第一凹槽提供空间。
所述初始第二凹槽205为后续形成第二凹槽提供空间。
所述初始第一凹槽204和初始第二凹槽205底部表面与隔离层201顶部表面齐平或低于。
本实施例中，所述初始第一凹槽204和初始第二凹槽205底部表面与隔离层201顶部表面齐平。
参考图10，形成初始第一凹槽204后，去除第一改性层202和第二改性层203，在第一鳍部211第一侧壁形成第一侧墙251；形成初始第二凹槽205后，在第二鳍部212第四侧壁形成第二侧墙252。
去除第一改性层202和第二改性层203，使得初始第一凹槽204形成为第一凹槽206，使得初始第二凹槽205形成为第二凹槽207。
去除所述第一改性层202和第二改性层203的工艺包括：干法刻蚀工艺或者湿法刻蚀工艺。
所述湿法刻蚀工艺的参数包括：磷酸的体积百分比浓度为70％～95％，工艺温度为90摄氏度～150摄氏度。
所述第一改性层202和第二改性层203为侧墙材料层240离子掺杂后形成，第一改性层202和第二改性层203的材料为掺杂有掺杂离子的氮化硅，掺杂离子为硅，掺杂离子破坏氮化硅的原子结构，使得掺杂后的氮化硅容易被去除的同时对第一侧墙251和第二侧墙252的影响较小。
第一侧墙251位于第一凹槽206一侧，第二侧墙252位于第二凹槽207同一侧；在第一凹槽206内形成第一掺杂层261，在第二凹槽207内形成第二掺杂层262；所述第一掺杂层261受第一侧墙251限制，使得第一掺杂层251的表面在第一侧墙251限制的一侧不易形成尖端；所述第二掺杂层262受第二侧墙252限制，使得第二掺杂层262的表面在第二侧墙252限制的一侧不易形成尖端。
参考图11，形成第一侧墙251和第二侧墙252后，在第一鳍部211内形成第一掺杂层261；在第二鳍部内212形成第二掺杂层262，第二掺杂层262与第一掺杂层261相邻。
在第一凹槽206中外延形成第一掺杂层261。
在外延形成第一掺杂层261的过程中，还包括对所述第一掺杂层261进行原位掺杂，在第一掺杂层261内掺杂第一源漏离子。
当所述第一栅极结构221用于形成P型器件时，第一掺杂层261的材料包括掺杂有第一源漏离子的硅锗，第一源漏离子的导电类型为P型；当所述第一栅极结构221用于形成N型器件时，第一掺杂层261的材料包括掺杂有第一源漏离子的硅，第一源漏离子的导电类型为N型。
在第二凹槽207中外延形成第二掺杂层262。
在外延形成第二掺杂层262的过程中，还包括对所述第二掺杂层262进行原位掺杂，在第二掺杂层262内掺杂第二源漏离子。
当所述第二栅极结构222用于形成P型器件时，第二掺杂层262的材料包括掺杂有第二源漏离子的硅锗，第二源漏离子的导电类型为P型；当所述第二栅极结构222用于形成N型器件时，第二掺杂层262的材料包括掺杂有第一源漏离子的硅，第二源漏离子的导电类型为N型。
本实施例中，所述第一区域I与所述第二区域II所形成的器件类型相同，所述第一栅极结构221和第二栅极结构222均用于形成P型器件，所述第一掺杂层261和第二掺杂层262的材料为掺杂有硼离子的硅锗，所述第一源漏离子为硼离子。
在一实施例中，所述第一栅极结构221和第二栅极结构222均用于形成N型器件，所述第一掺杂层261和第二掺杂层262的材料为掺杂有磷离子的硅，所述第一源漏离子为磷离子。
在其他实施例中，所述第一区域I与所述第二区域II所形成的器件类型不同，所述第一栅极结构221用于形成P型器件，所述第二栅极结构222均用于形成N型器件；或者所述第一栅极结构221用于形成N型器件，所述第二栅极结构222均用于形成P型器件。
第一侧墙251位于第一鳍部211第一侧壁，第一侧壁朝向第二鳍部212；在第一鳍部211内形成第一掺杂层，在第二鳍部212内形成第二掺杂层；第一侧墙251位于第一掺杂层261和第二掺杂层262之间，将第一掺杂层261和第二掺杂层262隔离，避免第一掺杂层261和第二掺杂层262发生桥接，同时，在第二鳍部212的第四侧壁形成第二侧墙252，在第二鳍部212内形成第二掺杂层262；则可以防止第二掺杂层262与第二鳍部的第四侧壁所朝向的相邻鳍部内所形成的掺杂层与第二掺杂层262发生桥接。在相邻鳍部间距离一定的情况下，相邻的第一掺杂层261和第二掺杂层262可以实现体积较大且不会发生桥接，相应的第一掺杂层261和第二掺杂层262表面积也较大。由于后续制程中形成的插塞与第一掺杂层261或第二掺杂层262的接触为全覆盖式接触，即插塞全覆盖第一掺杂层261或者第二掺杂层262的表面，第一掺杂层261或第二掺杂层262表面积较大，与的插塞的接触面积相应较大，能够降低所形成的晶体管的接触电阻，从而提高器件的性能。
在一实施例中，不形成所述第二侧墙。第一侧墙位于第一鳍部第一侧壁，第一侧壁朝向第二鳍部；在第一鳍部内形成第一掺杂层，在第二鳍部内形成第二掺杂层；第一侧墙位于第一掺杂层和第二掺杂层之间，将第一掺杂层和第二掺杂层隔离，避免第一掺杂层和第二掺杂层发生桥接。
相应的，本实施例还提供一种采用上述方法形成的半导体器件，参考图11，包括：衬底200，所述衬底200上具有相邻的第一鳍部211和第二鳍部212，所述第一鳍部211具有相对的第一侧壁和第二侧壁，第一侧壁朝向第二鳍部212，所述衬底200上还具有覆盖第一鳍部211和第二鳍部212部分侧壁的隔离层201，且所述隔离层201表面低于第一鳍部211顶部表面和第二鳍部212顶部表面；位于第一鳍部211的第一侧壁表面的第一侧墙251；位于第一鳍部211内的第一掺杂层261，所述第一侧墙251覆盖第一掺杂层261部分侧壁；位于第二鳍部212内的第二掺杂层262。
所述衬底200参照前述实施例的内容，不再详述。
所述第一侧墙251的结构和位置参考前述实施例的内容，不再详述。
所述第一掺杂层261和第二掺杂层262的材料和位置参考前述实施例的内容，不再详述。虽然本发明披露如上，但本发明并非限定于此。任何本领域技术人员，在不脱离本发明的精神和范围内，均可作各种更动与修改，因此本发明的保护范围应当以权利要求所限定的范围为准。

Claims (20)

1.一种半导体器件的形成方法，其特征在于，包括：
提供衬底，所述衬底上具有相邻的第一鳍部和第二鳍部，所述第一鳍部具有相对的第一侧壁和第二侧壁，第一侧壁朝向第二鳍部，所述衬底上还具有覆盖第一鳍部和第二鳍部部分侧壁的隔离层，且所述隔离层表面低于第一鳍部顶部表面和第二鳍部顶部表面；
在第一鳍部的第一侧壁表面形成第一侧墙；
形成第一侧墙后，在第一鳍部内形成第一掺杂层，所述第一侧墙覆盖第一掺杂层部分侧壁；
在第二鳍部内形成第二掺杂层。
2.根据权利要求1所述的半导体器件的形成方法，其特征在于，所述第二鳍部具有相对的第三侧壁和第四侧壁，所述第三侧壁朝向第一鳍部；所述半导体器件的形成方法还包括：在第二鳍部的第四侧壁形成第二侧墙；在第二鳍部内形成第二掺杂层，所述第二侧墙覆盖第二掺杂层部分侧壁。
3.根据权利要求2所述的半导体器件的形成方法，其特征在于，形成所述第一侧墙后，形成第二侧墙；形成所述第二侧墙后，形成所述第一侧墙。
4.根据权利要求2所述的半导体器件的形成方法，其特征在于，形成所述第一侧墙过程中形成所述第二侧墙。
5.根据权利要求4所述的半导体器件的形成方法，其特征在于，所述第一侧墙和第二侧墙的形成方法包括：在衬底上形成侧墙材料层，所述侧墙材料层覆盖第一鳍部顶部和侧壁以及第二鳍部顶部和侧壁；对所述第一鳍部第二侧壁的侧墙材料层和第二鳍部第三侧壁的所述侧墙材料层进行改性处理，使得位于第一鳍部第二侧壁和位于第二鳍部的第三侧壁的侧墙材料层具有掺杂离子，所述具有掺杂离子的侧墙材料层和无掺杂的侧墙材料层的刻蚀选择比不同；回刻蚀所述侧墙材料层，直至暴露出第一鳍部和第二鳍部顶部表面，在第一鳍部第一侧壁形成第一侧墙，在第一鳍部第二侧壁形成第一改性层，在第二鳍部第四侧壁形成第二侧墙，在第二鳍部第三侧壁形成第二改性层，所述第一改性层和第二改性层内具有掺杂离子；去除所述第一改性层和所述第二改性层，在第一鳍部第一侧壁形成所述第一侧墙，在第二鳍部第四侧壁形成所述第二侧墙。
6.根据权利要求4所述的半导体器件的形成方法，其特征在于，所述第一侧墙和第二侧墙的形成方法包括：在第一鳍部侧壁形成初始第一侧墙；在第二鳍部侧壁形成初始第二侧墙；对第一鳍部第二侧壁的初始第一侧墙和第二鳍部第四侧壁的初始第二侧墙进行改性处理，分别在第一鳍部第二侧壁和第二鳍部第四侧壁形成第一改性层和第二改性层，所述第一改性层和第二改性层内具有掺杂离子，所述第一改性层和第二改性层和初始第一侧墙和初始第二侧墙的刻蚀选择比不同；去除所述第一改性层和所述第二改性层，在第一鳍部第一侧壁形成所述第一侧墙，在第二鳍部第四侧壁形成所述第二侧墙。
7.根据权利要求6所述的半导体器件的形成方法，其特征在于，所述初始第一侧墙和初始第二侧墙的形成方法包括：在衬底上形成侧墙材料层，所述侧墙材料层覆盖第一鳍部顶部和侧壁以及第二鳍部顶部和侧壁；回刻蚀所述侧墙材料层，在第一鳍部侧壁形成初始第一侧墙，在第二鳍部侧壁形成初始第二侧墙。
8.根据权利要求1所述的半导体器件的形成方法，其特征在于，所述第一侧墙的形成方法包括：在第二鳍部上形成保护层，所述保护层覆盖第二鳍部顶部和侧壁；形成保护层后，在第一鳍部和保护层上形成侧墙材料层，所述侧墙材料层覆盖第一鳍部顶部和侧壁；对所述第一鳍部第二侧壁的侧墙材料层进行改性处理，使得位于第一鳍部第二侧壁的侧墙材料层具有掺杂离子，所述具有掺杂离子的侧墙材料层和无掺杂的侧墙材料层的刻蚀选择比不同；回刻蚀所述侧墙材料层，直至暴露出第一鳍部顶部表面，在第一鳍部第一侧壁形成第一侧墙，在第一鳍部第二侧壁形成第一改性层，所述第一改性层内具有掺杂离子；去除所述第一改性层，在第一鳍部第一侧壁形成所述第一侧墙。
9.根据权利要求5、6或8所述的半导体器件的形成方法，其特征在于，所述改性处理为离子掺杂工艺。
10.根据权利要求9所述的半导体器件的形成方法，其特征在于，所述掺杂离子包括：氩离子或硅离子。
11.根据权利要求9所述的半导体器件的形成方法，其特征在于，所述离子掺杂工艺包括离子注入工艺；所述离子注入工艺的参数包括：所述注入离子为氩离子或者硅离子，所述注入离子的剂量为1.0E14atom/cm2～1.0E17atom/cm2。
12.根据权利要求5或6所述的半导体器件的形成方法，其特征在于，去除所述第一改性层和第二改性层的工艺包括：干法刻蚀工艺或者湿法刻蚀工艺。
13.根据权利要求12所述的半导体器件的形成方法，其特征在于，所述湿法刻蚀工艺的参数包括：磷酸的体积百分比浓度为70％～95％，工艺温度为90摄氏度～150摄氏度。
14.如权利要求5或6所述的半导体器件的形成方法，其特征在于，所述第一掺杂层的形成方法包括：在第一鳍部内形成第一凹槽；在第一凹槽内外延形成第一掺杂层。
15.如权利要求14所述的半导体器件的形成方法，其特征在于，所述第一凹槽的形成方法包括：去除第一改性层前，去除第一侧墙和第一改性层之间的第一鳍部形成初始第一凹槽；去除所述初始第一凹槽侧壁的第一改性层，形成第一凹槽。
16.如权利要求5或6所述的半导体器件的形成方法，其特征在于，所述第二掺杂层的形成方法包括：在第二鳍部内形成第二凹槽；在第二凹槽内外延形成第二掺杂层。
17.如权利要求16所述的半导体器件的形成方法，其特征在于，所述第二凹槽的形成方法包括：去除第二改性层前，去除第二侧墙和第二改性层之间的第二鳍部形成初始第二凹槽；去除初始第二凹槽侧壁的第二改性层，形成第二凹槽。
18.根据权利要求1所述的半导体器件的形成方法，其特征在于，形成所述第一掺杂层后，形成所述第二掺杂层；形成所述第二掺杂层后，形成所述第一掺杂层。
19.根据权利要求1所述的半导体器件的形成方法，其特征在于，形成所述第一掺杂层过程中形成所述第二掺杂层。
20.一种采用权利要求1至19任一项方法所形成的半导体器件，其特征在于，包括：
衬底，所述衬底上具有相邻的第一鳍部和第二鳍部，所述第一鳍部具有相对的第一侧壁和第二侧壁，第一侧壁朝向第二鳍部，所述衬底上还具有覆盖第一鳍部和第二鳍部部分侧壁的隔离层，且所述隔离层表面低于第一鳍部顶部表面和第二鳍部顶部表面；
位于第一鳍部的第一侧壁表面的第一侧墙；
位于第一鳍部内的第一掺杂层，所述第一侧墙覆盖第一掺杂层部分侧壁；
位于第二鳍部内的第二掺杂层。
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