CN110945642B - 利用钨氧化还原的无缝钨填充 - Google Patents
利用钨氧化还原的无缝钨填充 Download PDFInfo
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- CN110945642B CN110945642B CN201880037482.4A CN201880037482A CN110945642B CN 110945642 B CN110945642 B CN 110945642B CN 201880037482 A CN201880037482 A CN 201880037482A CN 110945642 B CN110945642 B CN 110945642B
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- 229910052721 tungsten Inorganic materials 0.000 title claims abstract description 119
- 239000010937 tungsten Substances 0.000 title claims abstract description 119
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 title claims abstract description 116
- 239000000758 substrate Substances 0.000 claims abstract description 123
- 238000000034 method Methods 0.000 claims abstract description 57
- QGLKJKCYBOYXKC-UHFFFAOYSA-N nonaoxidotritungsten Chemical compound O=[W]1(=O)O[W](=O)(=O)O[W](=O)(=O)O1 QGLKJKCYBOYXKC-UHFFFAOYSA-N 0.000 claims abstract description 30
- 229910001930 tungsten oxide Inorganic materials 0.000 claims abstract description 30
- 238000000151 deposition Methods 0.000 claims abstract description 18
- 230000001590 oxidative effect Effects 0.000 claims abstract description 5
- 239000000463 material Substances 0.000 claims description 44
- 230000003647 oxidation Effects 0.000 claims description 21
- 238000007254 oxidation reaction Methods 0.000 claims description 21
- 239000000945 filler Substances 0.000 claims description 19
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 18
- 229910052710 silicon Inorganic materials 0.000 claims description 18
- 239000010703 silicon Substances 0.000 claims description 18
- 238000011946 reduction process Methods 0.000 claims description 13
- 238000000231 atomic layer deposition Methods 0.000 claims description 9
- 239000004020 conductor Substances 0.000 claims description 7
- 239000003989 dielectric material Substances 0.000 claims description 6
- -1 tungsten halide Chemical class 0.000 claims description 5
- 238000005229 chemical vapour deposition Methods 0.000 claims description 2
- 210000002381 plasma Anatomy 0.000 description 17
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 9
- 239000000376 reactant Substances 0.000 description 8
- 230000008021 deposition Effects 0.000 description 7
- 229910052751 metal Inorganic materials 0.000 description 6
- 239000002184 metal Substances 0.000 description 6
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 4
- 239000011521 glass Substances 0.000 description 4
- 229910052739 hydrogen Inorganic materials 0.000 description 4
- 229910052814 silicon oxide Inorganic materials 0.000 description 4
- 239000000126 substance Substances 0.000 description 4
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 3
- 229910052799 carbon Inorganic materials 0.000 description 3
- 239000007789 gas Substances 0.000 description 3
- 150000004767 nitrides Chemical class 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- 235000012239 silicon dioxide Nutrition 0.000 description 3
- 239000000377 silicon dioxide Substances 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 229910021529 ammonia Inorganic materials 0.000 description 2
- UMIVXZPTRXBADB-UHFFFAOYSA-N benzocyclobutene Chemical compound C1=CC=C2CCC2=C1 UMIVXZPTRXBADB-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000005429 filling process Methods 0.000 description 2
- 150000002429 hydrazines Chemical class 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 150000002739 metals Chemical class 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 239000011800 void material Substances 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 239000004642 Polyimide Substances 0.000 description 1
- 229910020177 SiOF Inorganic materials 0.000 description 1
- 150000001299 aldehydes Chemical class 0.000 description 1
- UORVGPXVDQYIDP-UHFFFAOYSA-N borane Chemical class B UORVGPXVDQYIDP-UHFFFAOYSA-N 0.000 description 1
- 229910000085 borane Inorganic materials 0.000 description 1
- 239000006227 byproduct Substances 0.000 description 1
- 229910002091 carbon monoxide Inorganic materials 0.000 description 1
- 150000001735 carboxylic acids Chemical class 0.000 description 1
- 229910017052 cobalt Inorganic materials 0.000 description 1
- 239000010941 cobalt Substances 0.000 description 1
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 229940104869 fluorosilicate Drugs 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- LNEPOXFFQSENCJ-UHFFFAOYSA-N haloperidol Chemical compound C1CC(O)(C=2C=CC(Cl)=CC=2)CCN1CCCC(=O)C1=CC=C(F)C=C1 LNEPOXFFQSENCJ-UHFFFAOYSA-N 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 125000004435 hydrogen atom Chemical class [H]* 0.000 description 1
- 238000009616 inductively coupled plasma Methods 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 150000001247 metal acetylides Chemical class 0.000 description 1
- 229910001092 metal group alloy Inorganic materials 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 239000005360 phosphosilicate glass Substances 0.000 description 1
- 238000005240 physical vapour deposition Methods 0.000 description 1
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 229920000642 polymer Polymers 0.000 description 1
- 229910021426 porous silicon Inorganic materials 0.000 description 1
- 229910052594 sapphire Inorganic materials 0.000 description 1
- 239000010980 sapphire Substances 0.000 description 1
- 150000004756 silanes Chemical class 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical class O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
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- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
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Abstract
描述了用于以无缝钨填充物来填充基板特征的方法。所述方法包括沉积钨膜、将钨膜氧化成氧化钨柱、将氧化钨膜还原成无缝钨间隙填充物,且可选地在钨间隙填充物上沉积额外的钨。
Description
技术领域
本公开的实施例总的来说涉及以无缝钨填充物来填充基板特征的方法。更具体而言,本公开的实施例涉及通过沉积氧化还原工艺来以无缝钨填充物填充基板特征的方法。
背景技术
间隙填充工艺为半导体制造的非常重要的阶段。间隙填充工艺用于以绝缘的或导电的材料填充高长宽比间隙(或特征)。例如,浅沟槽隔离、金属间介电层、钝化层、虚拟栅极等等。随着器件的几何形状缩小(例如,关键尺寸<20nm)以及热预算减少,空间的无缺陷填充变得越来越困难,因为有常规沉积工艺的限制。
大多数沉积方法在结构的顶部区域上比底部区域上沉积更多的材料。工艺通常形成蘑菇状膜轮廓。结果,特征的顶部部分某些时候过早捏缩,而在结构的下部部分内留下缝隙或空洞。此问题在小的特征中更加普遍。
用于间隙填充的钨的原子层沉积已证明为半导体工业中的关键技术。然而,间隙填充的缝隙为ALD钨沉积中的限制。因此,需要一种产生无缝钨填充的方法。
发明内容
本公开的一个或多个实施例涉及一种基板处理的方法,包括提供基板,所述基板具有第一材料的第一基板表面以及第二材料的第二基板表面。基板具有至少一个特征,所述至少一个特征具有侧壁以及底部。侧壁由第一基板表面形成,且底部由第二基板表面形成。在基板上形成钨膜。钨膜具有形成于特征内的缝隙以及形成于特征外部的第一基板表面上的覆盖物。平坦化基板表面以从第一基板表面移除覆盖物,使得钨膜的顶部与特征外部的第一基板表面大约共面。氧化钨膜以形成氧化钨柱,所述氧化钨柱从基板特征延伸而不具有缝隙。将氧化钨柱还原成钨。钨在特征内形成基本上无缝的钨间隙填充物。
本公开的另一实施例涉及一种基板处理的方法,包括提供基板,所述基板具有形成于基板表面中的至少一个特征。特征从基板表面延伸一距离,且具有侧壁以及底部。特征的侧壁以及基板表面由第一材料组成,且底部由不同于第一材料的第二材料组成。在基板上形成钨膜,使得在特征内在钨膜内存在空洞,以及钨覆盖物形成于基板表面上。平坦化基板以从基板表面移除钨覆盖物,使得钨膜的顶部与基板表面基本上共面。氧化钨膜以形成氧化钨的柱,所述柱从特征延伸而不具有缝隙。将氧化钨的柱还原成钨,以在至少一个特征内形成基本上无缝的钨间隙填充物。
本公开的其他实施例涉及一种基板处理的方法,包括提供基板,所述基板具有第一材料的第一基板表面以及第二材料的第二基板表面。第一材料由介电材料组成且第二材料由导电材料组成。基板具有至少一个特征,所述至少一个特征具有侧壁以及底部。侧壁由第一基板表面形成,且底部由第二基板表面形成。通过原子层沉积在基板上形成钨膜。钨膜具有在特征内形成的封闭的缝隙以及形成于特征外部的第一基板表面上的覆盖物。缝隙的顶部在特征的侧壁上方。平坦化基板表面以从第一基板表面移除覆盖物,使得钨膜的顶部与特征外部的第一基板表面大约共面,且缝隙的顶部被移除。通过热氧化工艺或等离子体氧化工艺来氧化钨膜,以形成氧化钨柱,所述氧化钨柱从特征延伸而不具有缝隙。通过热还原工艺或等离子体还原工艺而将氧化钨柱还原成钨。钨在特征内形成基本上无缝的钨间隙填充物,且钨间隙填充物的顶部在特征外部的第一基板表面下方小于或等于约在钨间隙填充物上沉积额外的钨,以通过在钨间隙填充物上沉积硅膜且将硅膜暴露至卤化钨以将硅膜转换成钨,来抬升钨间隙填充物的顶部至基本上与特征外部的第一基板表面共面。
附图说明
如上简要概述且于以下更详细讨论的本公开的实施例可通过参考本公开的实施例来理解,一些实施例在附图中描绘。然而,应注意到,附图仅示出本公开的典型实施例,且因此不应被认为为限制本公开的范围,因为本公开允许其他等效实施例。
附图显示根据本公开的一个或多个实施例的间隙填充工艺的剖面示意图。
具体实施方式
在描述本公开的数个示例性实施例之前,应理解本公开并非限于以下描述中提及的构造细节或工艺步骤。本公开能够包括其他实施例,且能够以各种方式实现或执行。
如此说明书以及所附权利要求中所使用,“基板”以及“晶片”一词可互换使用,两者均代表在其上工艺作用的表面或表面的部分。由本领域技术人员还将理解,基板的称呼也可仅代表基板的一部分,除非上下文另外清楚地指示。另外,在基板上沉积的称呼可意味着裸基板以及在其上具有沉积的或形成的膜或特征的基板。
如此处所使用的“基板”代表形成于基板上的任何基板或材料表面,于制作工艺期间在此基板上执行膜处理。例如,在其上可执行工艺的基板表面根据应用包括诸如硅、氧化硅、应变硅、绝缘体上硅(SOI)、碳掺杂氧化硅、氮化硅、掺杂硅、锗、砷化镓、玻璃、蓝宝石之类的材料以及任何其他的材料,诸如金属、金属氮化物、金属合金以及其他导电材料。基板包括但不限于半导体晶片。基板可暴露至预先处理工艺,以抛光、蚀刻、还原、氧化、羟化(或者产生或接枝目标化学部分以施加化学功能性)、退火和/或烘烤基板表面。除了在基板本身的表面上直接进行膜处理之外,在本公开中,如以下更详细公开,所公开的任何膜处理步骤还可对形成于基板上的下层执行,且术语“基板表面”如上下文指示,意图包括此下层。因此,例如,当在基板表面上已沉积膜/层或部分的膜/层时,新沉积的膜/层的暴露的表面变成基板表面。给定基板表面所包括的将取决于待沉积的膜以及所使用的特定化学物质。
附图示出具有两个特征110(例如,沟槽)的基板105的剖面视图。附图为了说明的目的示出基板具有两个特征;然而,本领域技术人员将理解可具有少于或多于两个特征。特征110的形状可为任何适合的形状,包括但不限于沟槽以及圆柱形通孔。在特定实施例中,特征110为沟槽。如此处所使用,术语“特征”意味着任何意图的表面不规则性。特征的合适示例包括但不限于具有顶部、两个侧壁和底部的沟槽、具有顶部和从表面向上延伸的侧壁的峰部(或鳍部)、以及具有从表面向下延伸的侧壁和开口底部的通孔。特征可具有任何适合的长宽比(特征的深度比特征的宽度的比率)。在某些实施例中,长宽比大于或等于约5:1、10:1、15:1、20:1、25:1、30:1、35:1或40:1。
基板105由两种材料组成,所述两种材料形成两个基板表面:第一材料120形成第一基板表面125且第二材料130形成第二基板表面135。特征110从特征110外部的第一基板表面127延伸至深度D到第二基板表面135。特征110具有界定特征110的宽度W的第一侧壁111和第二侧壁112。第一侧壁111和第二侧壁112由第一材料120组成。由侧壁以及底部形成的开口区域也称为间隙。填充间隙的材料称为间隙填充物或间隙填充材料。
在某些实施例中,第一材料120以及第二材料130是相同的。在某些实施例中,第一材料120以及第二材料130是不同的。在某些实施例中,第一材料120包括介电材料,且第二材料130包括导电材料,或反之亦然。
介电材料的示例包括但不限于二氧化硅、氧化硅、碳掺杂氧化物(CDO),例如碳掺杂二氧化硅、多孔二氧化硅、氮化硅或以上任何的组合。介电材料的额外示例包括但不限于氮化物、氧化物、某些聚合物、磷硅酸盐玻璃、氟硅酸盐(SiOF)玻璃、有机硅酸盐玻璃(SiOCH)、聚酰亚胺、环氧树脂、诸如苯并环丁烯(BCB)的可光限定的材料、或旋涂式玻璃。
导电材料的示例包括但不限于金属、金属氧化物、金属氮化物、金属碳化物以及它们的组合。在某些实施例中,第一材料120包括氧化硅且第二材料130包括钴或铜。
参照附图,本公开的一个或多个实施例涉及基板处理的方法100,方法100在基板特征中提供无缝隙的钨间隙填充。在基板上形成钨膜210。在间隙内,沿着侧壁以及底部形成部分的膜,但含有缝隙220。在某些实施例中,缝隙为膜沉积的副产物。例如,较高的长宽比特征更易于在沉积期间形成缝隙,因为于特征顶部的膜倾向捏缩闭合,使得在沉积的膜内围住空洞。缝隙220可为形成于特征110的侧壁111、112之间的任何间隙、空间或空洞。
在某些实施例中,类似于附图,沉积钨膜210使得由钨膜覆盖或“关闭”缝隙220。在此等实施例中,缝隙220具有顶部225。在某些实施例中,缝隙220的顶部225可在特征110外部的第一材料表面127上方延伸。
在某些实施例中,并未沉积钨膜,使得缝隙220并未由钨膜覆盖。在此类型的实施例中,缝隙220于膜的顶部维持打开。
钨膜210可通过任何适合的工艺形成,包括但不限于化学气相沉积、等离子体增强化学气相沉积、原子层沉积、等离子体增强原子层沉积和/或物理气相沉积。在某些实施例中,钨膜210通过原子层沉积形成。
在填充间隙之后,通过化学机械平坦化(CMP)工艺来移除覆盖物(即,沉积于间隙外部的基板的顶部上的钨)。在某些实施例中,执行CMP工艺,使得钨膜210的顶部与特征110外部的第一基板表面127大约共面。在此等实施例中,若缝隙220的顶部225在特征110的外部127的第一基板表面上方,则于平坦化期间将移除缝隙的顶部。在某些实施例中,钨膜210的顶部与特征110外部127的第一基板表面基本上共面。如此处所使用,术语“基本上共面”意味由第一表面形成的平面以及由钨膜形成的平面在 或/>内。
在平坦化之后,氧化钨膜210以形成氧化钨柱410。氧化钨柱通过化学氧化工艺或等离子体氧化工艺而形成。不论钨膜或特征内的任何缝隙,氧化钨柱410不具有缝隙。在氧化期间,在特征的顶部上维持间隙形状的保真度,使得氧化钨柱410从特征110直向上成长。如此处所使用,“直向上”意味着氧化钨柱410的侧边与特征110的侧壁111、112基本上共面。表面与侧壁111共面,其中在侧壁114和表面的接合处形成的角度为±10°。
热氧化工艺为通过特定反应物以及热量的使用而促进的氧化工艺,而并未使用等离子体。热氧化反应物的示例包括但不限于O2、O3、N2O、H2O、H2O2、CO、CO2以及它们的组合。
等离子体氧化工艺为通过特定反应物的自由基的形成而促进的氧化工艺。等离子体氧化反应物的示例包括但不限于O2、O3、H2O、H2O2以及它们的组合的等离子体。等离子体氧化工艺可为直接等离子体或远程等离子体。等离子体氧化工艺可为传导耦合等离子体(CCP)或电感耦合等离子体(ICP)。在某些实施例中,氧化工艺为自由基增强的,其中氧化气体经过热线以在气体内产生自由基,而并未离子化气体。
在氧化之后,还原氧化钨柱410以形成钨间隙填充物510。钨间隙填充物基本上无缝隙。钨间隙填充物510具有可比特征127外部的第一基板表面更高、更低或大约共面的顶部515。氧化钨柱通过热还原工艺或等离子体还原工艺来还原。
热还原工艺为通过特定反应物以及热量的使用而促进的还原工艺,而未使用等离子体。热还原反应物的示例包括但不限于氢、醇、羧酸、醛、硅烷、硼烷、氨、联氨、联氨衍生物以及它们的组合。
等离子体还原工艺为通过自由基的形成和/或特定反应物的离子而促进的还原工艺。等离子体还原反应物的示例包括但不限于氢、氨、联氨、联氨衍生物以及它们的组合的等离子体。
在某些实施例中,于还原氧化钨柱之后,钨间隙填充物510的顶部515为与特征127外部的第一基板表面125共面的内。换句话说,钨间隙填充物510的深度在特征深度D的/>内。在某些实施例中,钨间隙填充物510的顶部515在特征外部的第一基板表面125下方或低于特征外部的第一基板表面125。换句话说,钨间隙填充物510的深度小于特征深度D。在某些实施例中,于还原氧化钨柱之后,钨间隙填充物510的顶部515为与特征127外部的第一基板表面125共面的/>之中。
尽管未绘制于附图中,但在钨间隙填充物510的顶部515在特征127外部的第一基板表面125下方的实施例中,基板处理可进一步包括在钨间隙填充物510上选择性地沉积额外的钨。额外的钨的沉积可将钨间隙填充物510的顶部515抬升至与特征127外部的第一基板表面125基本上共面。在某些实施例中,额外的钨的此沉积包括在钨间隙填充物510上沉积硅膜以及将硅膜暴露至卤化钨,以将硅膜转换成钨。
此说明书全篇所称的“一个实施例”、“某些实施例”、“一个或多个实施例”或“一实施例”意指与实施例相结合描述的特定特征、结构、材料或特性包括在本公开的至少一个实施例中。因此,此说明书全篇的各处中的诸如“在一个或多个实施例中”、“在某些实施例中”、“在一个实施例中”或“在一实施例中”之类的短语的呈现并不一定代表本公开的相同实施例。再者,特定特征、结构、材料或特性可在一个或多个实施例中以任何适合的方式组合。
尽管本文已经参考特定实施例描述本公开,但是应理解此等实施例仅为本公开的原理和应用的说明。对本领域技术人员而言将明显的是可在不背离本公开的精神和范围的情况下对本公开的方法和装置作出各种改变和修改。因此,本公开意图包括所附权利要求的范围内的修改和改变及其均等方案。
Claims (15)
1.一种基板处理的方法,包括以下步骤:
提供基板,所述基板具有第一材料的第一基板表面以及第二材料的第二基板表面,所述基板具有至少一个特征,所述至少一个特征具有侧壁以及底部,所述侧壁由所述第一基板表面形成,且所述底部由所述第二基板表面形成;
在所述基板上形成钨膜,所述钨膜具有形成于所述特征内的缝隙以及形成于所述特征的外部的所述第一基板表面上的覆盖物;
平坦化所述基板以从所述第一基板表面移除所述覆盖物,使得所述钨膜的顶部与所述特征的外部的所述第一基板表面大约共面;
氧化所述钨膜以形成氧化钨柱,所述氧化钨柱从所述至少一个特征延伸而不具有缝隙;
将所述氧化钨柱还原成钨,所述钨在所述至少一个特征内形成基本上无缝的钨间隙填充物,使得所述钨间隙填充物的顶部在所述特征的外部的所述第一基板表面下方;以及
在所述钨间隙填充物上选择性沉积额外的钨,以抬升所述钨间隙填充物的所述顶部至与所述特征的外部的所述第一基板表面基本上共面,选择性沉积额外的钨包括在所述钨间隙填充物上沉积硅膜,且将所述硅膜暴露至卤化钨,以将所述硅膜转换成钨。
2.如权利要求1所述的方法,其中所述第一材料以及所述第二材料中的至少一者包括介电材料,且所述第一材料以及所述第二材料中的另一者包括导电材料。
3.如权利要求1所述的方法,其中所述钨膜的形成由原子层沉积工艺来执行。
4.如权利要求1所述的方法,其中在所述至少一个特征内形成的所述缝隙为封闭的。
5.如权利要求1所述的方法,其中在所述至少一个特征内形成的所述缝隙的顶部在所述侧壁上方,使得在平坦化时移除所述缝隙的所述顶部。
6.如权利要求1所述的方法,其中所述钨膜通过热氧化来氧化。
7.如权利要求1所述的方法,其中所述钨膜通过等离子体氧化来氧化。
8.如权利要求1所述的方法,其中还原所述氧化钨柱包括热还原工艺。
9.如权利要求1所述的方法,其中还原所述氧化钨柱包括等离子体还原工艺。
10.如权利要求1所述的方法,其中在还原所述氧化钨柱之后,所述钨间隙填充物的顶部在与所述特征的外部的所述第一基板表面为共面的内。
11.一种基板处理的方法,包括以下步骤:
提供基板,所述基板具有形成于基板表面中的至少一个特征,所述特征从所述基板表面延伸一距离且具有侧壁以及底部,所述特征的所述侧壁以及所述基板表面包括第一材料,且所述底部包括与所述第一材料不同的第二材料;
在所述基板上形成钨膜,使得在所述至少一个特征内在所述钨膜内存在空洞并且钨覆盖物形成于所述基板表面上;
平坦化所述基板以从所述基板表面移除所述钨覆盖物,使得所述钨膜的顶部与所述基板表面基本上共面;
氧化所述钨膜以形成氧化钨的柱,所述氧化钨的柱从所述至少一个特征延伸而不具有缝隙;
将所述氧化钨的柱还原成钨,以在所述至少一个特征内形成基本上无缝的钨间隙填充物,其中所述钨间隙填充物的顶部在所述基板表面下方;以及
在所述钨间隙填充物上选择性沉积额外的钨,以抬升所述钨间隙填充物的所述顶部至与所述特征的外部的所述基板表面基本上共面,选择性沉积额外的钨包括在所述钨间隙填充物上沉积硅膜,且将所述硅膜暴露至卤化钨,以将所述硅膜转换成钨。
12.如权利要求11所述的方法,其中所述钨膜的形成由原子层沉积工艺或化学气相沉积工艺中的一者或多者来执行。
13.如权利要求11所述的方法,其中所述钨膜通过热氧化工艺或等离子体氧化工艺中的一者或多者来氧化。
14.如权利要求11所述的方法,其中还原所述氧化钨的柱通过热还原工艺或等离子体还原工艺中的一者或多者而发生。
15.一种基板处理的方法,包括以下步骤:
提供基板,所述基板具有第一材料的第一基板表面以及第二材料的第二基板表面,所述第一材料包括介电材料且所述第二材料包括导电材料,所述基板具有至少一个特征,所述至少一个特征具有侧壁以及底部,所述侧壁由所述第一基板表面形成,且所述底部由所述第二基板表面形成;
通过原子层沉积在所述基板上形成钨膜,所述钨膜具有在所述特征内形成的封闭的缝隙以及形成于所述特征的外部的所述第一基板表面上的覆盖物,所述缝隙的顶部在所述侧壁的上方;
平坦化所述基板以从所述第一基板表面移除所述覆盖物,使得所述钨膜的顶部与所述特征的外部的所述第一基板表面大约共面,且所述缝隙的所述顶部被移除;
通过热氧化工艺或等离子体氧化工艺来氧化所述钨膜,以形成氧化钨柱,所述氧化钨柱从所述特征延伸而不具有缝隙;
通过热还原工艺或等离子体还原工艺而将所述氧化钨柱还原成钨,所述钨在所述特征内形成基本上无缝的钨间隙填充物,且所述钨间隙填充物的顶部在所述特征外部的所述第一基板表面下方小于或等于约以及
在所述钨间隙填充物上沉积额外的钨,以通过在所述钨间隙填充物上沉积硅膜且将所述硅膜暴露至卤化钨以将所述硅膜转换成钨,来抬升所述钨间隙填充物的所述顶部至与所述特征的外部的所述第一基板表面基本上共面。
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Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4882203A (en) * | 1988-11-04 | 1989-11-21 | Cvd Systems & Services | Heating element |
JP2003507888A (ja) * | 1999-08-18 | 2003-02-25 | ステアーグ アール ティ ピー システムズ インコーポレイテッド | 半導体ウェーハ上に銅の特徴を生じさせる方法 |
KR20050030097A (ko) * | 2003-09-24 | 2005-03-29 | 가부시끼가이샤 르네사스 테크놀로지 | 반도체 집적회로장치 및 그 제조방법 |
Family Cites Families (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP4315424B2 (ja) | 2003-08-29 | 2009-08-19 | キヤノン株式会社 | ナノ構造体の製造方法 |
TW200734482A (en) * | 2005-03-18 | 2007-09-16 | Applied Materials Inc | Electroless deposition process on a contact containing silicon or silicide |
US7879683B2 (en) | 2007-10-09 | 2011-02-01 | Applied Materials, Inc. | Methods and apparatus of creating airgap in dielectric layers for the reduction of RC delay |
KR101534678B1 (ko) * | 2009-02-12 | 2015-07-08 | 삼성전자주식회사 | 텅스텐 콘택 플러그를 산소 분위기에서 rta 처리하고, rto 처리된 텅스텐 플러그를 수소 분위기에서 환원시키는 반도체 소자의 제조방법 |
US8575753B2 (en) | 2009-05-27 | 2013-11-05 | Samsung Electronics Co., Ltd. | Semiconductor device having a conductive structure including oxide and non oxide portions |
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TWI408183B (zh) * | 2010-12-07 | 2013-09-11 | Ind Tech Res Inst | 隔熱材料及其製造方法 |
KR101172272B1 (ko) | 2010-12-30 | 2012-08-09 | 에스케이하이닉스 주식회사 | 매립비트라인을 구비한 반도체장치 제조 방법 |
CN113862634A (zh) | 2012-03-27 | 2021-12-31 | 诺发系统公司 | 钨特征填充 |
US9312168B2 (en) | 2013-12-16 | 2016-04-12 | Applied Materials, Inc. | Air gap structure integration using a processing system |
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Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4882203A (en) * | 1988-11-04 | 1989-11-21 | Cvd Systems & Services | Heating element |
JP2003507888A (ja) * | 1999-08-18 | 2003-02-25 | ステアーグ アール ティ ピー システムズ インコーポレイテッド | 半導体ウェーハ上に銅の特徴を生じさせる方法 |
KR20050030097A (ko) * | 2003-09-24 | 2005-03-29 | 가부시끼가이샤 르네사스 테크놀로지 | 반도체 집적회로장치 및 그 제조방법 |
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