CN110932732A - Single bit receiving system and method thereof - Google Patents
Single bit receiving system and method thereof Download PDFInfo
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Abstract
A single bit receiving system and method thereof, comprising a microwave channel front end and a sampling processing board; the front end of the microwave channel is connected with the sampling processing plate; and a low noise amplifier is arranged at an input port at the front end of the microwave channel for receiving radio frequency signals. And each stage of amplifier, filter, temperature compensation circuit and equalizer are arranged in the front end of the microwave channel. The defects of high operation complexity and low sensitivity of frequency domain detection of a single-bit receiver in the aspect of instantaneous calculation in the prior art are effectively avoided by combining other structures or methods.
Description
Technical Field
The invention relates to the technical field of interference signals and signal generation, in particular to a single-bit receiving system and a method thereof.
Background
The single bit receiver, namely the single bit digital receiver, is a special broadband receiver, adopt 1 bit to quantize, it is apt to realize the superspeed sampling, and can realize the real-time signal processing, it applies to the instantaneous frequency measurement, can reach the bandwidth, sensitivity of the same order of magnitude as IFM receiver, possess the ability to process the multiple signals arriving at the same time, and have stronger use flexibility and function expansibility, in addition, the single bit digital receiver can be regarded as the guide receiver of the superheterodyne receiver, can judge whether the signal exists and rough measurement of frequency in real time and high sensitivity, guide the superheterodyne receiver to follow the signal frequency fast and promote and intercept the probability, the single bit digital receiver has wide application in the ultra wide band communication system too.
However, the conventional single-bit receiver has a high computational complexity in instantaneous calculation and also has low sensitivity in frequency domain detection.
Disclosure of Invention
In order to solve the above problems, the present invention provides a single-bit receiving system and method thereof, which effectively avoid the defects of high operation complexity and low sensitivity of frequency domain detection in the aspect of instantaneous computation of a single-bit receiver in the prior art.
In order to overcome the defects in the prior art, the invention provides a solution for a single-bit receiving system and a method thereof, which comprises the following steps:
a single-bit receiving system comprises a microwave channel front end and a sampling processing board;
the front end of the microwave channel is connected with the sampling processing plate;
and a low noise amplifier is arranged at an input port at the front end of the microwave channel for receiving radio frequency signals. And each stage of amplifier, filter, temperature compensation circuit and equalizer are arranged in the front end of the microwave channel.
The structure that sets up amplifier and wave filter, temperature compensation circuit and the equalizer of each stage in microwave channel front end includes:
a plurality of cascaded amplifiers;
an attenuator or an equalizer is connected in series between each stage of amplifier.
The structure that an attenuator or an equalizer is cascaded between amplifiers of each stage comprises:
the input end of the first-stage amplifier is used as an input port of the front end of the microwave channel for receiving radio-frequency signals;
a first fixed attenuator is connected between the first-stage amplifier and the second-stage amplifier;
a first temperature compensation attenuator is connected between the second-stage amplifier and the third-stage amplifier;
a second fixed attenuator is connected between the third-stage amplifier and the fourth-stage amplifier;
a first amplitude equalizer is connected between the fourth-stage amplifier and the fifth-stage amplifier;
and the fifth-stage amplifier, the second temperature compensation attenuator, the sixth-stage amplifier, the second amplitude equalizer and the second fixed attenuator are sequentially connected.
The first-stage amplifier, the second-stage amplifier, the third-stage amplifier, the fourth-stage amplifier, the fifth-stage amplifier and the sixth-stage amplifier are all HMC462 type amplifiers;
the first amplitude equalizer and the second amplitude equalizer are both BWAES-6/18 type amplitude equalizers;
the first fixed attenuator and the second fixed attenuator are both ARN3590-3 type fixed attenuators;
the first temperature-compensation attenuator and the second temperature-compensation attenuator are both WTVA0200N07WB2 type temperature-compensation attenuators.
Filters can also be cascaded between the amplifiers of each stage.
The sampling rate of the sampling processing plate is 40 Gsps.
The ultra-high speed sampling processing board adopts a mode of scrambling high speed data lines, and the mode of scrambling the high speed data lines comprises the following steps:
generating a pseudo-random signal which is homologous with the sampling clock and is fixed in a certain set speed range, carrying out XOR operation on the pseudo-random signal and data obtained after the signal sent from the front end of the microwave channel is processed by the ADC, and enabling the signal obtained after the XOR operation to enter a processor of the ultra-high speed sampling processing board after the signal passes through the XOR gate circuit so as to achieve the purpose of scrambling.
The high-speed signal simulation comprises via hole optimization simulation, frequency domain simulation analysis and time domain simulation analysis;
the via optimization simulation is used for optimizing the size of the via, so that the impedance of the via meets the requirement of 100 ohms of differential impedance;
the frequency domain simulation analysis is used for checking the channel transmission condition according to the simulation signal channel characteristic;
the time domain simulation analysis is used for predicting the waveform of the signal so as to check whether the signal meets the standard requirement.
The ultra-high-speed sampling processing board comprises a low-speed ADC, a clock chip, a high-speed ADC, an FPGA chip, an ARM chip, an interface isolation chip and a photoelectric conversion module;
the low-speed ADC, the high-speed ADC, the ARM chip, the interface isolation chip and the photoelectric conversion module are all connected with the FPGA chip;
the high-speed ADC is connected with the clock chip and is used for receiving radio frequency signals;
the low-speed ADC is used for receiving a DLVA signal, and the DLVA signal is a signal obtained after the radio-frequency signal passes through DLVA.
The FPGA chip CAN be a Virtex-7 Virtex-7 Vx690T model FPGA chip, and the interface isolation chip is used for being connected with an LVDS interface, a CAN bus or an RS232 serial port;
the ARM chip is connected with the RS232 serial port;
the photoelectric conversion module is connected with the optical fiber.
The method of the single-bit receiving system comprises the following steps:
and processing a pulse signal obtained by sampling the ultra-high-speed sampling processing plate and sampling data obtained by sampling the DLVA signal through an amplitude sampling circuit.
The method for processing the pulse signal obtained by sampling the ultra-high speed sampling processing plate and the sampling data obtained by sampling the DLVA signal through the amplitude sampling circuit comprises the following steps of:
step 1: the high-speed data receiving stage specifically comprises:
the ultra-high speed sampling processing board works at a signal transmission rate of 40Gbps to respectively sample and quantize pulse signals input from the front end of the microwave channel, and the sampled and quantized digital signals are received and transmitted through a high-speed serial transceiver embedded in the FPGA chip; the internal control logic of the FPGA chip firstly aligns received digital signals serving as sampling data to ensure the synchronization of the sampling data; secondly, the sequential switching of the sampling data is completed, because the randomness of the sampling clock phase can influence the change of the signal output sequence of the low-speed ADC or the high-speed ADC; finally, the adjusted data are sorted and integrated according to the sequence required by the algorithm, so that the integrated data are sent to a single-bit ultra-fast Fourier transform module to carry out the operation of single-bit ultra-fast Fourier transform after the clock domain synchronization is finished;
step 2: the single-bit ultra-fast Fourier transform FFT stage specifically comprises:
a discrete Boyle transform DFT, expressed as equation (2):
in the formula (2), x (N) is the N +1 th data in the input integrated data, N is the value obtained by adding one to the number of the integrated data, N and k are integers,
is a Kernel function;
and step 3: a spectral peak search stage, which specifically comprises:
performing maximum spectrum search in an autocorrelation output result X (k) of discrete Boly transform DFT, namely performing modular operation on the autocorrelation output result X (k), comparing in each channel of an ultra-high-speed sampling processing board to obtain a maximum value after the modular operation, selecting complex information of the maximum value as a peak spectral line for extracting phase information, simultaneously sending the complex information to a frequency fine measurement module for performing frequency fine estimation, and applying a sliding FFT algorithm to a module of the peak spectral line and a determined threshold to obtain envelope information of an input signal for use in TOA and PW pulse width calculation;
and 4, step 4: the frequency precision measurement stage specifically comprises the following steps:
further fine estimation is carried out on the frequency value obtained by the FFT by using an instantaneous frequency measurement method;
and 5: a PDW formation phase, which comprises in particular:
and synchronously fusing the relative amplitude of the digital processing and the amplitude of the video sampling, and acquiring signal amplitude information while performing inter-channel harmonic suppression. And finally, synthesizing the frequency, the phase, the amplitude, the arrival time and the pulse width information into PDW for output.
The invention has the beneficial effects that:
the invention compensates the gain fluctuation of the device at the front end of the broadband microwave channel at high and low temperatures through the temperature compensation attenuator, compensates the gain fluctuation of the circuit at the front end of the broadband microwave channel at high and low ends of frequency by using the amplitude equalizer, ensures the output power of the sixth-stage amplifier to be consistent at high and low ends of power when the second amplitude equalizer is used as the final-stage equalization, and ensures that the output power of the broadband microwave channel is in the optimal working range of the ultra-high speed sampling processing board used as the digital sampling board. The ultra-wideband high-sensitivity instantaneous frequency measurement technology for the single-bit receiving system to carry out frequency domain detection is the core for realizing large bandwidth, high sensitivity and real-time processing. The corresponding frequency measurement algorithm needs to meet the requirements of broadband input and real-time performance, and also needs to be well adapted in the aspects of signal envelope extraction, narrow pulse adaptation, simultaneous arrival signal adaptation, frequency fine estimation and the like. When the algorithm is implemented, the optimization design is achieved as much as possible, the calculation amount and the complexity in the real-time processing process are reduced, and the consumption of hardware processing resources is reduced. The hardware platform is constructed aiming at the characteristics of the algorithm such as time sequence requirement, resource demand type, topological structure and the like on the basis of meeting the implementation of the algorithm. The software algorithm and the hardware processing platform are combined together efficiently. Meanwhile, the whole processing time sequence runs at high speed and reliably through reasonable distribution of hardware processing resources and reasonable layout and wiring constraint of logic resources.
Drawings
Fig. 1 is a structural diagram of a microwave channel front end of a single bit reception system of the present invention.
Fig. 2 is a flow chart of the front end of a broadband microwave channel with a specification model of the single bit receive system of the present invention.
Fig. 3 is a graph of the gain of the amplifier at the front end of the microwave channel of the single bit receive system of the present invention.
Fig. 4 is a graph of the saturated output of the amplifier at the front end of the microwave channel of the single bit receive system of the present invention.
Fig. 5 is a frequency characteristic curve of an amplitude equalizer at the front end of a microwave channel of the single-bit receiving system of the present invention.
FIG. 6 is a schematic diagram of a via model of the present invention.
FIG. 7 is a schematic diagram of a via simulation result of the present invention.
Fig. 8 is a simulation of insertion loss of the present invention.
Fig. 9 is a structural view of an ultra high speed sampling processing board of the present invention.
FIG. 10 is a Kernel function with both real and imaginary parts quantized to 1 bit according to the present invention.
Fig. 11 shows the Kernel function when N is 8 according to the present invention.
Detailed Description
The invention will be further described with reference to the following figures and examples.
As shown in fig. 1-11, the single-bit receiving system includes a broadband microwave channel front end and an ultra-high speed sampling processing board;
the front end of the broadband microwave channel is connected with the ultra-high speed sampling processing board;
the technical difficulties of the front end of the broadband microwave channel mainly include two points. The method has the advantages that the requirements of no obvious deterioration of signal stray and intermodulation in a channel and low noise are met under the condition that an input large dynamic radio frequency signal is compressed to be within a constant level range. Secondly, miniaturization and low power consumption need to be realized.
In addition, in order to ensure the sensitivity and the receiving performance of a single-bit receiving system, good amplitude-frequency consistency, lower spurious level (-10dBc) and lower noise coefficient are necessarily required in the front end of the whole broadband microwave channel. For an ultra-high-speed sampling processing board, an input signal obtained from the front end of the broadband microwave channel generally requires a power level in a range of-5 dBm to +6dBm (the power range is small in quantization random jitter). The signal input into the single-bit receiving system has a large dynamic range, and to achieve a sensitivity of-65 dBm, the signal input into the single-bit receiving system needs to be compressed to a constant level range, small signals and large signals are guaranteed not to be distorted, and the performance of inputting the large signals into the front end of the broadband microwave channel needs to be designed in detail on the premise of large gain. In order to reduce the noise coefficient in the broadband microwave channel front end, a low noise amplifier is added to an input port of the broadband microwave channel front end for receiving radio frequency signals so as to improve the noise level of the whole single-bit receiving system. And the high-performance front end of the broadband microwave channel is realized by reasonably distributing and setting the gains of amplifiers at all stages and necessary filters, temperature compensation circuits and equalizers in a multistage amplification mode in the front end of the broadband microwave channel.
The structure of the broadband microwave channel front end with high performance is realized by adopting a multi-stage amplification mode in the broadband microwave channel front end and reasonably distributing and setting the gains of amplifiers at all stages and necessary filters, temperature compensation circuits and equalizers, and comprises the following steps:
a plurality of cascaded amplifiers;
an attenuator or an equalizer is connected between each stage of amplifiers in a cascade connection mode, and therefore circuit stability is improved.
The structure that an attenuator or an equalizer is cascaded between amplifiers of each stage comprises:
the input end of the first-stage amplifier is used as an input port of the front end of the broadband microwave channel for receiving radio-frequency signals;
a first fixed attenuator is connected between the first-stage amplifier and the second-stage amplifier;
a first temperature compensation attenuator is connected between the second-stage amplifier and the third-stage amplifier;
a second fixed attenuator is connected between the third-stage amplifier and the fourth-stage amplifier;
a first amplitude equalizer is connected between the fourth-stage amplifier and the fifth-stage amplifier;
and the fifth-stage amplifier, the second temperature compensation attenuator, the sixth-stage amplifier, the second amplitude equalizer and the second fixed attenuator are sequentially connected. The device at the front end of the broadband microwave channel is compensated with gain fluctuation under high and low temperatures through the temperature compensation attenuator, the amplitude equalizer is used for compensating the gain fluctuation of a circuit at the front end of the broadband microwave channel at the high and low ends of frequency, the second amplitude equalizer serving as the final-stage equalization ensures that the output power of the sixth-stage amplifier is consistent at the high and low ends of power when in saturated output, and the output power of the broadband microwave channel is in the optimal working range of the ultra-high speed sampling processing board serving as the digital sampling board.
The first-stage amplifier, the second-stage amplifier, the third-stage amplifier, the fourth-stage amplifier, the fifth-stage amplifier and the sixth-stage amplifier are all HMC462 type amplifiers;
the first amplitude equalizer and the second amplitude equalizer are both BWAES-6/18 type amplitude equalizers;
the first fixed attenuator and the second fixed attenuator are both ARN3590-3 type fixed attenuators;
the first temperature-compensation attenuator and the second temperature-compensation attenuator are both WTVA0200N07WB2 type temperature-compensation attenuators. The first-stage amplifier, the second-stage amplifier, the third-stage amplifier, the fourth-stage amplifier, the fifth-stage amplifier and the sixth-stage amplifier are all HMC462 type amplifiers of ADI company, and the HMC462 type amplifier is used as a broadband amplifier, has low noise coefficient, excellent band energy gain flatness and large dynamic range, and simultaneously has fully verified stability and reliability in a large number of applications. Between each stage of amplifier, a temperature compensation attenuator, a fixed attenuator and an amplitude equalizer are used as interstage matching and temperature and amplitude equalization respectively. And through reasonable circuit layout, the gain and fluctuation in the band at the front end of the broadband microwave channel in the full temperature range are ensured to be small, and the working stability can be kept. In an actual circuit, parasitic parameters of port matching and wire bonding have a larger influence on the high end of the frequency, so that the high end gain is designed to be higher in the design so as to compensate errors caused by the above factors. Thus, when the input of the radio frequency signal is-65 dBm, the power of the output signal is between-5 and +1 dB; when the signal is output in saturation, the maximum output power can be found to be between + 5dBm and +6dBm according to the saturated output curve of the amplifier and the frequency characteristic curve of the amplitude equalizer. Therefore, the output of the front end of the whole broadband microwave channel can meet the power interval of-5 dBm to +6dBm in a dynamic range.
Filters can also be cascaded between the amplifiers of each stage.
The performance analysis of the broadband microwave channel front end is as follows:
(a) low noise
The calculation of the noise coefficient is calculated according to the calculation formula (1) of the cascade noise coefficient:
the NF is the total noise coefficient of a cascade circuit at the front end of the broadband microwave channel; NFAThe noise coefficient of the first stage circuit; NFBThe noise coefficient of the second-stage circuit; NFCThe noise coefficient of the third stage circuit; NF(n)The noise coefficient of the nth stage circuit; the value of n can be 7; gAIs the gain of the first stage circuit; gBIs the gain of the second stage circuit, GcIs the gain of the third stage circuit, G(n-1)Is the gain of the (n-1) th stage circuit. n is a positive integer and can take a value of 7.
The first-stage circuit is often a 6-18 GHz broadband low-noise amplifier with a gain of 15dB (GA 102.5) used for amplifying pulse signals outside the front end of a broadband microwave channel, so that according to a calculation formula of a cascade noise coefficient, the influence of a later stage on the noise coefficient is small. The second stage circuit is a first stage amplifier, and the nth stage circuit is an nth-1 stage amplifier.
(b) Low stray
After the 6-18 GHz pulse signals are subjected to power division filtering by a filter outside the front end of the broadband microwave channel and are subjected to amplitude limiting, amplifying and filtering directly by the front end of the broadband microwave channel, harmonic signals of the pulses can be controlled to be below-10 dBc.
(c) Gain distribution/amplitude equalization
Corresponding microwave simulation design software can be adopted in the design to simulate each stage of circuit so as to ensure that the link gain distribution at the front end of the whole broadband microwave channel is reasonable and the amplitude fluctuation is balanced. The front end design of the broadband microwave channel comprises a large number of amplifiers, filters, limiting amplifiers and the like. Various microwave components have certain fluctuation, especially the gain of the filter sideband is reduced quickly, so that the amplitude fluctuation of the whole frequency band is very large, and in order to ensure the amplitude fluctuation in the bandwidth, an amplitude equalizer with a reasonable curve is arranged, so that the noise substrate and the amplitude fluctuation of a 6-18 GHz channel are ensured to be within +/-2 dB.
(d) Large dynamic range
In a sensitivity state, setting a gain level of an amplifier to enable an input pulse signal to pass through a DLVA to form a large dynamic DLVA radio frequency signal which is a DLVA minimum detectable signal; the output of the amplifier is set so that the radio frequency signal of the input large dynamic DLVA is the maximum detectable signal of the DLVA. Theoretically, the radio frequency signals entering the large dynamic DLVA are ensured to be within the dynamic range of the DLVA within the full input dynamic range, and the whole dynamic range of the single-bit receiving system is improved.
(e) Low power consumption and miniaturization
The number of hardware at the front end of the whole broadband microwave channel is relatively reduced, various processes are comprehensively integrated by adopting a microwave printing process technology, circuits such as a low-noise amplifier, a power amplifier and the like are integrated together, a power supply circuit adopts a low-dropout regulator, and the broadband microwave channel which is miniaturized, high in performance and low in power consumption is realized.
(f) Homologous coherent design
The frequency of the internal reference crystal oscillator at the front end of the broadband microwave channel is 40MHz, and when a 40MHz clock is accessed from the outside, the module can be automatically switched to an external clock working mode.
The sampling rate of the ultra-high speed sampling processing plate is 40 Gsps. The sampling rate of the ultra-high-speed sampling processing board is 40Gsps, so that the circuit function is simple, but the sampling rate of 40Gsps enables the routing of the clock and signal distribution circuit not to be processed according to the method of the lumped parameter circuit, and the transmission line effect, the mutual interference of the clock and signal distribution circuit and the interference between the clock and signal distribution circuit and other on-chip key signal paths, namely the signal integrity problem, should be considered. The sampling technology of the ultra-high speed sampling processing board is carried out on the premise of effective electromagnetic simulation and combined simulation analysis of measured data serving as high-speed signal simulation.
The ultra-high speed sampling processing board adopts a mode of scrambling the high-speed data line to avoid the long 1 and long 0 states of the data line, thereby further compressing the bandwidth of the data line and ensuring the opening of a data eye pattern. The method for scrambling the high-speed data line comprises the following steps:
generating a pseudo-random signal which is homologous with the sampling clock and is fixed in a certain set speed range, carrying out XOR operation on the pseudo-random signal and high-speed data obtained after the signal sent from the front end of the broadband microwave channel is processed by the ADC, and enabling the signal obtained after the XOR operation to enter a processor of the ultra-high speed sampling processing board after the signal passes through the high-speed XOR gate circuit so as to achieve the purpose of scrambling. During design of the ultra-high-speed sampling processing board, crosstalk among signals, pollution of noise of a switching power supply, signal integrity of a signal link and the like are fully considered, and a combined design of front simulation and rear simulation is performed. And testing the finished circuit of the ultra-high speed sampling processing board for the dielectric constant, impedance, insertion loss and the like of a real object, and then guiding a further simulation process by the measured parameters to design the ultra-high speed sampling processing board meeting the requirements.
The high-speed signal simulation comprises via hole optimization simulation, frequency domain simulation analysis and time domain simulation analysis;
the via optimization simulation is used for optimizing the size of the via, so that the impedance of the via meets the requirement of 100 ohms of differential impedance;
the frequency domain simulation analysis is used for checking the channel transmission condition according to the simulation signal channel characteristic;
the time domain simulation analysis is used for predicting the waveform of the signal so as to check whether the signal meets the standard requirement. The whole single-bit receiving system is in point-to-point communication, and the signal rate of a single channel serving as the output data rate of the ADC is 10 Gbps.
The via optimization simulation analysis specifically comprises:
according to the wiring condition of design, the wiring layer used by the high-speed signal is the 16 th layer, so that the via hole optimization is carried out on the layer; namely, a simulation result of the via optimization simulation is obtained according to the via model, and the optimal via size is found out by scanning the size of the relevant parameters of the via. Therefore, the size of the anti-bonding pad is changed, the impedance of the via hole is simulated and compared, and the result is like that: when the diameter of the via anti-pad is 40mil (the radius is 20mil), the impedance is optimal, and the impedance of the via passing through the simulation Art16 layer is optimally designed as follows:
1. via hole parameters: the aperture is-8 mil (at present, the impedance of the via hole is low, so the best processing requirement of the process is comprehensively considered, and the minimum aperture used for processing is selected);
2. pad parameters: the diameter of the bonding pad is-16 mil (the minimum process requirement is single-side 4 mil);
3. anti-pad parameters: the diameter of the reverse welding disc is-40 mil;
4. hole pitch parameters: the differential hole pitch was 40 mil.
The channel frequency domain analysis specifically includes:
testing the insertion loss to obtain an insertion loss simulation diagram:
the correspondingly selected plate material is usually required to achieve the insertion loss of the channel of the ultra-high-speed sampling processing plate under the condition of 10GHz frequency of 4.420dB and the return loss of-7.013 dB.
The ultra-high-speed sampling processing board comprises a low-speed ADC, a clock chip, a high-speed ADC, an FPGA chip, an ARM chip, an interface isolation chip and a photoelectric conversion module;
the low-speed ADC, the high-speed ADC, the ARM chip, the interface isolation chip and the photoelectric conversion module are all connected with the FPGA chip;
the high-speed ADC is connected with the clock chip and is used for receiving radio frequency signals;
the low-speed ADC is used for receiving a DLVA signal, and the DLVA signal is a signal obtained after the radio-frequency signal passes through DLVA.
The FPGA chip CAN be a Virtex-7 Virtex-7 Vx690T model FPGA chip, and the interface isolation chip is used for being connected with an LVDS interface, a CAN bus or an RS232 serial port;
the ARM chip is connected with the RS232 serial port;
the photoelectric conversion module is connected with the optical fiber.
The method of the single-bit receiving system comprises the following steps:
the ultra-wideband high-sensitivity instantaneous frequency measurement technology for the single-bit receiving system to carry out frequency domain detection is the core for realizing large bandwidth, high sensitivity and real-time processing. The corresponding frequency measurement algorithm needs to meet the requirements of broadband input and real-time performance, and also needs to be well adapted in the aspects of signal envelope extraction, narrow pulse adaptation, simultaneous arrival signal adaptation, frequency fine estimation and the like. When the algorithm is implemented, the optimization design is achieved as much as possible, the calculation amount and the complexity in the real-time processing process are reduced, and the consumption of hardware processing resources is reduced. The hardware platform is constructed aiming at the characteristics of the algorithm such as time sequence requirement, resource demand type, topological structure and the like on the basis of meeting the implementation of the algorithm. The software algorithm and the hardware processing platform are combined together efficiently. Meanwhile, the whole processing time sequence runs at high speed and reliably through reasonable distribution of hardware processing resources and reasonable layout and wiring constraint of logic resources.
The hardware platform corresponding to the algorithm part is a processor, and the processor adopts the FPGA chip as an FPGA processor. The pulse signal obtained by sampling the ultra-high speed sampling processing plate and the sampling data obtained by sampling the DLVA signal by an amplitude sampling circuit of a video signal are processed.
The method for processing the pulse signal obtained by sampling the ultra-high speed sampling processing plate and the sampling data obtained by sampling the DLVA signal by an amplitude sampling circuit of a video signal comprises the following steps:
step 1: the high-speed data receiving stage specifically comprises:
the ultra-high speed sampling processing board works at a signal transmission rate of 40Gbps to respectively sample and quantize pulse signals input from the front end of the broadband microwave channel, and the sampled and quantized digital signals are received and transmitted through a high-speed serial transceiver embedded in the FPGA chip; the receiving rate of the high-speed serial transceiver embedded in the FPGA chip is configured at 10.24Gbps, and the reference clock of the high-speed serial transceiver embedded in the FPGA chip is generated by frequency division of the associated clock of the ultra-high-speed sampling processing board, so that the data can be stably received by the GTH embedded in the FPGA chip without generating accumulated errors. The internal control logic of the FPGA chip firstly aligns received digital signals serving as sampling data to ensure the synchronization of the sampling data; secondly, the sequential switching of the sampling data is completed, because the randomness of the sampling clock phase can influence the change of the signal output sequence of the low-speed ADC or the high-speed ADC; finally, the adjusted data are sorted and integrated according to the sequence required by the algorithm, so that the integrated data are sent to a single-bit ultra-fast Fourier transform module to carry out the operation of single-bit ultra-fast Fourier transform after the clock domain synchronization is finished;
step 2: the single-bit ultra-fast Fourier transform FFT stage specifically comprises:
the single-bit ultrafast fourier transform is intended to reduce the complexity of the FFT by eliminating the multiplication operations in the FFT process. One simple way to eliminate the multiplication is to use a 1-bit ADC, which produces an output of only ± 1 (corresponding to the 1, 0 state of the bit), i.e., the input data to the FFT has only +1 and-1.
A discrete fourier transform DFT, which may be expressed as equation (2):
in the formula (2), x (N) is the N +1 th data in the input integrated data, N is the value obtained by adding one to the number of the integrated data, N and k are integers,
is a Kernel function; if the input x (n) is + -1, no multiplication is needed between the input integrated data and the Kernel Kernel function. If the FFT only requires addition and subtraction, the computational complexity required is greatly reduced. Another way to avoid multiplication by the FFT is to reduce the number of bits in the Kernel function to 1. The Kernel function is a complex function, and therefore, it is notCan be represented by a real number of 1 bit. The simplest way to represent the Kernel function is to represent the real part with 1 bit and the imaginary part with l bits. Mathematically, it can be expressed as formula (3):
the value of the Kernel function may be equal to one of the 4 values in equation (3). Under this condition, the FFT operation also does not require multiplication.
If represented graphically, the values of the Kernel function are distributed on a unit circle of the complex plane, the values of the Kernel function start from 1, and two adjacent points are spaced by an angle of 2 pi/N, where N is the number of integrated data as the number of points of the FFT. Fig. 10 shows the case where N is 8. In fig. 11, the value of the Kernel function adopts 1 bit to represent the real part and 1 bit to represent the imaginary part, so that the value of the Kernel function in the range of-pi/4 ≦ θ < pi/4 is quantized to 1; the value in the range of phi/4-theta <3 pi/4 is quantized to j; the value in the range of 3 pi/4 to theta <5 pi/4 is quantized to-1; the value in the range of 5 pi/4. ltoreq. theta <7 pi/4 is quantified as-j. Finally, the aim of instantaneous calculation is achieved by reducing the complexity of operation.
And step 3: a spectral peak search stage, which specifically comprises:
performing maximum spectrum search in an autocorrelation output result X (k) of discrete Boly transform DFT, namely performing modular operation on the autocorrelation output result X (k), comparing in each channel of an ultra-high-speed sampling processing board to obtain a maximum value after the modular operation, selecting complex information of the maximum value as a peak spectral line for extracting phase information, simultaneously sending the complex information to a frequency fine measurement module for performing frequency fine estimation, and applying a sliding FFT algorithm to a module of the peak spectral line and a determined threshold to obtain envelope information of an input signal for use in TOA and PW pulse width calculation;
by combining with a sliding FFT algorithm, the requirement of real-time flowing water rapid measurement on the high-speed sampling signal obtained by the ultra-high-speed sampling processing board can be met.
And 4, step 4: the frequency precision measurement stage specifically comprises the following steps:
in order to further improve the frequency measurement precision, the frequency value obtained by FFT is further precisely estimated by an instantaneous frequency measurement method; the instantaneous frequency measurement method is similar to the principle of an analog IFM receiver, the whole software algorithm part is carried out under a processing clock, the time interval of two FFT processing results is fixed, and the instantaneous frequency can be obtained by knowing the instantaneous phase difference of two beats.
And 5: a PDW formation phase, which comprises in particular:
and synchronously fusing the relative amplitude of the digital processing and the amplitude of the video sampling, and acquiring signal amplitude information while performing inter-channel harmonic suppression. And finally, synthesizing the frequency, the phase, the amplitude, the arrival time and the pulse width information into PDW (pulse width modulation) for output, wherein the design scheme only needs to output parallel frequency code data, and the step can be omitted.
Therefore, if a 40G high-speed ADC is adopted, the coverage of the maximum instantaneous bandwidth of 20G can be realized, so that 6-18 GHz radio frequency signals can be directly sampled, the frequency range of 6G-18 GHz can be instantaneously covered, and the frequency domain full interception can be realized. In terms of the sensitivity of the single-bit receiving system, the following is known:
the single-bit receiving system performs FFT operation on the sampled and quantized signal, transforms the signal from a time domain to a frequency domain for processing, and can simultaneously obtain information such as frequency, amplitude and the like of the signal. Because the radar signal has the characteristic of energy concentration in the frequency domain, the detection sensitivity can be greatly improved by utilizing FFT operation to detect the frequency domain. The sensitivity of the single-bit receiving system describes the minimum signal that the single-bit receiving system can detect and process, and is one of the most important technical indexes of the single-bit receiving system. In general, receiver sensitivity can be computed simply as:
S＝-114dBm+NF+101gBR+SNR
for the single-bit receiving system, the processing capacity SNR of the single-bit receiving system is-11 dB, the tentative system front-stage noise coefficient NF is 8dB, BR is 16GHz, and the parameters are substituted into the following formula:
S＝-114dBm+NF+101gBR+SNR
the sensitivity of the single-bit receiving system can be estimated as follows:
S＝-114dBm+8dB+42dB-11dB＝-75dBm。
the present invention has been described in an illustrative manner by the embodiments, and it should be understood by those skilled in the art that the present disclosure is not limited to the embodiments described above, but is capable of various changes, modifications and substitutions without departing from the scope of the present invention.
Claims (10)
1. A single-bit receiving system comprises a microwave channel front end and a sampling processing board;
the front end of the microwave channel is connected with the sampling processing plate;
the microwave channel is characterized in that a low noise amplifier is arranged at an input port used for receiving radio frequency signals at the front end of the microwave channel. And each stage of amplifier, filter, temperature compensation circuit and equalizer are arranged in the front end of the microwave channel.
2. The single-bit receiving system according to claim 1, wherein a structure of each stage of amplifier and filter, temperature compensation circuit and equalizer is provided in the front end of the microwave channel, comprising:
a plurality of cascaded amplifiers;
an attenuator or an equalizer is connected in series between each stage of amplifier.
3. The single-bit receiving system according to claim 2, wherein the structure in which an attenuator or an equalizer is connected in series between each stage of amplifiers includes:
the input end of the first-stage amplifier is used as an input port of the front end of the microwave channel for receiving radio-frequency signals;
a first fixed attenuator is connected between the first-stage amplifier and the second-stage amplifier;
a first temperature compensation attenuator is connected between the second-stage amplifier and the third-stage amplifier;
a second fixed attenuator is connected between the third-stage amplifier and the fourth-stage amplifier;
a first amplitude equalizer is connected between the fourth-stage amplifier and the fifth-stage amplifier;
and the fifth-stage amplifier, the second temperature compensation attenuator, the sixth-stage amplifier, the second amplitude equalizer and the second fixed attenuator are sequentially connected.
4. The single-bit receiving system of claim 3, wherein the first, second, third, fourth, fifth and sixth stage amplifiers are all HMC462 type amplifiers;
the first amplitude equalizer and the second amplitude equalizer are both BWAES-6/18 type amplitude equalizers;
the first fixed attenuator and the second fixed attenuator are both ARN3590-3 type fixed attenuators;
the first temperature-compensation attenuator and the second temperature-compensation attenuator are both WTVA0200N07WB2 type temperature-compensation attenuators.
5. A single bit receive system as claimed in claim 3, wherein filters can also be cascaded between the stages of amplifiers.
6. The single-bit reception system of claim 1, wherein the sampling rate of the sampling processing board is 40 Gsps.
7. The single-bit reception system of claim 1, wherein the superspeed sample processing board scrambles the high-speed data lines by:
generating a pseudo-random signal which is homologous with the sampling clock and is fixed in a certain set speed range, carrying out XOR operation on the pseudo-random signal and data obtained after the signal sent from the front end of the microwave channel is processed by the ADC, and enabling the signal obtained after the XOR operation to enter a processor of the ultra-high speed sampling processing board after the signal passes through the XOR gate circuit so as to achieve the purpose of scrambling.
8. The single bit reception system of claim 1, wherein the high speed signal simulation includes a via optimization simulation, a frequency domain simulation analysis, and a time domain simulation analysis;
the via optimization simulation is used for optimizing the size of the via, so that the impedance of the via meets the requirement of 100 ohms of differential impedance;
the frequency domain simulation analysis is used for checking the channel transmission condition according to the simulation signal channel characteristic;
the time domain simulation analysis is used for predicting the waveform of the signal so as to check whether the signal meets the standard requirement.
9. The single-bit receiving system of claim 1, wherein the ultra-high speed sampling processing board comprises a low speed ADC, a clock chip, a high speed ADC, an FPGA chip, an ARM chip, an interface isolation chip, and a photoelectric conversion module;
the low-speed ADC, the high-speed ADC, the ARM chip, the interface isolation chip and the photoelectric conversion module are all connected with the FPGA chip;
the high-speed ADC is connected with the clock chip and is used for receiving radio frequency signals;
the low-speed ADC is used for receiving a DLVA signal, and the DLVA signal is a signal obtained after the radio-frequency signal passes through DLVA;
the FPGA chip CAN be a Virtex-7 Virtex-7 Vx690T model FPGA chip, and the interface isolation chip is used for being connected with an LVDS interface, a CAN bus or an RS232 serial port;
the ARM chip is connected with the RS232 serial port;
the photoelectric conversion module is connected with the optical fiber.
10. A method for a single bit reception system, comprising:
processing a pulse signal obtained by sampling the ultra-high-speed sampling processing plate and sampling data obtained by sampling the DLVA signal through an amplitude sampling circuit;
the method for processing the pulse signal obtained by sampling the ultra-high speed sampling processing plate and the sampling data obtained by sampling the DLVA signal through the amplitude sampling circuit comprises the following steps of:
step 1: the high-speed data receiving stage specifically comprises:
the ultra-high speed sampling processing board works at a signal transmission rate of 40Gbps to respectively sample and quantize pulse signals input from the front end of the microwave channel, and the sampled and quantized digital signals are received and transmitted through a high-speed serial transceiver embedded in the FPGA chip; the internal control logic of the FPGA chip firstly aligns received digital signals serving as sampling data to ensure the synchronization of the sampling data; secondly, the sequential switching of the sampling data is completed, because the randomness of the sampling clock phase can influence the change of the signal output sequence of the low-speed ADC or the high-speed ADC; finally, the adjusted data are sorted and integrated according to the sequence required by the algorithm, so that the integrated data are sent to a single-bit ultra-fast Fourier transform module to carry out the operation of single-bit ultra-fast Fourier transform after the clock domain synchronization is finished;
step 2: the single-bit ultra-fast Fourier transform FFT stage specifically comprises:
a discrete Boyle transform DFT, expressed as equation (2):
in the formula (2), x (N) is the N +1 th data in the input integrated data, N is the value obtained by adding one to the number of the integrated data, N and k are integers,
is a Kernel function;
and step 3: a spectral peak search stage, which specifically comprises:
performing maximum spectrum search in an autocorrelation output result X (k) of discrete Boly transform DFT, namely performing modular operation on the autocorrelation output result X (k), comparing in each channel of an ultra-high-speed sampling processing board to obtain a maximum value after the modular operation, selecting complex information of the maximum value as a peak spectral line for extracting phase information, simultaneously sending the complex information to a frequency fine measurement module for performing frequency fine estimation, and applying a sliding FFT algorithm to a module of the peak spectral line and a determined threshold to obtain envelope information of an input signal for use in TOA and PW pulse width calculation;
and 4, step 4: the frequency precision measurement stage specifically comprises the following steps:
further fine estimation is carried out on the frequency value obtained by the FFT by using an instantaneous frequency measurement method;
and 5: a PDW formation phase, which comprises in particular:
and synchronously fusing the relative amplitude of the digital processing and the amplitude of the video sampling, and acquiring signal amplitude information while performing inter-channel harmonic suppression. And finally, synthesizing the frequency, the phase, the amplitude, the arrival time and the pulse width information into PDW for output.
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