CN113381777A

CN113381777A - Digital reconfigurable channelized single-bit receiver and implementation method thereof

Info

Publication number: CN113381777A
Application number: CN202110662479.5A
Authority: CN
Inventors: 季鹏飞; 张德平; 袁文韬; 江云
Original assignee: Hunan Guokelei Electronic Technology Co ltd
Current assignee: Hunan Guokelei Electronic Technology Co ltd
Priority date: 2021-06-15
Filing date: 2021-06-15
Publication date: 2021-09-10
Anticipated expiration: 2041-06-15
Also published as: CN113381777B

Abstract

The invention discloses a digital reconfigurable channelized single-bit receiver and a realization method thereof, wherein the receiver consists of an ultra-wideband single-bit receiver sampled at 38.4GHz and a reconfigurable digital channelized system; the ultra-wideband single-bit receiver for 38.4GHz sampling comprises a 38.4GHz ultra-high-speed single-bit ADC and an FPGA chip; the reconfigurable digital channelized system is embedded in an FPGA chip and comprises a system state machine, a coarse frequency measurement module and a fine frequency measurement module of a multiplexing frequency measurement algorithm module, and the fine frequency measurement module further comprises a single-bit digital frequency mixing module and a single-bit digital filtering module. The invention enables the single-bit receiver to have the advantages of high frequency measurement precision, high pulse width detection precision and the like through a reconfigurable digital channelization technology, is easy to realize by an FPGA (field programmable gate array), and has strong universality.

Description

Digital reconfigurable channelized single-bit receiver and implementation method thereof

Technical Field

The invention belongs to the technical field of single-bit receivers, and particularly relates to a digital reconfigurable channelized single-bit receiver and an implementation method thereof.

Background

The broadband signal frequency measurement is widely applied to the field of electronic reconnaissance. In order to adapt to the current complex electromagnetic environment, accurate frequency measurement needs to be carried out in a wider frequency band, along with the continuous improvement of the level of electronic devices, more and more ADCs meeting the bandwidth requirement are provided, the sampling rate of a low-bit ADC is higher and higher, and the appearance of a high-speed sampling device can break through the complex structure that a traditional frequency measurement receiver needs to firstly carry out frequency conversion on signals at a radio frequency end and then process intermediate-frequency signals at a digital end, so that the digital end of the receiver can directly obtain and process broadband radio frequency signals, and further the development of the receiver towards miniaturization and low power consumption is promoted. However, it is obvious that the pressure brought to a digital processing chip such as an FPGA by the ultra-high sampling rate is obvious, and at the present, under the condition of the same resource utilization rate, the frequency measurement result is more accurate when the ADC with the low sampling rate is used, and the frequency measurement accuracy is reduced by multiples along with the increase of the sampling rate when the ADC with the high sampling rate is used.

For a single-bit ADC with a high sampling rate, the most common high-speed single-bit signal frequency measurement algorithm at present is an instantaneous frequency measurement algorithm based on a delay correlation algorithm and a single-bit DFT or FFT (fast fourier transform) algorithm which reduces the operation amount by simplifying a kernel function of DFT (discrete fourier transform). The former saves resources, but has insufficient multi-signal processing capability and poor anti-noise capability; the latter can process a plurality of signals which are achieved simultaneously, but the calculation amount is still large, and particularly with continuous breakthrough of ADC sampling rate, the current algorithm does not have matching processing capacity.

Therefore, how to match and adapt to the data transmission rate of the single-bit ADC with an ultra-high sampling rate and ensure that the frequency measurement receiver has high frequency measurement precision is a technical problem to be solved urgently at present.

Disclosure of Invention

The invention aims to provide a digital reconfigurable channelized single-bit receiver and a realization method thereof, so as to solve the technical problems.

In view of the above object, the present invention provides in a first aspect a digitally reconfigurable channelized single bit receiver comprising: the digital reconfigurable channelized single-bit receiver consists of an ultra-wideband single-bit receiver sampled at 38.4GHz and a reconfigurable digital channelized system;

the ultra-wideband single-bit receiver for 38.4GHz sampling comprises a 38.4GHz ultra-high-speed single-bit ADC and an FPGA chip containing a high-speed transceiver module; wherein the content of the first and second substances,

the 38.4GHz ultra-high-speed single-bit ADC is used for collecting radio frequency signals at a sampling frequency of 38.4GHz, quantizing the radio frequency signals, and inputting quantized initial sampling data into the FPGA chip;

the FPGA chip is used for receiving the initial sampling data through the high-speed transceiver module, generating a first path of sampling data and a second path of sampling data, and inputting the two paths of sampling data to the reconfigurable digital channelized system;

the reconfigurable digital channelized system is embedded in an FPGA chip and comprises a system state machine, a coarse frequency measurement module and a fine frequency measurement module, wherein the coarse frequency measurement module and the fine frequency measurement module multiplex a frequency measurement algorithm module; the precision frequency measurement module also comprises a single-bit digital frequency mixing module and a single-bit digital filtering module; wherein the content of the first and second substances,

the system state machine is used for controlling the frequency measurement processes of the coarse frequency measurement module and the fine frequency measurement module according to the current state data of the system state machine;

the coarse frequency measurement module is used for performing frequency measurement calculation on the received first path of sampling data through the frequency measurement algorithm module when the current state data of the system state machine is in a coarse frequency measurement state, and inputting a coarse frequency measurement result obtained through calculation into the system state machine;

the system state machine is further configured to determine a frequency measurement channel according to the received coarse frequency measurement result, so as to control the single-bit digital frequency mixing module to generate local oscillation data corresponding to the frequency measurement channel;

and the fine frequency measurement module is used for performing digital channelization processing on the received second path of sampling data according to the local oscillation data generated by the single-bit digital frequency mixing module and the filter coefficient generated by the single-bit digital filtering module when the current state data of the system state machine is in a fine frequency measurement state, and performing frequency measurement calculation on the data subjected to digital channelization processing through the frequency measurement algorithm module to obtain a fine frequency measurement result corresponding to a frequency measurement channel.

Preferably, the coarse frequency measurement module further comprises a first FIFO buffer and a first shift register; wherein the content of the first and second substances,

the first FIFO buffer is used for performing second-level speed reduction and data caching on the first path of sampling data so as to reduce the associated clock of the first path of sampling data to 150MHz, and meanwhile, the first path of sampling data is output after being cached;

the first shift register is used for carrying out shift register on data output by the first FIFO buffer under a 150MHz clock;

the fine frequency measurement module further comprises a binarization processor, a second FIFO buffer and a second shift register; wherein the content of the first and second substances,

the binarization processor is used for carrying out binarization on the second path of data subjected to digital channelization processing to obtain binarization data;

the second FIFO buffer is used for carrying out secondary speed reduction and data caching on the binary data output by the binary processor so as to reduce the channel associated clock of the binary data to 150MHz, and meanwhile, the binary data is output after being cached;

the second shift register is used for carrying out shift register on the data output by the second FIFO buffer under a 150MHz clock;

the frequency measurement algorithm module multiplexed by the coarse frequency measurement module and the fine frequency measurement module comprises a split-radix FFT algorithm module, a maximum value detection module, a threshold detection module and an output decision module; wherein the content of the first and second substances,

the split-radix FFT algorithm module is configured to perform spectrum analysis on the data output from the first shift register or the data output from the second shift register to obtain spectrum data;

the maximum value detection module is used for carrying out maximum value detection according to the frequency spectrum data to obtain a maximum amplitude spectral line and the amplitude and frequency values of the maximum amplitude spectral line;

the threshold detection module is used for comparing the amplitude of the maximum amplitude spectral line with a corresponding threshold value, if the amplitude is larger than the threshold value, the output decision module is controlled to output the frequency value of the maximum amplitude spectral line as a frequency measurement result, and if the amplitude is not larger than the threshold value, the output decision module is controlled to set the frequency measurement result to zero.

Preferably, the system state machine in the reconfigurable digital channelized system comprises an internal register, a channel switching controller, a frequency measurement state controller, a two-way selector and a threshold register; wherein the content of the first and second substances,

the internal register is used for storing the frequency measurement result output by the frequency measurement algorithm module; wherein, the frequency measurement result comprises a coarse frequency measurement result and a fine frequency measurement result;

the channel switching controller is used for switching frequency measurement channels according to the coarse frequency measurement result, controlling the single-bit digital frequency mixing module to generate corresponding local oscillation data according to the switched frequency measurement channel, and determining a channel change state;

the frequency measurement state controller is used for acquiring current state data according to the silence state control data and the internal state control data, and controlling the double-path selector to select a group of data in the first shift register and the second shift register to be input into the frequency measurement algorithm module according to the current state data; the silent state control data is input from the outside and comprises two types of silent state starting and silent state closing; the internal state control data is generated internally and comprises a storage state of a second shift register, the channel change state generated by the channel switching controller and the frequency measurement result type output by the frequency measurement algorithm module;

the threshold register is used for storing and outputting the threshold value.

Preferably, the single-bit digital mixing module consists of a digital mixing register and a digital mixing calculation module; wherein the content of the first and second substances,

the digital frequency mixing register is used for storing local oscillation data of all set frequency points and controlling to output the local oscillation data corresponding to the frequency measurement channel by the system state machine;

and the digital frequency mixing calculation module is used for performing dot multiplication operation on the local oscillation data corresponding to the frequency measurement channel and the second path of sampling data to obtain frequency mixing data.

Preferably, the single-bit digital filtering module consists of a digital low-pass filtering register and a digital low-pass filtering calculation module; wherein the content of the first and second substances,

the digital low-pass filter register is used for storing low-pass filter coefficients;

and the digital low-pass filtering calculation module is used for performing point multiplication and accumulation on the frequency mixing data output by the digital frequency mixing calculation module and the low-pass filter coefficient to obtain channelized data.

Preferably, the digital reconfigurable channelized single-bit receiver further comprises a radio frequency interface module, a data interface module and a power control module; the radio frequency interface module is connected with the 38.4GHz ultrahigh-speed single-bit ADC, the data interface module is connected with the FPGA chip, and the power supply control module is respectively connected with the 38.4GHz ultrahigh-speed single-bit ADC and the FPGA chip; wherein the content of the first and second substances,

the radio frequency interface module is used for receiving a radio frequency signal and outputting the radio frequency signal to the 38.4GHz ultra-high-speed single-bit ADC;

the data interface module is used for outputting internal data of the FPGA chip and receiving external data;

the power supply control module comprises an ADC power supply for supplying power to the 38.4GHz ultra-high-speed single-bit ADC and a switch power supply for supplying power to the FPGA chip.

In a second aspect, the present invention provides a method for implementing a digital reconfigurable channelized single-bit receiver, including:

the method comprises the steps that an ultrahigh single-bit ADC collects radio frequency signals at a sampling frequency of 38.4GHz, and the radio frequency signals are subjected to quantization processing to obtain initial sampling data;

a high-speed transceiver module embedded in the FPGA chip receives the initial sampling data output by the ultrahigh single-bit ADC and generates a first path of sampling data and a second path of sampling data;

a reconfigurable digital channelized system embedded in an FPGA chip controls the frequency measurement flow of a coarse frequency measurement module and a fine frequency measurement module according to the current state data of a system state machine;

when the current state data of the system state machine is in a rough frequency measurement state, the rough frequency measurement module receives the first path of sampling data, and frequency measurement calculation is carried out on the first path of sampling data through the frequency measurement algorithm module to obtain a rough frequency measurement result;

the system state machine receives a coarse frequency measurement result output by the frequency measurement algorithm module, determines a frequency measurement channel according to the coarse frequency measurement result, and controls the single-bit digital frequency mixing module to generate local oscillation data according to the frequency measurement channel;

and when the current state data of the system state machine is in a fine frequency measurement state, receiving the second path of sampling data by a fine frequency measurement module, performing digital channelization processing on the second path of sampling data according to local oscillation data generated by the single-bit digital frequency mixing module and a filter coefficient generated by the single-bit digital filtering module, and performing frequency measurement calculation on the data subjected to digital channelization processing by the frequency measurement algorithm module to obtain a fine frequency measurement result corresponding to a frequency measurement channel.

Preferably, the frequency measurement process of the coarse frequency measurement module includes:

the first FIFO buffer performs second-level speed reduction and data caching on the first path of sampling data so as to reduce the associated clock of the first path of sampling data to 150MHz, and meanwhile, the first path of sampling data is output after being cached;

the first shift register shifts and registers the data output by the first FIFO buffer under a 150MHz clock;

when the current state data of the system state machine is in a rough frequency measurement state, a split-radix FFT algorithm module performs spectrum analysis on the data output by the first shift register to obtain frequency measurement data;

the maximum value detection module carries out maximum value retrieval on the frequency measurement data output by the split-radix FFT algorithm module to obtain a maximum amplitude spectral line and the amplitude and frequency values of the maximum amplitude spectral line;

the threshold detection module compares the amplitude of the maximum amplitude spectral line with a rough measurement threshold value, and if the amplitude is larger than the rough measurement threshold value, the output decision module outputs the frequency value of the maximum amplitude spectral line as a rough frequency measurement result.

Preferably, the frequency measurement process of the fine frequency measurement module includes:

the digital mixing calculation module reads local oscillation data corresponding to a frequency measurement channel in a digital mixing register to perform dot multiplication operation on the second path of acquired data to obtain mixing data;

the digital low-pass filtering calculation module reads a filter coefficient in a digital low-pass filtering register, and performs dot multiplication and accumulation on the frequency mixing data output by the digital frequency mixing calculation module to obtain channelized data;

a binarization processing module binarizes the channelized data output by the digital low-pass filtering calculation module to obtain binarized data;

the second FIFO buffer performs secondary speed reduction and data caching on the binary data output by the binary processor, so as to reduce the channel associated clock of the binary data to 150MHz, and meanwhile, the binary data is output after being cached;

the second shift register performs shift register on the data output by the second FIFO buffer under a 150MHz clock;

when the current state data of the system state machine is in a fine frequency measurement state, a split-radix FFT algorithm module performs spectrum analysis on the data output by the second shift register to obtain frequency measurement data;

the threshold detection module compares the amplitude of the maximum amplitude spectral line with a precision measurement threshold value, and if the amplitude is larger than the precision measurement threshold value, the output decision module outputs the frequency value of the maximum amplitude spectral line as a precision measurement result.

Preferably, the workflow of the system state machine includes:

the channel switching controller acquires a coarse frequency measurement result from an internal register, switches frequency measurement channels according to the coarse frequency measurement result, controls the single-bit digital frequency mixing module to generate corresponding local oscillation data according to the switched frequency measurement channel, and determines a channel change state at the same time;

the frequency measurement state controller outputs current state data according to the silence state control data and the internal state control data so as to control the output data of the two-way selector according to the current state data; the silent state control data is input from the outside and comprises two types of silent state starting and silent state closing; the internal state control data is generated internally and comprises a storage state of a second shift register, the channel change state generated by the channel switching controller and the frequency measurement result type output by the frequency measurement algorithm module.

The digital reconfigurable channelized single-bit receiver and the implementation method provided by the invention have the following beneficial effects:

(1) the digital reconfigurable channelized single-bit receiver has the advantages of an ultrahigh-bandwidth radio frequency receiving range in a frequency range of 0.5-18.5 GHz, simple structure, low power consumption, miniaturization, redesign of single-bit related application and the like; (2) the whole frequency measurement process is divided into a coarse frequency measurement process and a coarse frequency measurement process through a reconfigurable digital channelized system, and the channel is guided by the coarse frequency measurement result in real time to realize reconfiguration, so that accurate frequency measurement is completed, and the frequency measurement precision can be greatly improved with less resource cost on the basis of not reducing the performance of the existing single-bit frequency measurement algorithm; (3) the reconfigurable digital channelized system adopts a module unit with a parallel flow structure, so that parallel flow processing of the whole frequency measurement process can be realized, the real-time data processing capacity of the reconfigurable digital channelized system is ensured to be matched with the data transmission rate of a 38.4GHz ultra-high-speed single-bit ADC, data is further ensured not to be lost, and the pulse width detection precision and the frequency measurement reliability of a receiver can be further improved; (4) the digital reconfigurable channelized single-bit receiver can be applied to processing of multi-bit data, and universality is high.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.

Fig. 1 is a block diagram of a digital reconfigurable channelized single bit receiver according to an embodiment of the present invention;

FIG. 2 is a block diagram of a reconfigurable digital channelized system in an FPGA chip according to an embodiment of the present invention;

FIG. 3 is a flow chart of a method for implementing a digital reconfigurable channelized single-bit receiver according to an embodiment of the present invention;

fig. 4 is a frequency measurement process of the coarse frequency measurement module according to an embodiment of the present invention;

fig. 5 is a frequency measurement process of the fine frequency measurement module according to an embodiment of the present invention.

In the figure: 1-38.4GHz ultra-high-speed single-bit ADC; 2-FPGA chip; 3-a radio frequency interface module; 4-a data interface module; 5-a power supply control module; 10-a high-speed transceiver module; 20-a system state machine; 21-an internal register; 22-a channel switch controller; 23-a frequency measurement state controller; 24-a two-way selector; 25-threshold register; 30-a frequency measurement algorithm module; 31 a-a first FIFO buffer; 31 b-a second FIFO buffer; 32 a-a first shift register; 32 b-a second shift register; 33-split-radix FFT algorithm module; 34-a maximum detection module; 35-a threshold detection module; 36-output decision module; 40-single bit digital mixing module; 50-single bit digital filter module.

Detailed Description

In order to make the technical solutions of the present invention better understood, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

Referring to fig. 1 and fig. 2 together, an embodiment of the present invention provides a digital reconfigurable channelized single-bit receiver, which includes a 38.4GHz sampled ultra-wideband single-bit receiver and a reconfigurable digital channelized system.

In the embodiment, the 38.4GHz sampled ultra-wideband single-bit receiver comprises a 38.4GHz ultra-high-speed single-bit ADC1 and an FPGA chip 2 containing the high-speed transceiver module 10. Wherein, the 38.4GHz ultra-high-speed single-bit ADC1 is connected with the FPGA chip 2; the 38.4GHz ultra-high-speed single-bit ADC1 is used for acquiring radio frequency signals at a sampling frequency of 38.4GHz, quantizing the radio frequency signals, and inputting quantized initial sampling data into the FPGA chip 2; the FPGA chip 2 is used for receiving the initial sampling data through the high-speed transceiver module 10 embedded in the FPGA chip 2, generating a first path of sampling data and a second path of sampling data, and inputting the two paths of sampling data into the reconfigurable digital channelized system. Preferably, the first path of sampling data and the second path of sampling data are the same 128-bit sampling data.

The reconfigurable digital channelized system is embedded in the FPGA chip 2, and the design of the reconfigurable digital channelized system adopts a module unit of a parallel pipeline structure, which includes a system state machine 20, a coarse frequency measurement module (not shown) and a fine frequency measurement module (not shown) of a multiplexing frequency measurement algorithm module 30, and the fine frequency measurement module further includes a single-bit digital mixing module 40 and a single-bit digital filtering module 50.

The system state machine 20 is configured to control frequency measurement processes of the coarse frequency measurement module and the fine frequency measurement module according to current state data of the system state machine 20, receive a coarse frequency measurement result output by the coarse frequency measurement module, determine a frequency measurement channel according to the coarse frequency measurement result, and control the single-bit digital frequency mixing module 40 to generate local oscillation data corresponding to the frequency measurement channel; the coarse frequency measurement module is configured to perform frequency measurement calculation on the received first path of sampling data through the frequency measurement algorithm module 30 when the current state data of the system state machine 20 is in a coarse frequency measurement state, and input a coarse frequency measurement result obtained through the calculation into the system state machine 20; and the fine frequency measurement module is configured to, when the current state data of the system state machine 20 is in a fine frequency measurement state, perform digital channelization on the received second channel of sampling data according to the local oscillation data generated by the single-bit digital frequency mixing module 40 and the filter coefficient generated by the single-bit digital filtering module 50, and perform frequency measurement calculation on the data after the digital channelization through the frequency measurement algorithm module 30 to obtain a fine frequency measurement result corresponding to a frequency measurement channel. Preferably, the local oscillation data is 128-bit local oscillation data, and the 128-bit local oscillation data is updated along with the update of the 128-bit sampling data under the control of the system state machine 20, so that the integrity of the mixing data can be ensured and the generation of redundant clutter can be avoided.

It can be understood that, in this embodiment, the 38.4GHz ultra-high-speed single-bit ADC1 and the preset series of low-cost FPGA chips 2 are combined to form a 38.4GHz sampled ultra-wideband single-bit receiver hardware system with miniaturization and low power consumption, and the 38.4GHz sampled ultra-wideband single-bit receiver hardware system and the reconfigurable digital channelized software system are combined to form a digital reconfigurable channelized single-bit receiver. Preferably, the preset series of FPGA chips 2 is XC7K series of low-cost FPGA chips, which have abundant logic resources and external interface resources.

Specifically, the ultra-high-speed single-bit ADC1 receives a radio frequency signal within a frequency range of 0.5 to 18.5GHz, quantizes the radio frequency signal, acquires initial sampling data obtained by quantization through the high-speed transceiver module 10 in the FPGA chip 2, generates sequential 128-bit sampling data inside the FPGA chip 2, and performs first-stage speed reduction and data replication on the 128-bit sampling data, so as to reduce a channel associated clock of the 128-bit sampling data to a 300MHz clock, and replicate the 128-bit sampling data into two identical paths of 128-bit sampling data. Preferably, the one-step reduction is a 128-fold reduction.

Furthermore, one path of 128-bit sampling data of the two paths of completely identical 128-bit sampling data enters a coarse frequency measurement module in the reconfigurable digital channelization system as direct acquisition data, the other path of 128-bit sampling data enters a fine frequency measurement module in the reconfigurable digital channelization system, the 128-bit local oscillation data generated by a single-bit digital frequency mixing module 40 in the fine frequency measurement module is subjected to point multiplication, and then the point multiplication is performed on the 128-bit filtering coefficient generated by a single-bit digital filtering module 50 in the fine frequency measurement module and then the accumulation is performed to obtain channelization data, that is, data obtained by performing digital down-conversion and digital filtering on the second path of 128-bit sampling data is obtained, and a group of data in the direct acquisition data and the channelization data is further controlled by a system state machine 20 to enter a frequency measurement algorithm module 30 for frequency measurement calculation to obtain a frequency measurement result.

In summary, the digital reconfigurable channelized single-bit receiver of the embodiment has the following beneficial effects: (1) the digital reconfigurable channelized single-bit receiver has the advantages of an ultrahigh-bandwidth radio frequency receiving range in a frequency range of 0.5-18.5 GHz, simple structure, low power consumption, miniaturization, redesign of single-bit related application and the like; (2) the whole frequency measurement process is divided into a coarse frequency measurement process and a coarse frequency measurement process through a reconfigurable digital channelized system, and the channel is guided by the coarse frequency measurement result in real time to realize reconfiguration, so that accurate frequency measurement is completed, and the frequency measurement precision can be greatly improved with less resource cost on the basis of not reducing the performance of the existing single-bit frequency measurement algorithm; (3) the reconfigurable digital channelized system adopts a module unit with a parallel flow structure, so that parallel flow processing of the whole frequency measurement process can be realized, the data processing capability of the reconfigurable digital channelized system is ensured to be matched with the data transmission rate of a 38.4GHz ultra-high-speed single-bit ADC1, data is further ensured not to be lost, and the pulse width detection precision and the frequency measurement reliability of a receiver can be further improved; (4) the digital reconfigurable channelized single-bit receiver can be applied to processing of multi-bit data, and universality is high.

Referring to fig. 2, in an alternative embodiment, the coarse frequency measurement module further includes a first FIFO buffer 31a and a first shift register 32 a. The first FIFO buffer 31a in the coarse frequency measurement module is configured to perform second-level speed reduction and data caching on the first path of 128-bit sampled data, so as to reduce a channel associated clock of the first path of 128-bit sampled data to 150MHz, and output the first path of 128-bit sampled data after caching; the first shift register 32a is used for shift registering the data output by the first FIFO buffer 31a under the 150MHz clock. Preferably, the first FIFO buffer 31a is a FIFO with 128 bits in 256 bits out, and correspondingly, the data output by the first FIFO buffer 31a is 256 bits data; the first shift register 32a is a 512-bit register, and accordingly, the data output from the first shift register 32a is 256-bit data.

The fine frequency measurement module further includes a binarization processor (not shown), a second FIFO buffer 31b and a second shift register 32 b. The binarization processor in the fine frequency measurement module is used for binarizing the second channel of channelized data subjected to digital down-conversion, digital filtering and the like to obtain binarized data; the second FIFO buffer 31b is used for carrying out secondary speed reduction and data caching on the binary data output by the binary processor so as to reduce the channel associated clock of the binary data to 150MHz, and meanwhile, the binary data is output after being cached; and a second shift register 32b for shift registering the data output from the second FIFO buffer 31b at a clock of 150 MHz. Preferably, the binarization of the channelized data means that the channelized data is compared with a preset zero value, if the channelized data is greater than or equal to the preset zero value, a "1" is output, and otherwise, a "0" is output; the second FIFO buffer 31b is a FIFO with 1bit in and 2bit out, and correspondingly, the data output by the second FIFO buffer 31b is 2bit data; the second shift register 32b is a 512-bit register, and accordingly, the data output from the second shift register 32b is 256-bit data.

Understandably, the first path 128-bit sampling data entering the coarse frequency measurement module sequentially passes through the first FIFO buffer 31a with the 128-bit input and 256-bit output and the first shift register 32a with the 512-bit output, and then a first group of 512-bit data x is obtained₁(n), simultaneously entering a second path of 128-bit sampling data of the frequency precision measurement module, and sequentially passing through a binarization processor, a second FIFO buffer 31b with 1bit in and 2bit out and a second shift register 32b with 512bit to obtain a second group of 512-bit data x₂And (n), the two groups of 512-bit data are controlled by a system state machine 20 in the reconfigurable digital channelized system under a 150MHz clock, and one group of 512-bit data enters the multiplexed frequency measurement algorithm module 30 for further operation.

The coarse frequency measurement module and the fine frequency measurement moduleThe multiplexed frequency measurement algorithm module 30 includes a split-radix FFT algorithm module 33, a maximum detection module 34, a threshold detection module 35, and an output decision module 36. The split-radix FFT algorithm module 33 in the frequency measurement algorithm module 30 is used for processing the data x output from the first shift register 32a₁(n) or data x output from the second shift register 32b₂(n) performing spectrum analysis to obtain spectrum data; the maximum value detection module 34 is configured to perform maximum value detection according to the frequency spectrum data to obtain a maximum amplitude spectral line and an amplitude value and a frequency value of the maximum amplitude spectral line; the threshold detection module 35 is configured to compare the amplitude of the maximum amplitude spectral line with a corresponding threshold value (the threshold value is stored in the threshold register 25 in advance), and if the amplitude is greater than the threshold value, the output decision module 36 is controlled to output the frequency value of the maximum amplitude spectral line as a frequency measurement result, otherwise, the output decision module 36 is controlled to set the frequency measurement result to zero. Preferably, the spectrum data output by the split-radix FFT algorithm module 33 is 256-bit spectrum data. In a subsequent embodiment, a frequency measurement code may be generated from the frequency value of the maximum amplitude spectral line and input into the system state machine 20.

It can be understood that the split-radix FFT algorithm module 33 in the frequency measurement algorithm module 30 adopts a parallel pipeline structure, the control clock is homologous to the 150MHz clock, new 512-bit sampling data flows in and new 512-bit spectrum data flows out at each beat, and for each group of 512-bit spectrum data, the first half group of 256-bit spectrum data is input to the maximum value detection module 34. The first half group of 256-bit spectrum data comprises the following composition rules: first, a step frequency for frequency point marking is determined, which step frequency may be denoted as f_x＝[(F_s/2)/255]Wherein f is_xTo step frequency, F_sIs the sampling frequency of the radio frequency signal, "is a frequency of the radio frequency signal]"is a rounding function; then, 0 to F within the half band_s/2 at a stepped frequency f_xMarking frequency points to obtain 256 spectral lines, wherein each spectral line has corresponding amplitude and frequency values; finally, the 256 spectral lines are arranged from large to small according to the frequency value to form 256-bit spectral data, the spectral line at the first position in the 256-bit spectral data corresponds to the minimum frequency value, and the spectral line pair at the last positionThe maximum frequency value should be used. According to the composition rule, the embodiment performs frequency point marking in 0-19.125 GH by taking 75MHz as stepping frequency, and 256 spectral lines are obtained to form 256bit spectral data.

Further, the maximum value detection module 34 in the frequency measurement algorithm module 30 is composed of 9 stages of comparison modules in a parallel pipeline structure, each stage of comparison module is composed of comparison units, each comparison unit performs pairwise comparison to obtain spectral lines with larger amplitude values, the frequency values of the spectral lines with larger amplitude values in the frequency spectrum are stored, the spectral lines flow into the next stage of comparison module, and the final stage of comparison module outputs the maximum amplitude spectral lines and the frequency values of the maximum amplitude spectral lines in the frequency spectrum. Specifically, the first-stage comparison module is composed of 256 comparison units, the second-stage comparison module is composed of 128 comparison units, the second-stage comparison module is composed of 64 comparison units, the fourth stage is composed of 34 comparison units, the fifth-stage comparison module is composed of 16 comparison units, the sixth-stage comparison module is composed of 8 comparison units, the seventh-stage comparison module is composed of 4 comparison units, the eighth-stage comparison module is composed of 2 comparison units, and the ninth-stage comparison module is composed of 1 comparison unit.

Referring to fig. 2, in an alternative embodiment, the system state machine 20 in the reconfigurable digital channelized system includes an internal register 21, a channel switching controller 22, a frequency measurement state controller 23, a two-way selector 24 and a threshold register 25; the internal register 21 is configured to store frequency measurement results output by the frequency measurement algorithm module 30, including a coarse frequency measurement result and a fine frequency measurement result. Preferably, the internal register 21 is a five-stage register.

And the channel switching controller 22 is configured to perform switching between the frequency measurement channels according to the coarse frequency measurement result, so as to control the single-bit digital frequency mixing module 40 to generate corresponding local oscillation data according to the switched frequency measurement channel, and determine a channel change state at the same time. Preferably, the channel switching process of the channel switching controller 22 is: firstly, calling a coarse frequency measurement result continuously cached by a five-level register, comparing the coarse frequency measurement result with a frequency measurement result currently output by a frequency measurement algorithm module 30, if the content of a front four-level register is consistent with the current frequency measurement result and the frequency error between the content of a fifth-level register and the current frequency measurement result is greater than 150MHz clock, determining that a channel changes, outputting a channel code corresponding to the current frequency, and controlling a digital frequency mixing module 40 to output corresponding local oscillation data according to the channel code; otherwise, determining that the channel is not changed and maintaining the current channel coding unchanged. The channel switching controller 22 may control 255 frequency measurement channels, and the channel code output by the channel switching controller 22 is the coarse frequency measurement code minus one; the coarse frequency measurement code is the position of the maximum amplitude spectral line in the 256-bit spectral data output by the split-radix FFT algorithm module 33 in the coarse frequency measurement state, that is, when the maximum amplitude spectral line is at the nth position of the 256-bit spectral data, the coarse frequency measurement code is determined to be n, and accordingly, the channel code output by the channel switching controller 22 is n-1(n-1 is greater than or equal to 1), and particularly, if the current coarse frequency measurement code is 0, it is determined that there is no valid data in the input data, and the currently output channel code does not need to be changed; if the current channel coding changes, it is determined that the frequency measurement channel changes, and the channel change state may be input to the frequency measurement state controller 23, so that the frequency measurement state controller 23 switches the frequency measurement state according to the channel change state and the storage state of the second shift register 32 b.

The frequency measurement state controller 23 is used for determining current state data according to the silence state control data and the internal state control data, and controlling the two-way selector 24 to select a group of data in the first shift register 32a and the second shift register 32b to be input into the frequency measurement algorithm module 30 according to the current state data; the current state data comprises a coarse frequency measurement state, a fine frequency measurement state and a silence state; the mute state control data is externally input, and includes two types, namely, a mute state start and a mute state close, the internal state control data is internally generated, and includes a storage state (including a full state and a non-full state) of the second shift register 32b, a channel change state (including a changed state and a non-changed state), a frequency measurement result type (including two types, namely, a coarse frequency measurement result and a fine frequency measurement result) output by the frequency measurement algorithm module 30, and the like. Preferably, if the silence state control data is the start of the silence state, the control system state machine 20 enters the silence state, and outputs the silence state as the current state data; if the mute state control data is mute state off, the storage state of the second shift register 32b is full, and the channel change state is changed, the control system state machine 20 enters the fine frequency measurement state, and outputs the fine frequency measurement state as the current state data; if the silence state control data is a silence state off and the frequency measurement result type is a fine frequency measurement result, the control system state machine 20 enters a coarse frequency measurement state and outputs the coarse frequency measurement state as current state data. And preferably, if the current state data of the frequency measurement state controller 23 is in the coarse frequency measurement state, 512bit sampling data in the first shift register 32a is selected and input into the frequency measurement algorithm module 30; if the current state data of the frequency measurement state controller 23 is in the fine frequency measurement state, 512bit sampling data in the second shift register 32b is selected and input into the frequency measurement algorithm module 30; if the current status data of the frequency measurement status controller 23 is in the silent status, no data is input to the frequency measurement algorithm module 30.

And the threshold register 25 is used for storing and outputting threshold values, and the threshold values are divided into rough measurement threshold values and fine measurement threshold values. Preferably, the type of threshold value output by the threshold register 25 may be controlled by an internal counter provided in the system state machine 20, in which case the threshold register 25 outputs a rough-measured threshold value when the count of the internal counter does not reach the count node, and the threshold register 25 outputs a fine-measured threshold value when the count of the internal counter reaches the count node.

It can be understood that the system state machine 20 in this embodiment is provided with three frequency measurement states, which are a silent state, a coarse frequency measurement state and a fine frequency measurement state, wherein the silent state is controlled by the outside, and the coarse frequency measurement state and the fine frequency measurement state are automatically switched by the inside of the system state machine 20. When the system state machine 20 is in the silent state, the system state machine 20 controls the rest modules (including the coarse frequency measurement module, the fine frequency measurement module, the internal register 21 and the like) to be continuously reset; when the system state machine 20 is in a coarse frequency measurement state, the system state machine 20 controls data in the first shift register 32a to be input into the frequency measurement algorithm module 30, and continuously caches a coarse frequency measurement value output by the frequency measurement algorithm module 30 as a coarse frequency measurement result to the internal register 21, and simultaneously detects whether the second shift register 32b is full, if so, the system state machine 20 controls sampling data in the second shift register 32b to be input into the frequency measurement algorithm module 30; when the system state machine 20 is in the fine frequency measurement state, the system state machine 20 controls the data in the second shift register 32b to be input into the frequency measurement algorithm module 30, and controls the internal register 21 of the system state machine 20 to buffer the fine frequency measurement result at the correct time. Preferably, the system state machine 20 further includes an internal counter (not shown) for controlling the above-mentioned correct time and the threshold type output by the threshold register 25, at this time, when the sampling data starts to be input into the frequency measurement algorithm module 30, the internal counter is controlled to be cleared, and then counting is started at a clock beat of 150MHz to obtain the whole pipeline delay from data input to result output of the frequency measurement algorithm module 30, the delay is used as a counting node, when the counting of the internal counter reaches the counting node, the fine measurement frequency value output by the frequency measurement algorithm module 30 is buffered as the fine measurement frequency result into the internal register 21, and the frequency measurement state machine is switched to the coarse frequency measurement state, that is, only when the counting of the internal counter reaches the counting node, the frequency measurement algorithm module 30 outputs the fine measurement frequency result, and the rest of time are the coarse frequency measurement result, at this time, the ratio of the times of the fine frequency measurement and the coarse frequency measurement is 1: 256.

In an alternative embodiment, the single-bit digital mixing module 40 is comprised of a digital mixing register and a digital mixing calculation module. The digital frequency mixing register is used for storing local oscillation data of all set frequency points, and the system state machine 20 controls and outputs the local oscillation data corresponding to the frequency measurement channel; and the digital frequency mixing calculation module is used for performing dot product operation on the local oscillation data corresponding to the frequency measurement channel and the second path of sampling data and outputting frequency mixing data.

In this embodiment, the digital mixing register is a read-only memory of 254 × 65536bit, and can store 254 sets of local oscillation data corresponding to 254 channels. When the single-bit digital frequency mixing module 40 works in a 150MHz clock domain, frequency conversion is not needed, the output of the digital frequency mixing calculation module is all 1, 128-bit frequency mixing data of a 255 th channel are formed, and the 150MHz clock domain is between 0 and 150 MHz; if the single-bit digital mixing module 40 does not operate in the 150MHz clock domain, the local oscillation data generated by the digital mixing calculation module is generated by equation (1), where equation (1) is:

in the formula (1), x is local oscillation data, k is a spectral line position corresponding to a coarse measurement frequency value in a frequency spectrum, a value taking result of k is an integer between 0 and 255, and abs () is an absolute value function; n is.

When the digital frequency mixing calculation module works in a 300MHz clock, continuous 128bit data in the current local oscillation data are output at each clock beat. Specifically, a 65536-bit cyclic shift register stores the current local oscillation data, and outputs the data with a low 128-bit per beat, and simultaneously shifts the data with a low 128-bit to a high 128-bit of the cyclic shift register. When a channel change occurs, the corresponding 65536bit data is read from the digital mixing register as an address and stored in the circular shift register according to the channel code output by the channel switch controller 22 in the system state machine 20. In practice, the dot product operation in the digital mixing calculation module is an exclusive-nor operation of the 128-bit local oscillation data and the second path of 128-bit sampling data, which can reduce the calculation amount to save resources.

In an alternative embodiment, the single-bit digital filter module 50 is comprised of a digital low-pass filter register and a digital low-pass filter calculation module. The digital low-pass filter register is used for storing low-pass filter coefficients; and the digital low-pass filtering calculation module is used for performing point multiplication on the mixing data output by the digital mixing calculation module and the low-pass filter coefficient and then accumulating to obtain channelized data, namely, data obtained by performing digital down-conversion and digital filtering on the second path of sampling data.

In this embodiment, the single-bit digital filtering module 50 operates in a clock domain of 300MHz, and the operation process of the single-bit digital filtering module 50 is as follows: firstly, storing a 128-bit filter coefficient into a digital low-pass filter register in advance; then, under each clock beat, a 128-bit filter coefficient is read from a digital low-pass filter register through a digital low-pass filter calculation module, and is subjected to point multiplication and accumulation with 128-bit mixing data output by the digital mixing calculation module, so that data obtained by performing digital down-conversion and digital filtering on the 128-bit sampling data can be obtained. In practice, the dot product operation in the digital low-pass filter calculation module is to sign change the filter according to single-bit data, which is specifically expressed as: when the single-bit data is 0, the filter coefficient of the corresponding bit is inverted, otherwise, the filter coefficient of the corresponding bit is unchanged, so that the use of a multiplier can be avoided, resources can be saved, and the direct-current component in the point bit data can be removed.

Referring to fig. 1, in an alternative embodiment, the digital reconfigurable channelized single-bit receiver further includes a radio frequency interface module 3, a data interface module 4 and a power control module 5; the radio frequency interface module 3 is connected with the 38.4GHz ultra-high-speed single-bit ADC1, the data interface module 4 is connected with the FPGA chip 2, and the power supply control module 5 is respectively connected with the 38.4GHz ultra-high-speed single-bit ADC1 and the FPGA chip 2.

The radio frequency interface module 3 is configured to receive a radio frequency signal and output the radio frequency signal to the 38.4GHz ultra-high-speed single-bit ADC 1; a data interface module 4, configured to output internal data stored in the FPGA chip 2 (preferably, the internal data may be stored in the internal register 21 of the FPGA chip 2, including but not limited to a coarse frequency measurement result, a fine frequency measurement result, and the like), and receive external data (including but not limited to a program executable by the FPGA chip 2, silence state control data, and the like); the power control module 5 comprises an ADC power supply for supplying power to the 38.4GHz ultra-high-speed single-bit ADC1 and a switch power supply for supplying power to the FPGA chip 2.

In this embodiment, the digital reconfigurable channelized single-bit receiver mainly comprises a 38.4GHz ultra-high-speed single-bit ADC1, an FPGA chip 2, a radio frequency interface module 3, a data interface module 4 and a peripheral power control module 5. The radio frequency input module 3 adopts an SMP connector, and external radio frequency signals in a frequency range of 0.5-18.5 GHz can be input to the digital reconfigurable channelized single-bit receiver through the SMP connector; the radio frequency interface module 3 adopts an FMC connector, external data can be input into the digital reconfigurable channelized single-bit receiver through the FMC connector, and data generated by the digital reconfigurable channelized single-bit receiver is sent to a display terminal connected with the digital reconfigurable channelized single-bit receiver. Understandably, the digital reconfigurable channelized single-bit receiver has the advantages of simple structure, small volume, low power consumption, abundant logic resources and external interface resources, strong plasticity and good reusability, and can be used for secondary development under various applications.

In addition, referring to fig. 3, an embodiment of the present invention further provides a method for implementing a digital reconfigurable channelized single-bit receiver, where the digital reconfigurable channelized single-bit receiver is the receiver in the foregoing embodiment, and the method includes the following steps:

step S10, the ultra-high single-bit ADC1 acquires a radio frequency signal at a sampling frequency of 38.4GHz, and quantizes the radio frequency signal to obtain initial sampling data.

Step S20, the high-speed transceiver module 10 embedded in the FPGA chip 2 receives the initial sampling data output by the ultra-high single-bit ADC1, and generates a first path of sampling data and a second path of sampling data.

Step S30, the reconfigurable digital channelized system embedded in the FPGA chip 2 controls the frequency measurement processes of the coarse frequency measurement module and the fine frequency measurement module according to the current state data of the system state machine 20.

In step S40, when the current state data of the system state machine 20 is in the coarse frequency measurement state, the coarse frequency measurement module receives the first path of sampling data output by the high-speed transceiver module 10, and performs frequency measurement calculation on the first path of sampling data through the frequency measurement algorithm module 30 to obtain a coarse frequency measurement result.

In step S50, the system state machine 20 receives the coarse frequency measurement result output by the frequency measurement algorithm module 30, determines a frequency measurement channel according to the coarse frequency measurement result, and controls the single-bit digital frequency mixing module 40 to generate local oscillation data according to the frequency measurement channel.

Step S60, when the current state data of the system state machine 20 is in the fine frequency measurement state, the fine frequency measurement module receives the second path of sampling data output by the high-speed transceiver module 10, performs digital channelization on the second path of sampling data according to the local oscillation data generated by the single-bit digital frequency mixing module 40 and the filter coefficient generated by the single-bit digital filtering module 50, and then performs frequency measurement calculation on the data after the digital channelization through the frequency measurement algorithm module 30 to obtain a fine frequency measurement result corresponding to the frequency measurement channel.

Preferably, after the digital reconfigurable channelized single-bit receiver is powered on, the ultrahigh-level single-bit ADC1 starts to acquire radio frequency signals according to a sampling frequency of 38.4GHz, and performs single-bit quantization on the radio frequency signals to obtain initial sampling data, the FPGA chip 2 acquires the initial sampling data output by the ultrahigh-level single-bit ADC1 through the high-speed transceiver module 10, and completes first-stage speed reduction and data copying inside the FPGA chip 2 to obtain two paths of 128-bit sampling data which are completely the same, wherein one path of 128-bit sampling data is input into the coarse frequency measurement module as directly acquired data, the other path of 128-bit sampling data is input into the fine frequency measurement module, and is subjected to point multiplication with 128-bit local oscillation data generated by the single-bit digital mixing module 40, and then subjected to point multiplication with 128-bit filter coefficients generated by the single-bit digital filtering module 50 to obtain data obtained by performing digital down conversion and digital filtering on the 128-bit sampling data, i.e. channelized data, and further the system state machine 20 controls a group of input frequency measurement algorithm modules 30 in the directly collected data and channelized data to perform frequency measurement calculation, so as to obtain a frequency measurement result. Understandably, if directly collecting data is selected and input into the frequency measurement algorithm module 30 for frequency measurement calculation, a coarse frequency measurement result is obtained, and if channelized data is selected and input into the frequency measurement algorithm module 30 for frequency measurement calculation, a fine frequency measurement result is obtained.

Further, the receiver sends the coarse frequency measurement result or the fine frequency measurement result to a display terminal for displaying through the data interface module 4.

It can be understood that, in the implementation method of the digital reconfigurable channelized single-bit receiver in this embodiment, the entire frequency measurement process is divided into the coarse frequency measurement process and the coarse frequency measurement process by the reconfigurable digital channelized system, and the channel is guided in real time by the coarse frequency measurement result to implement reconfiguration, so as to complete fine frequency measurement, and therefore, the frequency measurement accuracy can be greatly improved with less resource cost on the basis of not reducing the performance of the existing single-bit frequency measurement algorithm.

Referring to fig. 4, in an alternative embodiment, the frequency measurement process of the coarse frequency measurement module, that is, step S40, may include the following steps:

in step S401, the first FIFO buffer 31a performs second-level speed reduction and data buffering on the first path of sample data, so as to reduce the associated clock of the first path of sample data to 150MHz, and at the same time, buffers and outputs the first path of sample data.

In step S402, the first shift register 32a performs shift register on the data output by the first FIFO buffer 31a under the 150MHz clock.

In step S403, when the current state data output by the system state machine 20 is in the coarse frequency measurement state, the split-radix FFT algorithm module 33 performs spectrum analysis on the data output by the first shift register 32a to obtain frequency measurement data.

In step S404, the maximum detection module 34 performs maximum retrieval on the frequency measurement data output by the split-basis FFT algorithm module 33 to obtain a maximum amplitude spectral line and the amplitude and frequency values of the maximum amplitude spectral line.

In step S405, the threshold detection module 35 compares the amplitude of the maximum amplitude spectral line with the rough measurement threshold, and if the amplitude is greater than the rough measurement threshold, the output decision module 36 outputs the frequency value of the maximum amplitude spectral line as the rough frequency measurement result.

Preferably, the 128-bit sampling data input to the coarse frequency measurement module is subjected to secondary speed reduction and shift register sequentially through a first FIFO buffer 31a with 128-bit input and 256-bit output and a 512-bit first shift register 32a to obtain a group of 512-bit data, when the system state machine 20 enters the coarse frequency measurement state, the system state machine 20 controls the set of 512bit data to be input into the frequency measurement algorithm module 30, and then the spectrum analysis and the maximum value detection are performed sequentially by the split-radix FFT algorithm module 33 and the maximum value detection module 34 to obtain the maximum amplitude spectral line and the amplitude and frequency values of the maximum amplitude spectral line, the threshold detection module 35 compares the amplitude of the maximum amplitude spectral line with the rough-measured threshold value stored in the threshold register 25, and if the amplitude is larger than the rough-measured threshold value, the output decision module 36 outputs the frequency value of the maximum amplitude spectral line as a coarse frequency measurement result, otherwise, the output decision module 36 sets the output result to zero. It can be understood that, in this embodiment, the coarse frequency measurement process adopts parallel pipeline operation, which ensures that the data processing capability of the reconfigurable digital channelization system matches with the data transmission rate of the 38.4GHz ultra-high speed single-bit ADC1, and can ensure that data is not lost, thereby further improving the pulse width detection precision and the frequency measurement reliability of the receiver.

Referring to fig. 5, in an alternative embodiment, the frequency measurement process of the fine frequency measurement module, that is, step S60, may include the following steps:

step S601, the digital mixing calculation module reads local oscillation data corresponding to the frequency measurement channel in the digital mixing register to perform dot product operation on the second path of acquired data to obtain mixing data.

Step S602, the digital low-pass filtering calculation module reads the filter coefficient in the digital low-pass filtering register to perform dot multiplication and accumulation on the mixing data output by the digital mixing calculation module, so as to obtain channelized data.

Step S603, the binarization processing module binarizes the channelized data output by the digital low-pass filtering calculation module to obtain binarized data.

In step S604, the second FIFO buffer 31b performs second-level speed reduction and data buffering on the binarized data output by the binarizing processor, so as to reduce the channel clock of the binarized data to 150MHz, and at the same time, outputs the binarized data after buffering.

In step S605, the second shift register 32b performs shift register on the data output from the second FIFO buffer 31b under the 150MHz clock.

In step S606, when the current state data output by the system state machine 20 is in the fine frequency measurement state, the split-radix FFT algorithm module 33 performs spectrum analysis on the data output by the second shift register 32b to obtain frequency measurement data.

In step S607, the maximum detection module 34 performs maximum value search on the frequency measurement data output by the split-basis FFT algorithm module 33 to obtain the maximum amplitude spectral line and the amplitude and frequency values of the maximum amplitude spectral line.

In step S608, the threshold detection module 35 compares the amplitude of the maximum amplitude spectral line with the fine measurement threshold, and if the amplitude is greater than the fine measurement threshold, the output decision module 36 outputs the frequency value of the maximum amplitude spectral line as a fine measurement result.

Preferably, the 128-bit sampling data input to the fine frequency measurement module is subjected to digital down-conversion and digital filtering through a digital frequency mixing calculation module and a digital low-pass filtering calculation module to obtain channelized data, the channelized data is subjected to binarization processing and then input to a second FIFO buffer 31b for secondary speed reduction, and finally the second shift register 32b is subjected to shift registration to obtain a group of 512-bit data, when the system state machine 20 enters a fine frequency measurement state, the system state machine 20 controls the group of 512-bit data to be input to the frequency measurement algorithm module 30, and performs spectrum analysis and maximum value detection through a split-base FFT algorithm module 33 and a maximum value detection module 34 in sequence to obtain a maximum amplitude spectral line and an amplitude value and a frequency value of the maximum amplitude spectral line, the detection module 35 compares the amplitude value of the maximum amplitude spectral line with a fine measurement threshold value stored in the threshold register 25, if the maximum amplitude spectral line is greater than the predetermined value, the output decision module 36 outputs the frequency value of the maximum amplitude spectral line as a fine frequency measurement result, otherwise, the output decision module 36 sets the output result to zero. In the embodiment, the precise frequency measurement process adopts parallel pipeline operation, so that the data processing capability of the reconfigurable digital channelized system is ensured to be matched with the data transmission rate of the 38.4GHz ultra-high-speed single-bit ADC1, the data can be ensured not to be lost, and the pulse width detection precision and the frequency measurement reliability of the receiver are further improved.

In an alternative embodiment, the work flow of the system state machine 20, that is, the step S40, may include the following steps:

in the first step, the channel switching controller 22 obtains the coarse frequency measurement result from the internal register 21, and performs switching between frequency measurement channels according to the coarse frequency measurement result, so as to control the single-bit digital frequency mixing module 40 to generate corresponding local oscillation data according to the switched frequency measurement channel, and at the same time, determine the channel change state.

Step two, the frequency measurement state controller 23 outputs current state data according to the silence state control data and the internal state control data, so as to control the output data of the two-way selector 24 according to the current state data; the silent state control data is input from the outside and comprises two types of silent state starting and silent state closing; the internal state control data is internally generated, and includes the storage state of the second shift register 32b, the channel variation state generated by the channel switching control 22, and the frequency measurement result type output by the frequency measurement algorithm module 30.

Preferably, for the channel switching controller 22, when the system state machine 20 is in the coarse frequency measurement state, the channel switching controller 22 calls the coarse frequency measurement result from the internal register 21 to compare with the coarse frequency measurement result currently output by the frequency measurement algorithm module 30, and if the channel is determined to change according to the comparison result, the channel coding of the frequency measurement channel after switching is determined according to the current frequency; if the channel is not changed according to the comparison result, the current channel code is maintained, and further the system state machine 20 controls the single-bit digital frequency mixing module 40 to generate corresponding local oscillation data according to the channel code and generates a channel change state according to whether the channel is changed.

For the frequency measurement state controller 23, it is first detected whether the silent state is on, that is, whether the silent state control data is on or off, if the silent state is on, the system state machine 20 is controlled to enter the silent state, and the silent state is output as the current state data, at this time, the data of the first shift register 32a and the second shift register 32b are not selected to enter the frequency measurement algorithm module 30.

If the silent state is turned off, it is further detected whether the frequency measurement channel changes, that is, it is determined whether the channel change state is channel change or channel non-change, if the channel change state is channel change, when the second shift register 32b is full, the system state machine 20 is controlled to enter the fine frequency measurement state, and the fine frequency measurement state is output as current state data, and at this time, the system state machine 20 controls the data of the second shift register 32b to enter the frequency measurement algorithm module 30. Otherwise, it is determined that the system state machine 20 is still in the coarse frequency measurement state, and the coarse frequency measurement state is output as the current state data, at this time, the system state machine 20 controls the data of the first shift register 32a to enter the frequency measurement algorithm module 30. In addition, when the mute state is turned off, if the system state machine 20 receives a fine frequency measurement result, the system state machine 20 is controlled to enter the coarse frequency measurement state.

In this embodiment, according to two requirements of coarse frequency measurement and fine frequency measurement, the frequency measurement state controller 23 controls the system state machine 20 to enter different frequency measurement states and output corresponding current state data, and then a group of data in the direct sampling data and the channelized data is selected according to the current state data and input into the multiplexed frequency measurement algorithm module 30 for frequency measurement, so as to achieve the reconfigurable purpose. In addition, the frequency measurement channel is adjusted by the channel switching controller 22, so that the precise frequency measurement is realized.

Those of ordinary skill in the art will understand that: the discussion of any embodiment above is meant to be exemplary only, and is not intended to intimate that the scope of the disclosure, including the claims, is limited to these examples; within the idea of the invention, also technical features in the above embodiments or in different embodiments may be combined and there are many other variations of the different aspects of the invention as described above, which are not provided in detail for the sake of brevity. Therefore, any omissions, modifications, substitutions, improvements and the like that may be made without departing from the spirit and principles of the invention are intended to be included within the scope of the invention.

Claims

1. A digital reconfigurable channelized single-bit receiver is characterized by consisting of a 38.4GHz sampled ultra-wideband single-bit receiver and a reconfigurable digital channelized system;

the FPGA chip is used for receiving the initial sampling data through a high-speed transceiver module embedded in the FPGA chip, generating a first path of sampling data and a second path of sampling data, and inputting the two paths of sampling data to the reconfigurable digital channelized system;

2. The digital reconfigurable channelized single bit receiver of claim 1 wherein said coarse frequency measurement block further comprises a first FIFO buffer and a first shift register; wherein the content of the first and second substances,

3. A digital reconfigurable channelized single bit receiver according to claim 2 wherein said system state machine in said reconfigurable digital channelized system includes internal registers, channel switching controller, frequency measurement state controller, two-way selector and threshold register; wherein the content of the first and second substances,

the threshold register is used for storing and outputting the threshold value.

4. The digital reconfigurable channelized single bit receiver of claim 1 wherein said single bit digital mixing block is comprised of a digital mixing register and a digital mixing computation block; wherein the content of the first and second substances,

5. The digital reconfigurable channelized single bit receiver of claim 4 wherein said single bit digital filter block is comprised of a digital low pass filter register and a digital low pass filter calculation block; wherein the content of the first and second substances,

6. The digital reconfigurable channelized single bit receiver of claim 1 further comprising a radio frequency interface module, a data interface module and a power control module; the radio frequency interface module is connected with the 38.4GHz ultrahigh-speed single-bit ADC, the data interface module is connected with the FPGA chip, and the power supply control module is respectively connected with the 38.4GHz ultrahigh-speed single-bit ADC and the FPGA chip; wherein the content of the first and second substances,

7. A method for implementing a digitally reconfigurable channelized single bit receiver, comprising:

8. The method of claim 7, wherein the frequency measurement procedure of the coarse frequency measurement module comprises:

9. The method of claim 7, wherein the frequency measurement procedure of the fine frequency measurement module comprises:

the digital low-pass filtering calculation module reads a low-pass filter coefficient in a digital low-pass filtering register, and performs point multiplication and accumulation on the frequency mixing data output by the digital frequency mixing calculation module to obtain channelized data;

10. The method of claim 8, wherein the system state machine workflow comprises:

the frequency measurement state controller outputs current state data according to the silent state control data and the internal state control data, so as to control the double-path selector to select a group of data in the first shift register and the second shift register to be input into the frequency measurement algorithm module according to the current state data; the silent state control data is input from the outside and comprises two types of silent state starting and silent state closing; the internal state control data is generated internally and comprises a storage state of a second shift register, the channel change state generated by the channel switching controller and the frequency measurement result type output by the frequency measurement algorithm module.