FI85076C - Digital radio frequency receiver - Google Patents

Description

1 85076

Digital radio frequency receiver

FIELD OF THE INVENTION This invention relates to radio communication area 5, and more particularly to a radio frequency receiver substantially implemented in digital circuitry.

Background of the invention

Conventional radio communication equipment is implemented mainly on analog circuitry. The intrinsic properties of the analog 10 components limit the amount of signal processing possible. For example, the noise and gain characteristics of analog amplifiers limit the dynamic range of the processed analog signal. In addition, analog information cannot be easily stored in a manner that allows for advanced signal processing.

The use of digital signal processing to replace operations previously performed using analog processing eliminates unwanted variations in these operations that may result from external influences such as temperature, humidity, and aging of analog components. In addition, digital signal processing technologies provide flexibility in the form of programmable functionalities and features. For example, an integrated digital intermediate frequency (IF) circuit should be programmed up to its channel frequency, its sampling frequency, and, to a certain extent, its filter response. A digital signal processor (DSP) that performs alternating stored programs can perform different filtering and demodulation to implement completely different types of radios. The DSP can also be used for advanced processing techniques, such as adaptive correction.

35 An additional advantage of the digital receiver structure is that the DSP and IF circuitry can be designed so that it can be "inverted" to perform similar operations on a digitally implemented transmitter. For bidirectional (half-duplex) operation, the circuitry could be connected to simply reverse the "direction", while for bidirectional operation, two intermediate frequency filters would be required.

The basic technological aid that essentially leads to the feasibility of a digital receiver is a high-speed (20-100 MHz) high-resolution 10-bit (10-12 bit) A / D converter. Another factor that leads to the technical feasibility of a digital receiver structure is the high level of integration and high speeds achievable in VLSI integrated circuit implementations, which in extreme cases allow, for example, a 4-na-15 (4-zero) dual-precision digital filter with 40 kHz sampling frequency, the implementation of the current digital signal processor. The present invention combines these new technologies with improved techniques for providing a feasible model for front-end analog processing and digital intermediate frequency filtering for a substantially digital receiver.

The receiver structure of the present invention enables a revolutionary change in the production technology and operating characteristics of travel radios. In addition, this approach allows the radio to be built with a minimal number of parts, which immediately reduces parts and manufacturing costs while also improving the reliability and maintainability of the radio.

30 Summary and Objects of the Invention

In summary, the present invention contemplates a fully digital radio receiver that operates on a received radio frequency signal that has been converted to digital form after preselection at the antenna output. The receiver of the present invention comprises a preselector, a high speed analog-to-digital converter (A / D), a digitally implemented intermediate frequency selectivity (IF) section having a substantially baseband output signal, and integrated circuits of a multi-purpose digital signal processor (DSP), perform the final selectivity or smoothing, demodulation, and post-demodulation processing.

Thus, it is an object of the present invention to provide a digitally implemented radio receiver.

Another object of the present invention is to provide a radio receiver structure that is easily adapted to receive a plurality of transmission schemes.

It is a further object of the present invention to provide a radio receiver structure substantially implemented using integrated circuit techniques.

It is a further object of the present invention to provide an intermediate frequency filter structure for a digital receiver that operates at a relatively fast speed so as to reduce the resolution and step size requirements in the A / D converter.

20 Brief Description of the Drawings

Fig. 1 is a block diagram showing the functions of the digital receiver of the present invention.

Figure 2 is a block diagram of the front end circuitry of a digital receiver * of the present invention.

Fig. 3 is a block diagram of a digital zero-type intermediate frequency selectivity portion of the present invention.

Figure 4a is a block diagram of the digital oscillator referred to in Figure 1.

Fig. 4b is a block diagram of a pseudo-random vibration generator compatible with the digital zero-type intermediate frequency selectivity portion * - * 'of Fig. 3.

:: Figure 5a is a block diagram of a desired "fast", two-way low pass filter.

4 85076

Figure 5b is a block diagram of a scattered approximation for the fast low pass filter of Figure 5a.

Figures 6a to 6d are frequency diagrams showing the characteristics of the fast low pass filters of Figure 5.

Fig. 7 is a block diagram of a second order narrowband infinite impulse response (IIR) low pass filter used in the distributed "fast" low pass filters of Fig. 5b.

Fig. 8 is a block diagram of a finite impulse response 10 (FIR) second order filter with an attenuation well halfway through the sampling frequency used in the distributed low pass filters of Fig. 5b.

Figures 9a-9c are block diagrams of a time division multiplexed plexed second stage IIR low pass filter used in the time division multiplexed "slow" low pass filters described in connection with Figure 3.

Figure 10 is a block diagram of a fifth order FIR sub-pass filter used to further reduce the sampling frequency from 80 kHz to 50 kHz.

Figure 11 is a block diagram of a fourth order IIR sub-pass filter used for final selectivity and passband equalization prior to demodulation.

Figure 12 is a block diagram of an FM demodulator implemented with a general purpose DSP.

Figures 13a to 13c are diagrams showing the principles of pointers in the context of the present invention.

Figs. 14a and 14b are flow charts showing the operation of the FM router of the FM demodulator of the present invention.

Figures 15a to 15b are flow charts of the operation of the scaling routine described in connection with Figure 15a.

: Figs. 16a to 16c are flow charts showing. operate the other parts of the digital demodulator 35 of the present invention.

5 85076

Detailed explanation of the drawings

Figure 1 illustrates the functions of a digital receiver comprising three main operations. Although the diagram does not provide any example of receiver variability, it will be apparent to one skilled in the art that various, diverse implementations could be applied to the receiver of the present invention. In more detail, the "front end" section 104, further shown in more detail in Figure 2, connects the antenna 102, which receives the radio frequency (RF) signal, to a digitally implemented intermediate frequency selectivity section 110. The preselector 106 provides wideband filtering of the incoming signal to prevent false aliasing. the transformation process. The A / D block 108 includes the gain-15 and sampling and hold operations necessary for digital processing of the present receiver structure.

The next main part, the intermediate frequency selectivity part 110, which will be described in more detail below in connection with Fig. 3, comprises a quadrature local oscillator (LO) 116 which generates a complex exponential signal (quadrature signals sine and cosine). The frequency of this signal is selected by the system channel input "A", quadrature mixers 112 are used as digital multipliers to frequency shift the desired narrowband channel down to an intermediate frequency of about 0 Hz. The high speed selectivity section 114 includes several:. successive narrowband low-pass filter portions that remove unwanted signals at higher frequencies from a desired signal centered near zero frequency. This low-pass filtering allows the incremental sampling frequency to be reduced from the high frequencies at the output of the A / D converter 108 to frequencies comparable to the input at the "end" portion 120 of the channel bandwidth.

6 85076 The "end end" section 120 is used to "specialize" a general purpose radio structure into a single structure specifically tailored to a particular radio application, designated radio type input "B" of the system. 5 Its best implementation may comprise a general purpose digital signal processor (DSP). The final selectivity section 124 provides all the additional filtering required before demodulating the radio signal according to the modulation type and channel characteristics. For example, it may ai-10 include adaptive channel correction for a digital data transmission system. This filter section 124 also provides adjacent channel attenuation and passband correction to compensate for imperfections in the properties of the high-speed selectivity filters 114 resulting from the coarse-coefficient quantization required to implement multiplicative (sub-pass) filters. The deraodulation section 126 may be programmed to implement many types of demodulation, including FM demodulation for audio and AC frequency modulated 20 (FSK) data. The demodulated audio signal may be converted back to analog form, then amplified and reproduced through a speaker, as suggested by reference numerals 121 and 122. Alternatively, di-. the digital voice message can be stored digitally: 25 in digital memory 123 for later playback. Data transfers in a computer system (not shown), demodulated data symbols ... may be routed to a computer for further processing or to a computer terminal for immediate display. In addition, control information for implementing the automatic frequency tracking-30 nan 128 may be generated "end end" -. finally, the clock generating section 118 is needed to control the input sampling frequency of the A / D conversion required for accurate downconversion, to use: digital circuitry in a regular manner, and to control the output sampling frequency, perhaps for synchronization with later systems. In the exemplary embodiment described herein, the sampling frequency f is assumed to be 20 MHz and the band of receivable frequencies is centered at about 875 MHz.

Figure 2 is a schematic diagram of the front end circuitry of the di-5 digital receiver of the present invention. This circuitry works to digitize the selected band of radio frequency signals. The present invention provides that sampling is performed directly at radio frequencies. However, wideband preselection has been performed with radio frequency 10 analog filters prior to sampling. The operation of the radio frequency filters 202 and 206 is to provide selectivity for interference responses. These include häiriövasteet the image side of the intermediate frequency bursts, Able Baker bursts etc., as found in conventional receiver front end. In addition to these 15 bursts, selectivity must be provided for frequencies that can be falsified by the sampling process. The maximum allowable bandwidth is limited to the Nyquist bandwidth (fs / 2, where f is the sampling frequency), although this is significantly reduced by practical filters.

The use of the 2-pole and 5-pole filters shown in Figure 2, each with a bandwidth of about 4 MHz, provides greater than 90 dB attenuation for false-repeated frequencies when sampling at 20 MHz. In addition to providing selectivity; V; for signals entering the antenna 224, the filter 206 band-limits the wideband noise generated by the radio frequency amplifier 204 to the first sampling and holding circuit 208. This is necessary to prevent false reproduction of the noise 30, which effectively increases the noise factor of the front end 200. The radio frequency preamplifier 204 is used to amplify the radio frequency signal to a level sufficient to provide the necessary signal-to-noise ratio required for system sensitivity. Because different filters are required for different bands, it is practical to include a radio frequency amplifier 204 8 85076 as part of the filter structure (202 and 206). The receiver of the present invention comprises a radio frequency amplifier 204 having an amplification of about 28 dB and a noise factor of about 5 dB.

The clock 212 and the sampling pulse generator 210 5 provide clock signals and sampling pulses to the first sampling and holding circuit 208, the second sampling and holding circuit 220, the analog-to-digital converter 222, and the digital zero type intermediate frequency selectivity portion (not shown). Clock generation can be accomplished with a 20 MHz crystal oscillator, which is widely available. The 40 MHz signal for use by a digital signal processor (not shown) is derived by doubling the 20 MHz signal with an analog doubling circuit.

Pulse generator 210 is used to shape the 15 MHz clock signal (approximately sinusoidal) into very narrow pulses. The width of the sampling pulse depends on the largest frequency band to be received. A pulse width of about 300 picoseconds generates a harmonic "comb" with an approximately flat ampli-20 tudi up to about 1 GHz. This is necessary for operation of the receiver of the present invention at an operating frequency of about 875 MHz. Pulse generation can be performed using a conventional step reset diode and ringing circuit. This type of circuit is described in Harmonized Generation Using Step Recovery Diodes and SRD modules, Hewlett Packard Application note 920, available from the Hewlett Packard Microwave Semiconductor Division, 350 Trimble Rd., San Jose,

Ca., 95131.

30 The band of signals amplified and selected by blocks 202, 204 and 206 is sampled for the first on the sampling and holding circuit 208. This is analogous to the downconversion of a conventional radio frequency receiver. Although the flash-type analog-to-digital converter 35 efficiently samples the signal, practical converters have band-limited inputs, thus requiring sampling prior to conversion. Also to this day, all known high-resolution (more than 10 bits) high-speed converters utilize a two-stage conversion process. This type of converter requires the use of a second 5 sampling and holding circuit 220.

Double sampling is necessary to overcome the practical limitations of data collection time, accuracy and depression. The first sampling must take place extremely quickly, in the range of 300 picoseconds at the receiver of the present invention. This requires the use of a small hold capacitor to charge the capacitor from sample to sample to approximately the input signal voltage. The inability to fully prepare for the value of the input signal during the sampling interval results in poor filtering processing, which can be considered negligible for the narrowband signals typically used for terrestrial mobile communication. The use of a small holding capacitor in the first sampling and holding circuit results in a depression rate of 20 that is not acceptable for use with a two-phase analog-to-digital converter. Also, the settling time of the relatively simple latch circuit that may be used in the first sampling and latch circuit may be insufficient for a two-phase converter. For these 25 reasons, a high-precision second display and acquisition circuit 220 is used. Because the signal is efficient. ti downconverted, it changes at a much slower rate \ la. This allows for longer data acquisition time and the use of a larger holding capacitor. Known two-stage converters require that sampling and holding drop in less than 1/2 step interval in a significantly shorter time than the sampling period (typically less than 1/2 of the sampling period).

The first sampling and holding (208) may be performed using conventional techniques

Schottky diode bridge and double gate MOS FETs as a buffer ίο 85076 amplifier. The second sampling and holding can be realized using a Schottky diode bridge with additional backdiasing to limit the subsidence in the holding state. A high-speed amplifier consisting of J-FETs in the dif-5 differential connection as inputs and bipolar followers with a large dynamic range acts as a buffer amplifier.

A wideband amplifier 209 is needed to further amplify the signal in order to overcome the quantization noise of the analog-to-digital guitar converter. Amplifier 209 is used to amplify the sampled signal; therefore, it must be broadband. A large dynamic range is also necessary to prevent the nonlinearities of the amplifier from distorting the signal. The noise factor 15 of the amplifier 209 depends on the amount of "takeover" amplifier provided by the radio frequency amplifier 204 and the overall sensitivity noise requirements. The Motorola MHW591 CATV Broadband Amplifier is suitable for use as a broadband amplifier in the 800 MHz receiver of the present invention.

A 20 A / D converter structure similar to the type described herein is presented in an article by Muto, Peetz, and Rehner entitled Designing a 10-bit, 20 MS-Per-Second Analog-to-Digital Converter System , HEWLETT PACKARD JOURNAL, Vol. 33, 11, pp. 9-29, November 25, 1982.

In accordance with the teachings of the present invention, the color signal 218 is added to the sampled signal in the combiner / isolator 214. The combiner / insulator helps prevent nonlinearities in the broadband amplifier and vibration source from transmitting low-pass noise to other frequencies. The purpose of the vibration 218 is to uniformly propagate the quantization noise of the analog-to-digital converter. The uniform propagation of the noise layer over the Nyquist bandwidth prevents quantization-induced inter-λ 35 distortion distortion from being an inherent problem and also allows the signal to be recovered below the least significant li 85 076 bit level, thus reducing gain requirements before A / D conversion, nonlinearities in the preceding stages cause. The vibration signal 218 must be added before the second sampling and hold 220 if a two-phase converter is used, because the signal must be kept constant during the conversion period. Vibration source 218 may be implemented using an analog noise source, such as a noise diode. The general properties and advantages of vibration signals are described in Schuchman, L., Dither Signals and Their Effect on Quantization Noise, IEEE TRANSACTIONS ON COMMUNICATIONS TECHNOLOGY, pp. 162-165, December 1964.

The noise added to the signal should be spectrally separated from the information. Sampling performed at the 800 MHz receiver of the present invention places the information between about 3 and 7 MHz. The low-pass filter 216 prevents noise from being added to the information signal. The receiver of the present invention is provided with a 5-pole-20a elliptical filter having a 1.5 MHz cut-off frequency for the low-pass filter 216. The average voltage level of the vibration signal over the noise equivalent band of the low-pass filter 216 should be greater than about 5 analog-to-digital converter steps. Care must be taken to prevent the vibration signal from causing clipping in the A / D converter 222.

The analog-to-digital converter 222 converts the analog signal to a digital signal. The converter must be able to accept signals beyond the dynamic conditions of the intended receiver application. At least a 10-bit A / D converter is required for terrestrial communication applications, and theoretical studies show that the dynamic range provided by a 12-bit converter should be comparable to all existing conventional terrestrial mobile receivers. The two most important factors of the analog-to-digital converter 222 are the sampling rate and step size of the i2 85076. The step size determines the amount of gain required before the converter to get above the quantization noise layer. The larger the step size, the higher the gain requirement. Large gain amounts result in nonlinear effects before the converter. The conversion rate is also very important because it determines the allowable bandwidth of the front end filters and also reduces the gain requirement by spreading quantization noise over a larger bandwidth.

The analog-to-digital converter 222, which is satisfactory for use with the 800 MHz digital receiver of the present invention, is a two-phase 10-bit converter with a step size of about 3 mV and capable of converting at frequencies greater than 50 MHz. In accordance with the principles of the present invention, a front end gain of about 54 dB is required to provide a post-detection signal-to-noise ratio of about 10 dB in a receiver having a bandwidth of 30 kHz when receiving a 0.3 μm signal from which to sample 20 MHz. The large amount of gain required before transducer 222 limits the nonlinear performance of the system. The intermodulation ratio (IMR) is limited to about 65 dB, which is slightly less than is achievable with pe-25 parallel receivers. It will be apparent to one skilled in the art that reducing the step size to about 200 uV will allow an intermodulation ratio greater than 80 dB to be achieved. This value is comparable to most existing traditional 800 MHz receivers.

Referring now to Figure 3, there is shown in block diagram form a digital zero type intermediate frequency selectivity (DZISS) section that is compatible with the practice of the present invention. A digital zero-35 type intermediate frequency selectivity section is located between the front end circuit 200 of Fig. 2 and the rear end DSP i3 85076 120 of Fig. 1, and operates to convert the modulated digital radio frequency signal output from the front end 200 to a baseband signal 300 processed by the rear end DSP. 304, 5 quadrature phase mixer 306 (quadrature = 90 ° phase difference), digital quadrature local oscillator (LO) 302 (which provides in-phase local oscillator signal 309 and 90 ° phase difference local oscillator signal 311), two "fast" low pass filters 308 and 310, two "slow" digital low pass filters 312 and 313, and a clock source (not shown).

In practice, in the present invention, identical digital information is input to both in-phase mixer 304 and quadrature phase mixer 306 at input ports 303 and 307, respectively. Generally, ports 303 and 307 are not single lines, but are in fact multiple lines representing multi-bits (e.g. 10 or 12 bits) digital word. The actual length of the digital word used in any given application depends on many factors, including: the resolution required, the dynamic range required, and the sampling frequency of the received radio signal. For example, a 12-bit word length is considered an acceptable performance when receiving a typical radio signal if sampled at 20 MHz.

Mixers 304 and 306 have, as a second input, quadrature local oscillator lines 304 and 311, respectively. In connection with the A / D output signal described above, the local oscillator signals are not single circuits but are multi-bit discrete time representations of the signals in 90 ° phase-to-phase. and cosine waveforms). Mixers 304 and 306 perform arithmetic multiplications of the A / D input word and the local oscillator-35 risana, rounding the result to form an output word that is fed from the output ports of mixers i4, 85076 304 and 306 to the input ports of digital low pass filters 308 and 310, respectively. The digital word lengths of the Pai oscillator and mixer output signals may be selected to provide acceptable noise performance. As the digital word is lengthened, more levels of quantization are available to represent the signals. Smaller quantization increments result in improved noise, as is well understood in the art. This quadrature mixing process described above is analogous to a process performed in analog "intermediate frequency" or direct converting reception. However, the truly linear use of digital multipliers precludes the second-order mixing of unwanted signals into direct current, as well as other undesirable phenomena that occur with analog direct conversion.

The quadrature mixing frequency performed by the multipliers 304 and 306 shifts the desired signal to a center frequency of about 0 Hz, where the amount of frequency shift may be determined by channel frequency control 305. The resulting quadrature signal may then be low pass filtered to remove out-of-band noise and unwanted signals. In a preferred embodiment of the present invention, this selectivity is achieved at two degrees. The first stage is formed by high speed recursive digital filter sections 308 and 310. The digital filters 308 and 310 are identical in structure and may be formed from a recursive filter topology, which will be described in more detail below. Lop-30 puselectivity is provided by "slower" recursive filters 312 and 313, respectively. This choice of architecture will be described in more detail below. After the filtering process, the digital signals are fed to the downstream DSP 120 for further processing.

.λ 35 Figure 4a is a block diagram of the digital oscillator described in connection with Figure 3. It should be recalled that the function of the quadrature oscillator is to provide digitized, sampled versions of the cosine and sine waveforms used in the quadrature mixing process. The implementation of the digital intermediate frequency selectivity-5 part depends on the ability to generate accurate, stable digital representations of these waveforms. The class of digital oscillator implementation, which is particularly suitable for the requirements of the present invention, is based on the ROM read-write and write-memory) search principle. Consider the generation of a cello-like digital signal comprising samples of a complex sine wave: w (t) = 15 where f is the desired oscillator frequency.

According to the traditional communication theory, ej2Jtfct _ C0S2Ttfct + jsin2rtfct, 20 Thus, the desired cosine and sine waveforms can be considered as real and imaginary parts of the complex sine waveform, respectively. The sampled version of the factor is obtained by replacing the continuous time variable t with a discrete time variable nT, where n is a computational integer (1, 2, 25 3, ...) and T is a sampling period equal to 1 / fg = 1 / sampling frequency. This discrete time signal is then equivalent to the following equation: w (n) »e j2rtfc (nT) 30 ROM search methods for generating this signal follow from making the frequency variable f and the time variable ____: c m discrete. If f = kf / 2 (where k and N are integers es V), then:

w (n) = e j2Kkfs (n / fs) / 2N - e j2 * nk / 2N

85076 BC

It can be seen that cosine and N must be generated

values for 2 different phases only. One method of generating these values, called a direct ROM search, basically involves using a ROM table that

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5 contains 2 pairs of values (cosine and sine) and is indicated by a register containing the integer nk (relative to the phase). The phase register is incremented by k (corresponding to the desired frequency fc) at each sampling time (corresponding to the variable n). The obtained frequency separation is Af =

N N

10 fg / 2, in which case 2 separate frequencies can be generated.

Depending on the application, large numbers of ROMs may be directly associated with ROM retrieval technology. The ROM size can be reduced somewhat by utilizing the symmetrical properties of the cosine and sine waveforms. These features

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15 allow the number of table entries to be reduced 2

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from a pair of numbers to a pair of 2/8 numbers. Even with this reduction, the ROM size may still be too large. In such cases, a technique called Factored ROM search can be used to further reduce the ROM size.

The digital local oscillator 400 of the present invention uses a factor-based ROM search technique that takes advantage of the fact that a unit value pointer can be divided into a complex product of "coarse" and "fine" pointers. Thus, a unit-sized pointer can be represented by dividing the signal into e ^ c * e ^ f. Therefore, the unit value pointer can be realized with separate coarse pointer and fine pointer stored in ROMs and multiplied together to obtain the discrete-time sine and cosine values required for quadrature mixers. The advantage of this factorization is that the amount of ROM required to store coarse and fine pointers is greatly reduced from what was required for a direct ROM search application. The price to pay for this reduction in ROM size is bringing the i7 85076 circuit to perform complex multiplication of coarse and fine pointers. In general, complex multiplication can be performed with four multipliers and two adders. By selecting the fine pointer slot with the right 5 and remembering that the cosine of the small angle can be approximated by 1, the ROM for the fine pointer of the cosine can be eliminated. In addition, by approximating the cosine values of the small angle to 1, two multipliers of the multiplication structure required to generate the complex number product can be eliminated. This results in both cost and space savings in the implementation of a factor-based ROM.

Still referring to Figure 4a, a digital quadrature local oscillator 400, implemented using a factor-based ROM implementation, is illustrated in block diagram form. The frequency information in the form of an N-bit binary number proportional to the desired frequency within the sampled band of the A / D converter is loaded into the channel frequency lock circuit 402. The channel frequency lock circuit 402 20 may be implemented in many different forms. For example, assuming N = 20, five cascaded 74LS175 circuits (four D-beam) manufactured by Motorola Inc. and others provide an acceptable implementation. It will be appreciated by those skilled in the art that the channel frequency lock circuit 402 may be loaded by various means. For example, in single frequency radio, the channel frequency lock circuit could be permanently loaded with a single binary number. In multi-frequency radios, the channel frequency lock circuit 402 could be loaded from an EPROM or ROM look-up table or otherwise counted by a microprocessor and locked therefrom.

The output of the channel frequency lock circuit 402 is coupled to a binary adder 404. Those skilled in the art will appreciate that "in the following description of the digital quadrature local oscillator 400, all switching lines between function blocks 35 are in fact multi-bit binary words and not individual switches. The 406 may be implemented as an N-bit binary lock circuit used to hold the address of the next addressable location of the ROM, so the output of the phase accumulator 406 may be directly connected to the coarse cosine ROM 418, the coarse blue ROM: 416 and fine-grained sine ROM 414 (Recall that fine-valued cosine ROM is not needed because it is approximated by 1.) In addition, the output of phase accumulator 406 is fed back to adder 404 10 for summation (modulo 2N) to binary numbers representing channel frequency ll. 402 placed channel frequency inf The output of the phase accumulator 406 is updated with each clock pulse, which is usually the sampling frequency. As a result of this binary summation, the phase accumulator 406 keeps the binary sum (proportional to the phase) of the last address and the binary vector contained in the channel data hair switch. This figure indicates the next address required for the class of quadrature local oscillator signals cos 27 £ fcnT and sin 2ftfcnT.

In the preferred embodiment, the ROM size may be reduced or, accordingly, the level resolution may be improved without increasing the ROM size by adding a digital jitter signal to the output of the phase accumulator 406 and truncating the result before assigning the ROM tables. The frequency resolution of the local 25 oscillator is determined by the Phase Battery Data Path width (N) and the required sampling rate fs · The most straightforward method to increase the frequency resolution is to add more bits to the phase battery and increase the size of the ROM tables. However, this can be an expensive solution because the size of the ROM must double for each bit added to the phase accumulator. Another option would be to add the bits to the phase accumulator,: ’but cut the extra bits before performing the ROM search. This involves severe phase rounding and causes bursts at the output of the local oscillator.

19 85076 To avoid these bursts, a small level of vibration signal is added to the battery output before surgery.

In accordance with the principles of the present invention, the frequency resolution of the digital oscillator can be increased, without increasing the ROM size and without bringing bursts to the output, by adding a binary vibration signal to the output of the phase accumulator 106 prior to cutting. To accomplish this, there is a digital oscillator 400 with an L-bit vibration source 408 that generates a pseudo-random "white noise" signal with a wide L-bit probability density. The vibration source 408 is clocked at a sampling frequency fg to provide a new L-bit vibration word for each phase output of the phase accumulator 406. The N-bit vibration word is formed by adding M = N - L leading zeros to the eight L-bit vibration word outputs of the vibration source. This combined N-bit jitter signal is added to the N-bit of the phase accumulator 406

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output with an N-bit binary adder 410 Modulo 2 way. The sum output of adder 410 is then cut to 20 M bits (not shown). In practice, this cutting process is achieved simply by ignoring the least significant bits produced at the output of the digital adder 410. The cutting operation itself allows for a reduced ROM size.

25 Quantization or shear of a binary phase word produces distortion or noise in the generated sine and cosine waveforms. Since phase is a periodic function (sawtooth), the noise produced by quantization would also be periodic if it were not done in some way for random sex. Periodic noise would result in separate "bursts" in the output spectrum of the oscillator, which bursts are undesirable in most applications if their level exceeds some threshold. Adding a vibration signal before quantizing the phase makes the phase noise random, resulting in a more desirable white noise spectrum at the output. The binary phase word is represented by an N-bit binary word. The jitter signal comprises an L-bit pseudo-random binary word summed to an N-bit phase word. The process results in a binary word with N = L + M bits. This binary word is then cut into an M-bit binary phase word that is relatively free of the burst signals described above.

The effect of phase quantization on the output noise of the oscillator can be shown by the following analysis. The output of the oscillator after Ha-10 is described by the following equation: w (n) = 15

If the phase angle is quantized by the error fc (n), the actual output is described as follows: w (n) = ej [0 (n) +3 (n)] 20 The included error is: E (n) = w (n) - w (n ) = ej [0 (n) +3 (n)] _ gj0 (n) = ej0 (n) £ ej8 (n) .1 j In the case where 3 (n) is very small (<< 1), the term e - * ^ n * can be approximated by the term l + jd (n), which gives E (n) = · j3 (n) 30 ____: The spectrum of the term E (n) can be seen simply --- phase quantization noise 3 (n) as a frequency shift of the spectrum (and non-significant scaling by the term j). Thus, if 3 (n) is random or "white", so is E (n).

· '"35 In addition, the power of the term E (n) is equal to the power of the term 3 (n) 2i 85076, which allows an easy evaluation of the output noise level generated by the phase noise.

Selecting the power level of the vibration signal involves a trade-off between the "bleaching" effect of noise and the noise power level of the output. As the vibration power is increased (by increasing the number of bits L in the vibration signal), the noise becomes whiter, but the total power of the phase noise also increases. It can be shown that if the vibration signal has a uniform probability density, the selection of L = N - M results in a preferred level of vibration power because it represents the smallest vibration signal required to fully whiten the phase quantization noise. Thus, in the preferred embodiment, the number of vibration bits L is equal to the number of bits omitted in the cutting process. It may be noted that vibration signals with a non-uniform probability density can be utilized. However, a uniform density is most advantageous because it is most easily generated. At L = N - M, the phase noise variance (power) is equal to twice the equivalence phase variance of the vibration signal. Given the desired frequency resolution, defined by the terms N and f, then b L and M and thus the required ROM size are determined by the allowable level of white noise at the output of the oscillator.

; . For example, when fg = 20 MHz and N = 20 bits, the • frequency resolution is 19.07 Hz. Cutting to M = 17 bits (to reduce the ROM size by a factor of 8) without jitter creates bursts at the output of the oscillator that are 98 dB below the desired signal level 30 at one particular frequency. Adding a 3-bit vibration signal before trimming whitens the error signal, eliminating bursts. In accordance with the principles of the present invention, the frequency resolution of a digital oscillator, to a certain level of output noise, can be increased infinitely by simply adding more bits to the frequency and phase light circuits and the vibration signal. The ROM size, 22 22 5076 is determined by M, remains constant. The M-bit binary word held after the cut is connected to the ROM address lock circuit 412, the output of which is connected to the ROMs 418, 416 and 414. During the reception of the address, the ROMs 5 418, 416 and 414 give a digital binary word to their respective output ports, located at the received address. The digital quadrature signals are then generated arithmetically from these three binary numbers.

10 As previously discussed, the output signals of ROMs 416 and 418 are binary numbers proportional to the coarse-phase cosine and sine. The output signal of ROM 414 is a binary number proportional to the fine phase blue. To minimize the error in the fine ko-15 sine approximation, the fine phase values used are values centered around the positive axis. The output of the ROM address lock circuit 412 is an M-bit number divided by an M-bit coarse address and a c-M £-bit fine address, where M = M + M, -.

^ w c f 20 The coarse phase is 2ϊί (Ρ + 1/2) / 2 c, where P is an integer c c corresponding to the M-bit coarse assigned. Fine

M C

the step is 2? t (p ^ -2 f-1) / 2, where P ^ is an integer corresponding to a fine address of the M ^ bit. For example, if * _ Mc = 10 and M ^ = 7, the ROM table inputs may be formed as shown in Tables 1 and 2 below. table 1

| Address (Pc) Coarse cosine Rough blue-R0M n

| | ROM contents osoip- contents at- |

1_1 in 'Pc' _] __ sa,? C · _I

30 I | | | | 0 I COS 2π · (1) / 211 | 8 ^ 2: ^ (1) / 211 |

| 1 | COS 2π · (3) / 2η | SIN 2π · (3) / 211 I

: * ··: | 2 I COS 2π · (5) / 211 | SIN 2π · (5) / 211 | | 3 I COS 2π · (7) / 211 | SIN 2π · (7) / 211 | I 4 I COS 2π · (9) / 211 | SIN 2π · (9) / 211 |

I · I I I

35 | . | | I

| 1022 I COS 271 (2045) / 2}} | SIN 2π (2045) / 2}} | I 1023 I COS2n (2047) / 211 | SIN 2π (2047) / 2η | _J__I__1 23 85076

Table 2 I Address (Pf) Great blue-ROM's | | complimentary? at | I _! __! 51 1, 7 1 | 0 I SIN 2k (-64) / 217 |

| 1 | SIN 2π (-63) / 217 I

| 2 | SIN 2k (-62) / 217 I

| 3 I SIN 2π (-61) / 217 1 * 1 i I * ίο I I, 7 1 | 126 I SIN 2π (62) / 217! | 127 I SEN 2π (63) / 217 I_1 _: -!

To generate a cosine waveform (i.e., the rea-15 component of the complex waveform), the outputs of the coarse sine ROM 418 and the fine sine ROM ROM 414 are first multiplied by a multiplier 426. The output of the multiplier 426 is fed to a summing circuit 440 where it is subtracted, where it is subtracted -complement form) from the output 416 of the coarse cosine-20 ROM. This arithmetic process outputs a cosine value output at gate 441 and coupled to the quadrature mixer 304 of Figure 3. To generate sine values of the digital quadrature local oscillator 416 and I of the coarse cosine ROM 41 Outputs of the fine sine ROM ROM 414. is multiplied by a multiplier 428. The output of the multiplier 428 is fed to a summing circuit 442, where it is summed with the output of the coarse blue ROM 418. The summing circuit 442 outputs, through circuit 443, a digital word of the discrete-time sine value connected to the quadrature mixer 306 of Figure 3. Therefore, since the discrete-time values of the sine and cosine signals are calculated mathematically, complete 90 ° phase control is achieved using minimal amount of ROM space. Latches 420, 422, 424, 35, 434, and 438 provide overlap of functions, which 24 85076 contributes to the high operating speed of the digital oscillator. Delays 430 and 436 exist to harmonize the delays of the different signal paths.

The factor-based ROM local oscillator pie-5 increases the ROM range while maintaining an acceptable frequency resolution. For example, to implement a digital quadrature local oscillator operating at 20 MHz, the coarse ROMs 416, 418 could each be implemented as 1,024 x 16 ROMs and the 10 fine blue ROMs 414 could be implemented as 128 x 8 ROMs. This would result in a frequency resolution of about 20 Hz, which uses about 34,000 bits as ROM. The factor-based ROM structure is preferred for operation at high sampling rates because, with the exception of the 15 phase batteries, there is no circuit connected to the feedback. This allows the rest of the local oscillator circuitry (especially the multipliers 426 and 428, which represent the main bottleneck at speed) to overlap to achieve a very high operating frequency .20. Interleaving would consist of bringing the latches to certain critical points, such as self-narrators, as is well understood in the art. Thus, a factor-based ROM local oscillator is described which outputs discrete-time digital quadrature signals having a selected frequency.

A digital adder suitable for use with the device of the present invention may be of the type constructed with a plurality of 4-bit arithmetic logic unit members 74LS181 connected in parallel. These elements are shown and described in a data manual entitled "Motorola Schottky TTL Data Book", available from Motorola Inc., Box 1092 Phoenix, Arizona, 85036. ROMs 418, 416, and 414 may be formed with various well-known ROMs. bodies such as 82LS181, available from Signetics Corporation, 25 85076 811 E. Argues Avenue, PO Box 3409, Sunnyvale, Calif. 94088, and described in the "Signetics Bipolar Memory Data Manual", 1984. Both multipliers 428 and 428 may be implemented, for example, in circuit MPY016K manufactured by TRW Inc., TRW Electronic Components Group, P.O. Box 2472, LaJolla, Ca. 92038.

The amount of coarse ROM required can be further reduced by utilizing cosine and sine waveform symmetries and thus storing only those 10 unit pointer values that are in the first octant of the unit pointer circle (i.e., the first 45 °). It will be appreciated by those skilled in the art that a unit value pointer represents sine or cosine values that rotate 360 °. Due to the symmetrical nature of the sinusoidal waveforms 15, the values of the cosine and sine waveforms in the first octane of the unit circle are identical to the values of these waveforms in any other octant, except for possible sign changes and role changes (i.e., blue becomes cosine and vice versa). Therefore, the only 20 rough coefficients required are in the first octane. There is an indicator of which octane the pointer is at at any given time, and there is circuitry that inverts (i.e., changes the sign) and / or swaps the coarse cosine ROM 416 and the kar-25 kine blue ROM 418. outputs according to the current octane. The octant detector is easily implemented using the three binary bits of the ROM address. For example, the three most significant bits (MSBs) could be used to indicate an octane, and the remaining bits could be used to indicate ROM for a coarse pointer.

Figure 4b is a circuit diagram of an example type of digital vibration generator compatible with the digital oscillator of the present invention. The digital jitter signal may be generated by any of a number of well-known pseudo-random sequence generation techniques. One type of vibration or random number generator is shown and described in G.I. In Donov’s A High-Speed Random-Number Generator, RADIO ELECTRONICS AND COMMUNICATION 5 SYSTEMS, Vol. 25, No. 4, pp. 88-90, 1982.

Referring now to Figure 4b, there is shown in circuit diagram form a feedback shift register type pseudo-random sequence generator that may be advantageously used in the practice of the present invention. The sequence generator of Figure 4b is used to provide an L-bit digital vibration signal to the binary adder 410 of Figure 4a. The vibration generator 408 includes an R-bit shift register 460, which may be formed of a plurality of flip-flops 464-499 connected in series. In a preferred embodiment of the present invention, the parallel 3-bit vibration signal is taken as a tap from the shift register from the outputs of flip-flops 478-491 and 499. The output of the exclusive OR gate 462 is connected to the input of flip-flop 464. The transmission register-20 blade produces a 3-bit pseudo-random vibration signal which is added to the output of the phase battery 406 of Figure 4a. Flip-flops 464-499 and exclusive OR gate 462, as well as other elements used in the practice of the present invention, may be any of a number of well-known logic elements; however, high speed TTL elixes are particularly well adapted to the practice of the present invention. Implementations that use other families of logic will also be apparent to one of ordinary skill in the art. The vibration generator of Figure 4b has previously been shown as an example of one type of digital color generator that works satisfactorily with the digital oscillator of the present invention. It would be obvious to a person skilled in the art that other digital vibration generators could also be advantageously used, assuming that the digital vibration generator produces: · a pseudo-random sequence of L-bit numbers, 27 85076

. . OF

with a period of at least as long as 2 samples and a uniform probability density so that the phase noise produced by the cleavage is (bleached).

As shown in Fig. 3, the intermediate frequency filter section 5 (IF) receives data from the A / D converter at a rate of 20 M samples / s, mixes the received signal with direct current (zero intermediate frequency), low-pass filters the received signal to separate the desired signal, and sends the signal to the end 120 of Fig. 1. At a sampling rate of 10. In the primary implementation, sub-emission filtering and sampling frequency reduction are not separate functions? instead, the sampling rate is gradually reduced between the filter portions as unwanted signals (which, if not removed, would cause spurious reproduction) are filtered out. The only filter data section that operates at the input sampling rate

(f = 20 MHz in the exemplary straight-S described herein

form) is the first part. The only other circuits that operate at this speed are the quadrature position-20 lis oscillator (LO) and mixers. Thus, it is this high-speed circuitry that sets the upper limit at the total operating speed of the digital intermediate frequency selectivity portion. High speed operation is very important for the digital receiver 25 of the present invention to minimize the intermodulation problems encountered in the front end sampling and holding circuit and the A / D converter and to allow sufficient broadband: signal reception.

Figure 5a is a block diagram of the (fast) narrowband low pass filters 308 and 310 of Figure 3. Quadrature local oscillator 302 and mixers 304 and 306. are non-feedback circuits (mainly ROMs and multipliers) suitable for overlapping functions or other parallel forms to increase their speed. However, because the low-pass filter portions 308, 310 are implemented recursively (infinite 28 8 5076 impulse response), they cannot be used in a pipeline to increase their speed. Their speed is determined by the maximum delay around the closed (feedback) road. For the implementation of the low-pass filter-5 of the present invention, this path includes two digital summers and one latch circuit. It is this path that limits the A / D sampling rate and therefore significantly limits the overall performance of the digital receiver. Due to problems at this very high speed, the 10 filter was designed by overlapping two 10 MHz TTL filters. False playback problems that would normally be associated with using a lower sampling rate have been reduced by adding zeros near unwanted filter poles.

The "fast" low pass section 546 of Figure 5a is divided into two half-speed sections and a connecting filter, as shown in Figure 5b. This variation allows the digital intermediate frequency portion to operate at twice the rate that would otherwise be possible and potentially allows for the improved performance of the digital receiver of the present invention. The "shared" filter of the present invention is shown in connection with Figures 3 and 5. Other filter distribution techniques are described, for example, in M. Bellanger, "G. Bonnerott and M. Coudreuse, Digital Filtering by '25 Polyphase Network: Application to Sample-Rate Alteration V- .: and Filter Banks. IEEE TRANSACTIONS ON ACOUSTICS, SPEECH, AND SIGNAL PROCESSING, Vol. ASSP-24, No. 2, April 1976.

The combining filter 554 is a non-recursive filter. The combining filter, shown in more detail in Figure 8, uses two zeros at a frequency of f / 2 (z = -1) to remove the poles generated in the division. Such a filter can only be implemented with adders and latch circuits (i.e. without multipliers) and thus increases the minimum number of circuits.

: 35 Note that although partitioning requires more circuits, it nominally increases power consumption (in CMOS-29 85076 implementation) because two half-speed circuits require approximately the same power as one full-speed circuit (excluding the additional power of the combining filter).

Figure 6 illustrates the division process in detail with several magnitude curves. In particular, Fig. 6a shows the response of the initial version of the first bipolar part at the input sampling rate f 20 MHz. Figure 6b shows a "split" characteristic resulting from two 10 MHz parts, while Figure 6c shows the response of a subsequent "combining" filter. Finally, Fig. 6d shows a combination (i.e., sequential connection) of Figs. 6b and 6c, which is virtually indistinguishable from Fig. 6a, except for a "pit" at 10 MHz 15 (due to two zeros at f / 2, which

S

remove the two close poles).

The split filter can be shown as follows:

2ND

y (n) = Σ y (n -i) hd (i) + x (n)

20 UI

where x and y are complex filter inputs and outputs, respectively (i.e., they have both a real part - * and an imaginary part). Further, h 1 are the polynomial coefficients of the scattered filter 25, and NQ = 2 is the degree of the original full rate filter. Since the split 20 MHz filter is -2 shown in mode z (as will be shown in the next section), it can be implemented in the form of a 10 MHz circuit, where: 30 hd (i) * hh (i / 2), 1 even 0, i odd where h ^ are the original high-speed coefficients.

35 Thus, the subtraction filter can be reproduced as follows: 30 85076

2ND

y (n) = Σ y (n -i) hh (i / 2) + X (n) i = 2 5 step 2

Replacing variable i with variable 2j simplifies this equation:

10 ND

y (n) = Σ y (n -2j) hh (j) + x (n) j = l From this equation, the inputs x and 15 outputs y of the subtraction filter can be divided into two flows, as shown in Figure 5a: xm) = i (2m + y) y ^ (m) = y (2m + y) where: 20 y = mod (n, 2)% 0 {0,1}

Replacing the term n with the term 2m + 1 in the above dilution filter equation gives:: 25% y (n) = I y (2m -2j +1) hj, (j) + x (2m + y) j-1 30 Finally, the two split subtraction filters (y = 0.1) can be ____:

Nd y (y) (m) - Σ y M (m -j) hh (j) + x (y) (m); 35 j-i 3i 85076

Assume that the desired filter has a pole z = z. such

P

the corresponding filter curve can be shown as follows: H Ml-ZpZ-1) - · 5

If this pole is "repeated" at 180 °, the following characteristic is obtained: 10 “m * Zp Σ (1 + Zp z ^)] ^ = (1 -Zp2! -2) '1 _ 2

Since the resulting characteristic is in the form z, it can be divided (as shown in the previous section) into two half-speed filters, each of which has a pole z =.

The low-pass filter portions in the digital zero-intermediate-frequency selectivity implementation of the present invention are realized using the following format written by the coefficients a and b, where b = ca. For the pole pair z ^, zp *, where:

The coefficients of Zp = (1 -d) e JQ Cd, q «l) are:: 25 a (3) 2d and b = d2 + q2 2

For half-speed filters, the pole cap is Zp and 30 (Zp2) *. Since zp2 = [(l-d) no <i] 2 @ (l-2d) ei2cl 35 The coefficients of the half-velocities for the filter can then be obtained by forming the coefficients of the full-velocity case. sa analogous to the full-velocity case: 32 85076 a '= 2 (2d) = 2a and b' »(2d + (2q) 2 5 = 4 (d 2 + q2) = 4b This implementation is illustrated in Figure 5b. the filter is described in, Agarwal, 10 AC, Burrus CS, New Recursive Digital Filter Structures

Havinf Very Low Sensitivity and Roundoff Noise, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS, Vol. CAS-27, No. 12, December 1975. Filter structure II proposed by Agarwal and Burrus has been modified for the purposes of the present invention to have the minimum possible delay around all feedback loops. The filter structure of the present invention is illustrated in Figure 7.

All digital filter structures are basically made of the same three components: adders, 20 multipliers, and delay circuits (usually latches or RAMs). Factors that affect the performance of a digital filter must all cope with the fact that the various parameters of the filters are quantized, i.e., they have finite accuracy rather than the infinite accuracy available in analog filters. The finite accuracy of a digital filter basically increases the three main effects on performance that must be controlled in all implementations of the digital filter.

30 Rounding of the coefficients is one of these effects. The constant coefficients found in a digital filter determine its frequency response. As a result of rounding these coefficients so that they can be represented digitally as a finite number of bits, there is a permanent predictable change in the filter response. This is analogous to changing the RLC values 33 8 5 076 in an analog filter; however, digital filters do not suffer from the disadvantages of temperature changes like analog filters. In general, the higher the value of the filter Q (i.e., the narrow bandwidth compared to the sampling-5 total frequency), the more the rounding of the coefficients distorts the frequency response unless special structures are used. A sensible choice of filter design is essential in light of the fact that intermediate frequency filters are generally extremely narrowband or high Q filters.

Rounding noise is another performance feature that needs to be controlled in a digital filter. The data entering the digital filter is rounded to a finite number of bits and it is almost always necessary to perform additional rounding at certain points in the filter. Such rounding functions generate an error or noise signal in the digital filter. For example, if the length of the digital word used in the filter is 16 bits and the coefficients are expressed in 10-bit format, each multiplication operation of 20 would produce a 25-bit result that would have to be rounded to 16 bits before the result could be put back into memory.

The last major effect controlled in the digital filter is the overflow level. The fact that the data samples are represented as a finite number of bits means that there is a maximum allowable absolute value associated with each node. in the filter and; '** which, if exceeded, results in an overflow phenomenon -: (usually recycling if 2-complementary binary arithmetic is used.) This maximum allowable data value coupled to the previously described rounding noise -.' r. level, determines the dynamic range of the filter.

Several traditional structures are available to implement digital filters. The most straightforward way to design is to put first and second - '· degree straight-line filters in sequence until the desired filter level of 34,85076 is reached. The advantages of this method are its simplicity, regularity and ease of actual filter design. However, this traditional method also suffers from many disadvantages, most often due to the fact that a high-precision (e.g., 16-bit) filter coefficient representation is required to implement a narrowband filter. This makes it necessary to perform very complex multiplications (e.g. 16 x 20 bits) on the feedback paths of the filter parts. Multiplications set stable-10 via speed and time limits for the operation of the filters. In addition, pipelining, a technique commonly used in high-speed logic circuits, cannot be used in feedback loops. In addition, high-precision, high-speed multipliers consume huge amounts of power.

Referring now to Figure 7, the digital low pass filter section 700 is shown in block diagram form. The filter implemented in DZISS is a recursive filter (i.e., the output signal is fed back, scaled, and summed at strategic points in the filter structure) with a narrow bandwidth and optimized for high for velocity and low sensitivity to the adverse effects previously described due to quantization of parameters in _ _ digital filters. The second-order narrowband infinite impulse response (HR) low-pass filter of Figure 7 is used in the split "fast" low-pass filter of Figure 5b, which operates at the speed of the A / D converter. Sharing is useful in achieving this high operating speed, but it requires additional circuitry: two second-order IIRs instead of one, and a second-order FIR that would not otherwise be needed.

The digital low-pass filter 700 provides the operation described in function blocks 550 and 552 of Figure 5b. The digital low-pass filter 700 consists of four 35 digital adders (2-complement) 704, 708, 712 and 716, two digital delays or lock circuits 710 and 718 and two binary shifter 706 and 714. As previously mentioned, in the description of the digital quadrature local oscillator 400, the individual connections of the low-pass filters 308, 310/312 and 313 depicted in Figure 3 are multi-bit digital words and not individual power lines.

The input signal to the digital filter 700 is applied to the non-inverting input 702 of the digital adder 704. The second inverting input to the digital adder 704 is taken from the digital delay 718 fed back from the filter circuit output 720. The difference output (2-complement) of the digital adder 704 is then the gain element displays the transmitted first sum-15 mass signal as one input of the digital adder 708.

Bit shifter 706 shifts all bits of the data word input from digital adder 704 to the right (i.e., toward the least significant bit) by Nc bits, performing a multiplication by a factor c equal to —Ne 20 as 2. This bit transfer may be accomplished by appropriate routing of the data lines from the digital adder 704 to the adder 708. Thus, the high operating speed of the digital filter section 700 is assisted because there is no time delay associated with the bit shifter 706 as if there were a multiplier in the multiplier circuit.

The digital adder 708 sums the transferred first sum signal to the last output of the digital adder 708, which is held at delay 710. Further, the last or previous output of the digital adder 708 is input to digital adder 712. A second inverted input to digital adder 712 is taken from digital delay 718. previously mentioned, the output 720 of the digital filter out-35 is taken. The result of the digital adder 712 is input to a bit shifter 714 connected to a digital adder 716. The bit shifter 714 shifts all bits of the data word input from the digital adder 712 to the right by N bits, a multiplication factor a equal to 2. Bit shifter 714 also promotes high operating speed because no time delay occurs. The parameters N N associated with the bit shifters 716 and 714, respectively, control the frequency response of the digital filter section 700 C cl and may be selected to provide a response appropriate to the intended application, as indicated in the foregoing analysis. The digital adder 716 sums the second transmitted sum signal to the previous output of adder 716, which is held at delay 718. The output of delay 718 is also the output of digital low pass filter section 700 and represents the input signal 702 previously applied to the input of summed circuit 704.

Fig. 8 is a block diagram of a finite impulse response (FIR) second order combining filter with a well halfway through the sampling frequency and used in the split, fast low pass filters of Fig. 5b. Input 802 for filter 800 is connected to output 720 of filter 700, as illustrated in Figure 5b. According to Figure 8, the digital filter 800 comprises digital transmitters 804, 806 and 808 connected to digital delays 810 and 814 and digital adder 812 and 816. Digital transmitters 804, 806 and 808 use gains 1/4, 1/2, respectively. and 1/4. To implement a filter with two zeros on a unit circle, halfway through the sampling frequency. These 30 digital transmitters perform a shift of input 802 to the right by 2.1 and 2 bits, respectively. Because such "bit transfer" can be accomplished by routing the wiring connections in an appropriate manner, these gain operations do not consume any real time and do not require any actual circuitry. The first subtotal is formed in adder 812 using the scaled output of gain element 37 850 76 806 as the first input and the previous or last scaled output of gain element 804 as the second input from delay element 810. Similarly, output 818 is obtained as the second subtotal formed by adder 816. using the scaled output of the gain element 808 as the first input and the previous or last first subtotal of the adder 812 as the second input obtained from the delay element 814. The transfer-10 function of this filter may be written: H (z) = Y (z) / X (z) = (1/4) [1 + z * 1 (2 + z * 1)] In order to calculate the output, this FIR filter only needs to perform one summing operation and one locking operation, compared to two summing operations and one locking operation, In the IIR parts, so that the FIR link filter easily operates at the full input sampling frequency (20 MHz). An alternative design would allow the adder 20 to operate at a lower sampling rate using additional control circuitry. This would allow the FIR filter to operate more slowly by incorporating thinning into the operation of the filter, i.e., counting only the outputs required by subsequent filter sections operating at a lower sampling rate. In a CMOS implementation, power consumption typically decreases as operating speed is reduced. Therefore, the power consumption of the FIR link filter could be reduced at the expense of a small control circuit.

Between the "high speed" filters 308 and 310 and the "hi-30" low pass filters 312 and 313 in Figure 3, it is desirable to reduce or reduce the sampling rate. As is well known in the art, the possible degree of sampling frequency reduction depends on the amount of attenuation provided by the "fast" low pass filters. For example, if a sampling frequency of 20 MHz input is used and the "fast" filters are implemented as 38 85076 split filters with the coefficients shown in Table 3 below, then a sampling rate of 2 MHz can be used over 100 dB of spurious protection provided by "fast" filters.

5 Table 3 I SuodlP part_I_a C i 1

fast (shared) 2 * ^ I 20 I

I hides L I 2-6 2-2 I 2 | 2® | hidas2 | 2 '^ 2 "^ | 2 | I hidas I 2 * 6 2A I 2 i

I-J-J_I

"Slow" low-pass filters 312 and 313 may be implemented in multiple stages of 2-pole filter sections.

For example, if three stages are used, each having the structure of Figures 9a, 9b and 9c and the coefficients listed in Table 3, with slow 1, slow 2 and slow 3 corresponding to Figures 9a, 9b and 9c, respectively, then the sampling rate 20 may be reduced from 2 MHz to a frequency of 80 kHz.

An alternative circuit-saving design involves interleaving the sample streams of in-phase samples and samples with a 90 ° phase difference and using three time division multiplexed filter stages. This requires that the filters operate at twice the rate of operation in a non-multiplexed structure, but because the sampling rate has been reduced by a factor of 10 for a fast filter, this multiplexed filter can still operate at a frequency 30/5 of the first filtering frequency.

Figure 9a is a block diagram of a first time division multiplexed second stage IIR low pass filtering stage used in a time division multiplexed implementation of "slow" low pass filters. Figures 9a to 9c 35 show a time division multiplexed version of a filter structure similar to that illustrated in Figure 7.

39 85 076 The main difference between the structure of Figure 7 and the multiplexed version of Figure 9 is that the length of the delay elements is doubled. Thus, instead of using z-elements implemented as single latch circuits, z-elements implemented as two latch circuits arranged in series are used. The effect of this structure is that the filter on each sample alternates between the processing of samples in the same phase and those with a phase difference of 90 °. In the following description 10, the operation of Fig. 9 will be described in detail. After processing as a digital filter 900a, the signal is coupled to a second filtering stage 900b and then to a third filtering stage, 900c. The entire filter structure of the digital filters 900a, 900b and 900c is identical, so that only the digital filter 900a will be described in detail.

However, the data paths and filter responses of the digital filters 900a, 900b and 900c vary slightly between different phases, as shown in Figures 9a, 9b and 20c and Table 3.

The digital low-pass filter 900a consists of four digital adder (2-complement) 904a, 908a, 912a and 916a, four digital latches, two in each block 910a and 918a, and two binary shifters 906a and 914a. The input signal to the digital filter 900a is applied to the non-inverting input 902a of the digital adder 904a. The second inverting input for the digital adder 904a is taken from the pair of digital latches 918a, which signal-30 is fed back from the output 920a of the filter circuit. The difference result (2-complement) of the digital adder 904a is next input to the input of the bit shifter 906a, which outputs the transmitted first sum signal as one input of the digital adder 908a.

35 The bit shifter 906a shifts all bits 40o 85076 of the data word output from the digital adder 904a to the right (i.e., toward the least significant bit) by N bits, performing a multiplication by a coefficient equal to “They are equal to 2. This bit transfer may be accomplished by appropriately routing the data lines from the digital adder 904a to the adder 908a. Thus, the high operating speed of the digital filter section 900a is facilitated because the bit shifter 906a is not associated with any time delay that would occur in a multiplier calculation implemented with a conventional multiplier circuit.

The digital adder 908a sums the transmitted first sum signal to the output of the digital adder 908a, which is held for two sample periods in the latch circuit pair 910a. Further, the output of the digital adder 908a held in the latch circuit 910a is fed to the digital adder 912a. The second inverting input for the digital adder 912a is taken from the latch circuit 918a, which signal, as previously mentioned, is taken from the output 920a of the digital filter. The result of the digital adder 912a is input to a bit shifter 914 connected to the digital adder 912a. The bit shifter 914a shifts all bits of the data word output from the digital adder 912a to the right by N bits cl, performing a multiplication with a coefficient equal to _Na as 2. The bit shifter 914a also facilitates a high operating speed because no time delay occurs.

The parameters N and N associated with the bit shifters c a 906a and 914a, respectively, control the frequency response of the digital filter stage 900a and may be selected to provide a response appropriate to the intended application. The digital-30th adder 916a adds a second transmitted sum signal to the previous output of adder 916a, which is held at delay 918a. The output of the delay 918a is also the output of the digital low-pass filter section 900a and represents a band-limited representation of the input signal 902a previously applied to the input of the summing circuit 904a.

4i 85076

It will be apparent to one skilled in the art that a more gradual reduction in sampling frequency could be used, for example, between each of the four low-pass filter sections. The gradual reduction of the sampling rate offers a significant advantage in that it provides a lot of flexibility in forming the total ratio of the input sampling rate to the output sampling rate. This allows the A / D sampling rate to be determined almost arbitrarily to match the desired passband of the preselector 10, which is exposed to be bound by the sampling frequency of the output. At the output of the third (and final) "slow" low-pass filter section, the channels are subjected to sufficient attenuation at higher frequencies so that the spurious reproduction caused by thinning from 2 MHz to 15 80 kHz does not interfere with the desired band centered at approximately zero frequency.

After filter processing and thinning by the high speed selectivity portions 114 of Figure 1, the recovered digital signal comprises 20 received digital signals with quadrature components. The quadrature characteristics of the received digital signal ensure that the phase information that was in the original radio frequency signal is stored throughout the processing chain. The received digital quadrature signals 25 are coupled to the rear end 120 of the digital receiver of Figure 1, which is preferably implemented with a programmable, universal, integrated signal processing circuit, as mentioned above. The radio end 120 performs the additional processing required to generate a digital carrier frequency signal that is used to provide the recovered data or audio signal. In addition, the rear end 120 of the radio may provide final pre-demodulation filtering and post-demodulation processing of the recovered signal. Figures 10 and 11 show in detail digital filter structures suitable for performing final pre-demodulation selectivity in connection with a digital integrated signal processing circuit. Figure 12 details a technique suitable for demodulating an FM signal in accordance with the teachings of the present invention.

Figure 10 shows a fifth order non-recursive filter 1,000 that provides additional attenuation so that the sampling rate can be further reduced from 80 kHz to 40 kHz while causing a negated spurious reproduction distortion of the desired band. Because this filter operates at a relatively low output sampling rate of 40 kHz (complex samples), it is possible to implement it in a general purpose digital signal processor. Such processors are typically well suited for interleaved multiplication operations of 1,004, 1,010, 1,016, 1,026, 1,030, 1,036, and summation operations of 1,006, 1,012, 1,020, 1,024, and 1,032, so that " straightforward "filter structure was chosen.

Figure 11 shows a straight filter structure 1000 with four poles and four zeros used to smooth the passband response of the receiver link filter, it may be implemented by a series of multiplication operations 1 104, 11 112, 1118, 1120, 11 126, 1,132, 1,140, 1,146 and 1,150, with a plurality of summing operations 1,106, 1,114, 1,116, 1,122, 1,108, 1,130, 1,136 and 1,144 in a general purpose digital signal processor. Because simple-precision (typically 16-bit word length) operations do not provide sufficient dynamic range for mobile radio applications, it is necessary to use dual-precision computations in a DSP implementation.

It will be apparent to one skilled in the art that different bandwidths for the final selective part could be obtained by systematically selecting different filter coefficients in the rear digital signal processor. Different selectivity bandwidths could also be obtained using different downsampling frequencies or with different wired gain elements (e.g., 43,85076 from two-to-one selectors) in multiplicative low-pass filter sections.

Figure 12 is a diagram of a digital FM demodulator compatible with the di-5 digital radio architecture of the present invention. In reality, digital demodulation is one task among others that is performed by a digital signal processor circuit. As shown in Fig. 12, the limiter section 1 202 comprises a scaling stage 1 204 together with an in-phase channel inverse-10 field generator 1 210 and an input multiplier 1 212, where the inverse of the scaled and rotated in-phase (I ') component is multiplied by the scaled and rotated Q , which is equal to the value of the phase angle tangent of the scaled and rotated signal vector sample. The operation of the digital multiplier 1 212 performs an ideal limitation of any amplitude variations in the input signal vector that may be present. The term released from the digital multiplier 1,212 represents the tangent of the rotated and scaled 20 signal vector samples. This term is processed by an inverse tangent generator stage 1,214, the output of which is equal to the phase angle of the rotated and scaled signal vector. This magnitude, when added by a digital adder 1,214 to the coarse phase value output from the coarse phase battery 1,206, represents the total phase angle of the vector sample of the input signal. The difference signal generated at the output of the digital adder 1,218 between the phase angle of the current signal vector sample and the negative of the delayed output generated by the digital delay 1,220 30 represents one sample of the output demodulated message.

Figures 13a to 13c are diagrams detailing the principles of pointers in the context of the present invention. Referring now to Figure 13a, if the operation of the scaler 1 204 is to scale the amplitude of a signal vector of varying size to the shaded area 44 85076 shown. The coarse phase accumulator 1 206 determines the coarse phase angle of the signal vector 0c and the output of the inverse tangent generator stage 1 212 is equal to the fine phase of the signal vector 0f, as illustrated in Fig. 13b. The Sig-5 nal vector 0f is located in the region -ίί / 450 ^ £ + ΤΖ / 4 (shaded area of Figure 13b) forced by the rotation of the vector. The sum of these two quantities generated at the output of the digital adder 1,214 represents the total phase angle of the vector signal 0 (n) of the input signal. The difference value 10 Δ (0 (η)) generated by the digital adder 1218 between the current phase sample 0 (n) and the phase sample 0 (n-1) generated by the digital delay 1,220 shown in Fig. 13c represents one sample of the demodulated output message. The stream of samples representing a demodulated output message may be low pass filtered to remove noise outside the message bandwidth, as is typically done after FM detection.

It would be apparent to one of ordinary skill in the art that the digital demodulator 20 described in the figures could be implemented with digital multipliers, adders, registers, etc. consisting of separate circuits. The digital demodulator of the present invention is particularly suitable for implementation by means known as digital signal processors. Present '. The invention would work satisfactorily in various well-known signal processors, such as the NEC D7720 available from NEC Eletronics U.S.A. From Incr, One Natick Executive Park, Natick, Mass. 01760 or TMS 320101, available from Texas Instruments Inc., P.O. Box 225012, 30 Dallas, Texas 752265. Digital signal processors typically include high-speed digital hard multipliers as well as the ability to process a digital data stream according to a predetermined algorithm.

Figs. 14a and 14b are flowcharts showing in detail the background processing of the present invention implemented with a digital signal processor. In all descriptions of the present invention, in-phase and out-of-phase signal vector components are hereinafter referred to as components I and Q, respectively. The algorithm of the present invention begins at step 402, which causes the digital signal processor to perform decision 4040 to determine the sign of the I component. Based on the result of decision 1 404, the sign of the Q component is determined by decisions 1 406 and 1 448. Next, the difference between the I and Q-10 components is determined at 1 410, 1 408, 1 472 and 1 450, which generate values comprising the values QI, respectively. IQ, QI and Q + I. The sign of the corresponding results is determined by decisions 1 430, 1 412, 1 474 and 1 452, respectively. For the results of these decisions, the component (I or Q) with the higher value is known and the actant (i.e. the ft / 4 multiple) where the signal vector is located. This value, if less than zero, is complemented by 1 420, 1 486, 1 476 and 1 462 respectively. The value representing the maximum absolute value of the already 20 or so I or Q channel is inserted into the program stack at 1 442, 1 432 , 1,422, 1,414, 1,488, 1,478, 1,466 and 1,454, respectively, and is hereinafter referred to as SMAX. The quantity SMAX is used by calling the scaling subroutine at items 1 444, 1 434,: 25 1 424, 1 416, 1 490, 1 480, 1 466 or 1 456 to determine the amount of correct scaling to be applied to the vector sample of the input signal. The scaling subroutine returns the correctly scaled signal vector components I and Q. Next, a rough phase value based on the octane location of the signal-30 vector is stored in a temporary memory location at 1,446, 1,436, 1,426, 1,418, 1,492, 1,482, 1,468, or 1,460, respectively.

-I. This value will always be a multiple of the ^ 2 radian in the range (c) The signal vector is then rotated with a geometrically coarse phase value negative that was retained at 1 440, 1 428, 1 492, 1 484, 46 8 50 76 1 470 or 1 460. The resulting scaled and rotated signal components are hereinafter referred to as I'and Q1 signal vector components. The purpose of this vector rotation is to rotate the signal vector so that the rotated signal vector components 1 'and Q' give a composite vector with a phase angle in the range - ^ / 4 * 0f 4.

Figures 15a and 15b are flow charts of the operation of the scaling subroutine described above in connection with Figure 14a.

10 The scaling subroutine 1,500 examines the value of SMAX to determine the correct amount of scaling to be applied to the signal vector components I and Q. The operation of this subroutine depends on the resolution or the number of bits used to represent the signal vector components. The operation of the Scaling-15 subroutine will be described in the context of using 32-bit long words to represent signal-vector components. After entering the scaling subroutine, the SMAX most significant word (MSW) of 1 502 is compared to zero by decision 1 504. If the 20 MSW of SMAX is greater than zero, the SMAX least significant word (LSW) is discarded and the MSW is compared to the scaling threshold in 1 506. If the MSW of the SMAX is equal to zero, then the MSW is discarded and the LSW is compared to the scale. the results of the comparisons generated at 1,506 and 25,528, respectively, are compared with zero at decisions 1,508 and 1,530, respectively, and if the result is found to be greater than zero, signal-vector component scaling is not necessary and the subroutine exits via 1,550 to , where the oh-30 program activates the subroutine 1,500. If the stored word in SMAX (i.e., MSW or LSW) is less than the threshold, the stored word is tested by decisions 1,510 and 1,532 to see if the absolute value is greater than 255. This is equivalent to determining whether the upper eight words of the stored word 35 of SMAX are greater than or equal to zero. If the result of this test is true 47 85076 (i.e., the SMW or LSW of SMAX is greater than 255), the retained word is divided by the number 256 at 1,514, or 1,536, respectively. This has the effect that the top eight bits of the retained word in SMAX are moving this word to the lower 5 to eight bits. If the result of a decision of 1,510 or 1,532 indicates that the retained word is less than 255, no division is performed. This value is now used as the address offset at 1,516, 1,512, 1,538, or 1,534 to select the values stored in the ROM data table-10 size and the scaling factor is returned from the ROM at 1,520, 1,540. This factor is set to the correct value, which it is necessary to scale the vector components of this signal, depending on previous decisions 1,510 or 1,532. Finally, the signal vector components are scaled to the right range for use by the demodulator at approximations at 1,522 and 1,524 or 1,542 and 1,546 and the routine exits back to the called program. through items 1,526 or 1,548.

Referring now to Figure 16a, the inversion or inverse of the vector component I'-20 is determined. This treatment is performed by performing a sixth-order Chebyshev polynomial approximation for the function f (x) = l / x.

The polynomial that approximates this function is: '25 f (x) * (1 / x) ** {[[[[[C7 (xl) + C6] (xl) + C5] (xl) + C4] (xl ) + C3] (xl) + C2] (x-1) +01} where x = Γ and Cl = +1.00000.02 = -1.0027, C3 = +1.00278, 04 = -0.91392 .05 = +0.91392, 06 = -1.62475.07 = -1.62475.

30

In accordance with the principles of the present invention, the Q 'component is inserted into the program stack memory area at 1,604 and the magnitude (I * - 1) is calculated at 1,606, hereinafter referred to as ARG.

35 The coefficient C7 is retrieved from the data ROMs at 1,608 and is multiplied by the ARG at 1,610 to form the magnitude TMP 48 85076. The coefficient C6 is retrieved from the data ROMs at 1,612 and added to the TMP at 1,614, which gives a new value to the TMP. This pattern is repeated sequentially at 1616 to 1644 until the Q 'component is then retrieved from the program map memory at 1648 and multiplied by the TMP at 1650, which gives an approximation of tan0 ^ = Q'I'. The inverse tangent of the quantity obtained at 1,650 is now determined. This processing is performed by performing a fifth-order Chebyshev polynomial approximation for 10 functions: = arctan (x)

The polynomial that approximates this function is: 15 arctan (x) - * {[[[[C6 (y) + C5] y + C4] y + C3] y + C2] y + Cl} where x - Qvr 20 y = (Qvr) 2 and C6 = -0.01343, CS = +057737, C4 * -0.12109, C3 - +0.19556, C2 = -0.33301, Cl = .0.99997.

The quantity x = (Q * / 1 *) is inserted into the stack memory of the program at 1,652 and the value of the squared quantity 25 y = x, hereinafter referred to as ARG, is calculated at 1,654. In a chain-like manner similar to the previous one described inverse value calculation, calculating the inverse tangent value of the quantity (Q '/ 1 *) at 1 656 to 1 692. The result of this process is an advantage-30 characteristic value representing the phase angle of the rotated signal vector or the fine phase angle of the vector signal of the input signal. The value of the coarse phase of the vector sample of the input signal is returned from the temporary memory location at 1 694 35 and added to the result of the inverse tangent calculation at 1 696.

49 8 5076 This result represents the phase angle of the vector sample of the input signal. The phase angle of the vector sample of the previous input signal is retrieved from the program stack at 1 700. The current phase sample is inserted into the program stack at 1 702. Finally, the difference between the previous phase sample and the current phase sample is calculated at 1 704, which outputs the demodulated message m (n).

The message sample m (n) comprises a demodulated audio signal in the sampled form. The demodulated audio signal can be converted back to analog form, then amplified and reproduced through a speaker, as mentioned above. Alternatively, the digital voice message may be stored digitally in a digital memory 123 for later use. In a communication system (not shown), the demodulated data symbols may be routed to a computer for further processing or to a computer screen for immediate display.

In summary, a digital radio receiver is shown. The digital receiver of the present invention forms a fully digital radio receiver that processes a received signal that has been converted to digital form after preselection at the antenna output. The receiver of the present invention comprises a preselector, a high-speed analog-to-digital converter (A / D), a digitally implemented intermediate frequency selectivity (IF) section having an output signal at substantially baseband frequencies, and integrated digital signal processing (DSP) integrated circuits. perform demodulation and audio filtering. Other uses and variations of the present invention will be apparent to those of ordinary skill in the art without departing from the spirit and scope of the present invention.

Claims (5)

50 85076 An apparatus for substantially digitally processing a wideband analog signal comprising a desired narrowband analog signal, the apparatus comprising (a) means comprising switching means (102) and filter means (106) for transmitting a wideband analog signal comprising the desired narrowband analog signal. and (b) digitizing means (108) coupled to the filter means (106) for periodic sampling of said wideband analog signal and converting it to a sampled wideband digital signal, characterized by (c) a digital means (110) coupled to the digitizing means (108) for selecting the desired sampled narrowband digital signal from the sampled wideband digital signal, the digital means comprising a digital quadrature oscillator (116), a digital a quadrature multiplier / mixer (112), a digital narrowband quadrature low pass filter (114 and 124), and means (120) for programmatically adjusting the bandwidth of the narrowband quadrature low pass filter, and (d) digitally processing said sampled narrowband modulated signal from the digital processing means (126). : V: 30 Device according to claim 1, characterized in that the switching and filtering means comprise an antenna element (102) for receiving signals containing a broadband signal (radio frequency). 35 si 85076 Device according to claim 2, characterized in that the filter means are connected to the antenna element for filtering the broadband signal (radio frequency). 5 A method for substantially digitally processing a wideband analog signal containing a desired narrowband analog signal, the method comprising the steps of: (a) receiving and filtering a wideband analog signal containing the desired narrowband analog signal, and (b) periodically sampling said wideband analog signal; converting it into a sampled 15 wideband digital signal, characterized in that it comprises the steps of: (c) selecting the desired sampled narrowband digital signal from the sampled wideband digital signal, programmatically adjusting the bandwidth of the sampled narrowband digital signal signal demodulation. A method according to claim 4, characterized in that the wideband analog signal comprises a wideband radio frequency signal. 52 85076