JPS63500766A - digital radio frequency receiver - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed description of the invention] digital radio frequency receiver field of invention TECHNICAL FIELD The present invention relates to the field of wireless communications, in particular implemented in substantially digital circuits. The present invention relates to a radio frequency receiver.

Background of the invention Conventional wireless communication devices are mainly implemented using analog circuits. analog components The inherent characteristics of the signal limit the amount of signal processing possible. For example, an analog amplifier The dynamic range of the processed analog signal is limited by the noise and gain characteristics of limited. In other cases, analog information is stored in a way that allows complex signal processing. It is not easy to pay.

Use digital signal processing to replace operations previously performed using analog processing. In use, external influences such as temperature, humidity, and aging may be applied to analog components. Undesirable fluctuations in these motions resulting from these movements are eliminated. Moreover, digital signal processing Technology is flexible in terms of programmable operating characteristics and features. . For example, a digital intermediate frequency (IF) integrated circuit has its channel frequency, program with respect to its sampling rate, and to some extent its filter response. It is possible. A digital signal processing device that alternately executes stored programs ( DSP> performs various types of filtering and demodulation to create completely different types of radios. can do. DSP also introduces advanced processing techniques such as adaptive equalization. It can be used for.

Another advantage of digital receiver architecture is that the DSP and IF circuits can be "reversed" Installed in such a way that it can perform the corresponding operation for the transmitter that is carried out on a regular basis. 1. It is something that can be done. In half-duplex operation, the circuit simply reverses the "direction". full-duplex operation requires two IF filters. Become.

The first technology that enables virtually digital receivers is high speed (20-100 Ml-1 z) It is a high resolution (10 to 12 bit) AD converter. digital receiver The second factor that makes the structure technically possible is that it can be achieved by implementing a VLSI IC. The high degree of integration and high speed will eventually lead to, for example, 40kHz The current digital filter is a 4-pole 4-zero integrated digital filter with This can be realized with a communication@processing device. This invention brings these new technologies to the forefront. Combined with improved techniques of end-analog processing and digital filtering This makes it possible to set up an upper digital receiver δ4.

The receiving structure of the present invention brings about revolutionary changes in the manufacturing technology and operating characteristics of mobile radio equipment. can be Furthermore, this method allows the radio to be assembled with a minimum number of parts. This immediately reduces the number of parts, lowers manufacturing costs, and improves the radio's design. Reliability and availability will also be improved.

Summary and purpose of the invention In summary, the present invention preselects the output of the antenna and then selects the output in digital form. All-digital radio reception is intended to operate on received RF signals that are converted to . The receiver of the present invention includes a preselector, a high speed analog-to-digital (AD) converter, a digitally constructed intermediate frequency with an output signal substantially at the baseband frequency; Wavenumber (IF) selection section and final selection or equalization, demodulation, and post-demodulation processing It is equipped with a general-purpose digital signal processing (DSP) integrated circuit that performs the following steps.

It is therefore an object of the present invention to provide a digitally constructed radio receiver. It is.

A wireless receiver that allows easy reception of multiple transmission schemes (providing forward This is another object of the present invention.

Still other objects of the present invention can be realized commercially using integrated circuit technology. Wireless receiver (to provide structure).

It is a further object of the present invention to reduce the resolution and step size requirements of an AD converter. To provide a design for a digital reception-specific IF filter that operates at relatively high speeds such that That's true.

Brief description of the drawing FIG. 1 is a block diagram showing the functions of the digital receiver of the present invention.

FIG. 2 is a schematic diagram of the front end circuit of the digital receiver of the present invention.

FIG. 3 shows the digital zero 1 of the present invention. This is a block diagram of the F, 'M selection section.

FIG. 4a is a schematic block diagram of the digital generator cited in FIG. 1.

Figure 4b shows digital zero 1. of Figure 3. F, pseudo-random divisor that can be adapted to the selection part 1 is a schematic diagram of a laser generator; FIG.

FIG. 5a is a block diagram of the required "fast" narrow band low pass filter.

FIG. 5b is a block diagram of the decomposition approximation method for the fast low-pass filter of FIG. 5a.

Figures 6a to 6d are frequencies showing details of the characteristics of the high-speed low-pass filter in Figure 5. These are several figures.

Figure 7 shows the second-order narrowband low-pass filter used in the decomposed "fast" low-pass filter of Figure 5b. 1 is a schematic diagram of an limited impulse response (IIR) filter; FIG.

Figure 8 shows half the sampling rate used for the decomposed high-speed low-pass filter in Figure 5b. This is a schematic diagram of a second-order finite impulse response (FIR) filter with a notch in the minute. .

Figures 9a through 9C are time-division multiplexed "slow" low-pass filters as described in connection with Figure 3. FIG. 2 is a schematic diagram of a time division multiplexed second-order low-pass IIR filter used in the filter.

Figure 10 is used to further reduce the sampling rate from 80kHz7 to 40kHz7. FIG. 2 is a block diagram of a fifth-order low-pass FIR filter used in the present invention.

Figure 11 shows the fourth-order low-band IIR used for final selection and passband equalization prior to demodulation. FIG. 2 is a block diagram of a filter.

FIG. 12 is a block diagram of an FM demodulator that can be implemented with a general-purpose DSP.

Figures 13a to 13c explain the details of the phasor principle in the context of the present invention. This is a diagram.

Figures 14a and 14b detail the operation of the background routine of the FM demodulator of the present invention. It is a flowchart for explaining.

Figures 15a and 15b are scale routines described in connection with Figure 15a. 2 is a flowchart of the operation.

16a to 16c illustrate the operation of the remaining parts of the digital demodulator of the present invention. 2 is a flowchart illustrating details.

Brief description of the drawing FIG. 1 shows the functionality of a digital receiver with three main operations. The diagram shows the receiver Although no example of diversity is shown, those skilled in the art will appreciate the It is clear that various guidance techniques can be applied. In particular, The code section 104 is shown in rough detail in FIG. An antenna 102 for receiving RF) signals and a digitally configured IF selection section 1 10. The preselector 106 performs broadband filtering on the incoming signal. to avoid aliasing in the subsequent AD conversion process. AD Bro A block 108 provides gain and sampling necessary for digital processing of the received wave structure according to the present invention. Includes hold operation.

The next main part, the IF selection section 110, will be described in further detail below in connection with FIG. is a quadrature local oscillator (quadrature signal, sine and cosine) that generates a complex exponential shadow signal ( LO) becomes 116. The frequency of this signal is the system channel frequency input “△ ” is selected. The quadrature mixer 112 uses digital multipliers to Frequency shift the band channel to an IF frequency of approximately OHz. High speed selection section 1 14 comprises several cascaded narrowband low-pass filter sections, which Remove high frequency unnecessary signals from the desired signal centered near the wave number. This low range By filtering the large velocity at the output of the ΔD converter 108, Gradually sample as fast as the channel bandwidth at the input to the 120 You can reduce the download speed.

The “back end” section 120 indicates the general purpose wireless @ construction in the wireless format of the system. The particular radio being used is used to "specialize" the application. It will be done. The best configuration includes a general purpose digital signal processor (DSP).

The final selection unit 124 recovers the radio signal according to the modulation format and channel characteristics. Perform any necessary additional filtration before adjusting. For example, digital data communication systems Adaptive channel equalization can be performed for This filter section 124 is adjacent to Channel attenuation and power meter are extremely low 1'0. ) the coarseness required to implement the filter. A method for compensating for imperfections in the characteristics of the fast selection filter 114 resulting from high coefficient quantization. It also performs overband equalization. The demodulator 126 receives audio data and frequency shift 1 to key ( The software can be used to perform many forms of demodulation, including FM demodulation of (FSK) data. A can be programmed. The demodulated audio signal is similar to @121 and and 122, it is converted back to analog form and then amplified through a loudspeaker. is played. Alternatively, digital voice messages can be digitally recorded for later playback. can be stored digitally in digital memory 123. data communication system (not shown), the demodulated data symbols are sent to a computer for rough processing. or can be sent to a computer terminal for immediate playback. In addition, automatic Control information for performing wave number tracking 128 is generated in the “back end” section 120 be able to. Finally, the clock generator 118 is used for clock generation when accurate down conversion is required. To control the input sampling rate of AD conversion, digital circuits can be used in a regular manner. Output samples for working with and possibly synchronizing with subsequent systems required to control the processing speed. In the exemplary embodiment described here, the The pulling speed f3 must be set to 20MHz, and the center of the receiving frequency band is approximately Located at 875MH2.

FIG. 2 is a schematic diagram of the front end circuit of the digital receiver of the present invention. this The circuit operates to digitize selected bands of radio frequency signals. Book The invention performs sampling directly in R, F, and frequency.

However, wideband preselection requires RoF and analog filters before sampling. It is held in Ta. The functions of R, F, and filters 202 and 206 are designed to prevent spurious responses. It is about making a choice. These spurious responses include conventional receiver freon. Images like those seen on Toendo, half 1. F, Spa, Able-Baker Spa - etc. Besides these spurs, selection can also result from the sampling process. It must also be done for certain frequencies. The maximum allowable bandwidth depends on the actual router reduces this considerably, but the Nyquist bandwidth (f,/2, where f is sampling speed).

The 2-pole and 5-pole filters shown in Figure 2, each with a bandwidth of about 4 MH2, are used. 9 for the alias frequency when sampling at a rate of 20MH7. Provides rejection greater than 0 dB. In addition to making selections for the signals entering antenna 224, , filter 206 is R, F, first sample and hold 2 generated in amplifier 204 Broadband 9i sound that falls in 08 is band-limited. This prevents noise aliasing , which is necessary to effectively increase the front end 200(7) 1 note index. be. R,F, preamplifier 204 is R,F.

Amplify the signal to a level sufficient to obtain the signal-to-noise ratio required for system sensitivity used to. Since different bands require different filters, The R, F, amplifier 204 is included as part of the data structure (202 and 206). It's practical. The receiver of the present invention has a gain of about 28 dB and a noise figure of about 5 dB. , F, and an amplifier 204.

The clock 212 and the sampling pulse generator 210 are connected to the first sample hole. second sample hold 2201 analog-to-digital converter 222 , and a digital zero IF selector (not shown) with clock signals and samples. and pulses. Clock generation is from a widely available 20MH7 crystal. It is done with a shaker. 40MH2 used by digital signal processing equipment (not shown) The signal is obtained by doubling 20MH2 by an analog doubling circuit.

The pulse generator 210 generates a 20 MHz clock signal (approximately a sine wave) into a very narrow pulse. Used for shaping into ruses.

The width of the sampling pulse is determined by the highest frequency band one wishes to receive. Approximately 30 A pulse width of 0 psec produces a harmonic “comb” with a nearly uniform amplitude up to about 1 GH2. ” occurs.

This is necessary to operate the receiver of the present invention at an operating frequency of approximately 875 MH2. Ru. Pulse generation uses a conventional step recovery diode and linking circuit. It can be done using This type of circuit is available in San Francisco, California 95131. Jose, 350 Trimble Road, Hewlett Paracard Microwave Semiconductor Department Huuret Paracard Application Note No. 92 available from the gate No. 0, “Harmonic generation using step recovery diode and SRD module” It is described in a publication titled "The Occurrence of

The bands of the signals amplified and selected in blocks 202, 204, and 206 are sample bold 208. This is a conventional R, F-, receiver. A [It is similar to blue down converting. flash analog di Digital converters effectively sample the signal, but practical converters have band-limited inputs. Therefore, it is necessary to perform sampling before conversion. Also, until now, the known The high resolution (>10 bits), high speed converter utilizes a two-step conversion process. ing. A second sample and hold circuit 220 is required for this type of converter.

Double sampling to overcome practical limitations in acquisition time, accuracy, and sag characteristics is necessary. The first sample and hold is very fast, 30 It must be acquired within a range of 0 psec. This includes sample to sample. A small hold capacitor is used to charge the capacitor to approximately the voltage of the input signal. The value of the input signal must be completely captured within the sampling interval. The inability to charge leads to additional filtering, which is difficult for land mobile communications. can be considered negligible for typically used narrowband signals. Ru. Using a small hold capacitor for the first sample and hold results in two stages. It produces droop speeds that are unacceptable for use in analog-to-digital converters. Cheating. Also, the first sample hold is relatively simple to use. The settling time of a hold circuit is inadequate for a two-stage converter. because of these reasons , using a high precision second sample and hold 220. The signal is effectively downcoupled. Because the signal is being converted, the signal is changing much more slowly. As a result, The gain time and hold capacitor can be increased. Known two-step transformation is much smaller than the sampling period (typically 1/1/2 of the sampling period). 2 or less) Sample hold that droops at less than 1/2 of the step size in time is necessary.

The first sample hold (208> is a Schottky diode bridge and buffer Constructed according to conventional technology using double gate MO3FET as amplifier can do. The second sample bold is a Schottky diode bridge. This can be achieved by separately back biasing to limit droop in hold mode. can be done. High speed amplifier and high die with differential configuration J-FET as input The Namitsu range and Tsuga lower operate as a buffer amplifier.

The wideband amplifier 209 is used to overcome the quantization noise of the analog-to-digital converter. It is necessary to further amplify the signal. Amplifier 209 converts the sampled signal into used for amplification. Therefore, it must be broadband (high frequency). The Inamitsu range also prevents signal distortion due to amplifier nonlinearity. is necessary. The noise figure of amplifier 209 is R1, and the noise figure generated by amplifier 204 is depends on the amount of "over" gain and the overall noise requirements for sensitivity. moto Roller's MH'1A1591 CATV wideband amplifier is equipped with the 800MHz receiver of the present invention. Suitable for use as a wideband amplifier used in radio equipment. the shape described here The structure of an AD converter similar to the formula is described in Hewlett Paracard Journal, Vol. , 33, No, 11. pp, 9-29. November 1982 “10 Design of a 20Ms/s Analog-to-Digital Conversion System Mute, Peet Z1 and Rehner.

In accordance with the teachings of the present invention, dither signal 218 is coupled to combiner/isolator 218. added to the sampled signal. Combiner/Isolator is a wideband amplifier The nonlinearity and dither source present in the low I! ! Don't convert the pheasant sound to other frequencies This will help you. The purpose of dither 218 is the amount of analog to digital converter. The goal is to uniformly distribute the childization noise. Noise floor across the Nyquist band Is intermodulation distortion caused by quantization an inherent problem if the signals are distributed uniformly? protection, signal recovery below the least significant bit level, and AD changes. The required gain before conversion is lower, resulting from nonlinearities in the previous stages of the converter. fewer problems. Dither signal 218 must keep the signal constant during the conversion period. Therefore, when using a two-stage converter, the second sample hold 22 The dither source 218 is a noise diode, etc. This can be realized using an analog noise source.

What are the general characteristics and advantages of dither signals? IEEE TRANSACTIONSON Co-unifications TECHN Kano OGY, pp, 162-16 5. December 1964 paper by Schuchman, L. “Dither Signal and its quantization noise and V influence.

Noise added to the signal should be spectrally separated from the information. present invention The sampling done in the 800MHz receiver of the Place it between 2.

Low pass filter 216 prevents noise from being added to the information signal. Receiver of the present invention A five-pole elliptic filter with a cutoff frequency of 1.5 MHz is used as the low-pass filter 216. It is provided. of the dither signal above the noise equivalent bandwidth of the low pass filter 216. The average voltage level is greater than the approximately 5 step size of the analog-to-digital converter. Should. The dither signal will not cause clipping in the AD converter 222. care must be taken.

Analog-to-digital converter 222 converts analog signals to digital signals. . This converter is capable of accepting signals over the dynamic environment of the intended receiving wave application. must be able to do so. For land mobile communications applications, a minimum of 10 A/D bits is required. theoretical research shows that the dynamic range offered by 12-bit converters is It has been shown that it must be equivalent to all existing conventional land mobile receivers. ing. The two primary important factors regarding analog-to-digital converter 222 are: sampling rate and step size. The step size is the omega noise floor Determine the amount of gain required before the converter to take over. large step size The greater the gain, the greater the required gain. If the amount of gain is large, there will be non-linearity in front of the converter. A shape effect occurs. The conversion speed determines the acceptable bandwidth of the front-end filter, It also reduces the required gain by distributing the quantization noise over a larger bandwidth. So conversion speed is also very important.

800MHz digital signal receiving analog/digital converter of the present invention Converter 222 is a two-stage 10-bit converter with a step size of approximately 3 mV; can perform conversions faster than 50MR2. According to the principle of the invention , Bandwidth when receiving a signal of 0.3μ■ sampled at a rate of 20MHz To achieve a post-detection signal-to-noise ratio of approximately 10 dB with a 30 kHz receiver, approximately 54 dB of front-end gain is required. Large gain before converter 222 The amount required limits the nonlinear performance of the system. Intermodulation ratio (IMR) is limited to about 65 dB, which is somewhat lower than achieved with conventional receivers. To those skilled in the art can achieve IMR>80dB by reducing the step size by about 200μVC'knee. It should be clear that it can be done.

This value is comparable to most of the existing conventional 800 MHz receivers. Ru.

Referring now to FIG. 3, a digital zero IFi compatible with the implementation of the present invention The selection section (DZISS> is drawn in the form of a block diagram.Digital zero IF selection The selection section includes the front end circuit 200 in FIG. 2 and the bank end DSP 120 in FIG. and the modulated digital RF output from the front end 200. to convert the signal into a baseband signal that is processed by the backend DSP 120. Operate. The DZISS300 has an in-phase mixer 304, a quadrature mixer 306, and a digital Digital quadrature local oscillator (LO) 302 (in-phase LO signal @309 and quadrature LO double signal) 11), two "fast" digital low-pass filters 308 and 310 ．． Two low-speed digital low-pass filters 312 and 313 and a clock source ( (not shown).

According to an embodiment of the present invention, the same digital information is shared between human ports 303 and 307. They are added to a phase mixer 304 and a quadrature mixer 306, respectively. In general, The ports 303 and 307 are not single lines, but rather multiple bits (e.g., 10 or are a plurality of lines representing digital words (12 bits). for a given purpose The actual length of the digital word used depends on the required resolution, required dynamics, Depends on a number of factors, including the cleanliness and frequency at which the received RF signal is sampled. It changes. For example, a word length of 12 bits is sampled at 20 MHz. It is believed to exhibit acceptable performance in receiving typical wireless signals.

Mixers 304 and 306 have second input right angle LO lines 309 and 311, respectively. It is growing. If only one LO low signal is connected, as in the case of the AD output signal above, (i.e., sine and cosine waveforms) with multiple bits separated by 90' in phase. It is a signal representing a discrete time period. Mixers 304 and 306 are Kafka with A/D input. Performs arithmetic multiplication with word 0 and outputs the output ports of mixers 304 and 306. are applied to the input ports of digital low-pass filters 308 and 310, respectively. Round the result to form the output word. Determination of output signals from LO and mixer The digital word length can be selected to provide acceptable noise performance. . The longer the digital word, the more quantization it takes to represent the signal. level will be available.

As is well understood by those skilled in the art, smaller quantization increments improve noise performance. be done. The quadrature mixing process described above can be used for analog ``zero IFJ'' or direct conversion reception. Similar to what is done on a machine. However, a truly linear digital multiplier If used, the secondary mixing of unwanted signals to DC, which occurs in the case of analog direct conversion, and other undesirable effects are eliminated.

The quadrature mixing performed by multipliers 304 and 306 converts the desired signal to a center frequency of approximately OHz. In this case, the amount of frequency conversion is controlled by the channel frequency control. This can be determined using the device 305. The resulting quadrature signal is then low-pass filtered to Remove external noise and unnecessary signals. In a preferred embodiment of the invention, this selection is done in two stages. It takes place on the floor. The first stage consists of fast iterative digital filter sections 308 and 310. is formed. Digital filters 308 and 310 are identical in structure and repeat can be formed from a filter topology, which is discussed further below. I will explain it in detail below. each of the remaining) translations is a ``slower'' iteration This is done by routers 312 and 313. See below for information on choosing such a configuration. This will be explained in detail. Following the filtering process, the digital signal is passed through the filter for further processing. output to the backend DSP 120.

FIG. 4a is a schematic block diagram of the digital oscillator described in connection with FIG.

The function of a quadrature oscillator is to digitize the cosine and sine waveforms used in the quadrature mixing process. Let us recall that it is the creation of a talized and sampled form.

The digital zero IFi selection section realizes accurate and stable digital representation of these waveforms. It depends on the ability to generate. A grade of digitizer particularly suited to the requirements of the invention The system is implemented based on the concept of ROM (Persistent Memory) lookup.

complex sine wave W(1)-ej27'CfC1 Consider the generation of a digital signal with samples of . Here f. is the required oscillator It is the frequency.

According to traditional communication theory ej27Tf1=cos l f 10jsin 2x fotc In this way, the desired cosine and sine waveforms can be converted to the real part and the complex sine waveform, respectively. and the imaginary part.

Cj27r　Sample form of fCt replaces continuous time variable t with discrete time variable nT It can be obtained by Here, n is a counting integer (1, '2.3...), T is the rimbling period and is equal to 1/fS-1/sampling rate. This discrete The time signal is therefore w(n)-ej27cfc”T) is equivalent to

The ROM lookup method for generating this signal uses a time variable in addition to the frequency variable fo. It can be obtained by making it divisible.

Let f = kf / 2N (k and N are integers), then S Ba, It turns out that all you have to do is survive. One way to generate these values is through direct ROM programming. Although it is called backup, it basically contains 2N pairs of values (cosine and sine). consists of using a ROM table containing an integer nk (proportional to the phase). address by the register in which it is located. The phase register corresponds to each sample time (n) to the value k (desired frequency f.

). The frequency resolution obtained is △f=f/ 2N, where 2N([B individual frequencies can be generated).

Depending on the application, the direct ROM lookup method may use large amounts of RONl. Ru. The size of the ROM can be reduced somewhat by taking advantage of the symmetry of the cosine and sine waveforms. Can be done. Due to this property, the number of entries in the table can be reduced from 2N pairs to 2N/8 pairs. can be done. Even with this reduction, the ROM size may still be too large. Ru. In such cases, factored ROM lookup and This can be achieved without reducing the size of the ROM by employing a technique called ROM.

The digital local oscillator 400 of the present invention uses a unit-sized phasor as a "coarse" phasor. We take advantage of the fact that it can be decomposed into multiple accumulations: phasor and phasor. A factorized ROM lookup method is used. In this way, the unit size The phasor ejφ can be expressed by dividing the signal into ejφc − ejφf. can. Therefore, a phasor of unit magnitude is the product of a separate coarse phasor and a phasor of unit magnitude. This can be realized by storing the phasor in ROM. These two The phasors are multiplied together and combined to produce the discrete time sine and cosine required for orthogonal mixing. yields the value of . The advantage of this number decomposition is that it stores the coarse and product phasors. The amount of ROM required for direct RON can be significantly reduced compared to the one-lookup method. There is C. The cost to be paid for this ROM size reduction is roughly and a circuit that performs complex multiplication of fine phasors. In general, complex numbers The multiplication of can be realized using four multipliers and two adders. product value phasor Correctly chosen and assuming that the cosine of a small angle can be approximated by 1. The ROM for the cosine product value phasor can be deleted. In addition, small angle By approximating the cosine value to 1, we can calculate two multiplications from the multiplication structure necessary to generate a complex multiplication product. Calculators can be eliminated. As a result, the cost and cost of configuring the number resolution ROM Jagged edges are saved.

In addition, referring to FIG. 4a, the digital direct Corner local light (Tatsuki 400 is drawn in block diagram form. Frequency within the band to be pulled, expressed as an N-bit binary number proportional to the desired frequency The number information is loaded into channel frequency latch 402. Channel frequency ramp 402 can be implemented in many different forms. For example, if N=20 Five cascaded Motorola 74LS175 (quadruple flip-flops) lop) create a configuration acceptable to others. Those skilled in the art will understand the It will be appreciated that the database 402 can be loaded in a variety of ways. and For example, in single frequency radios, the channel frequency latch is permanently loaded with a single binary number. can be coded. In a multilayer wave number radio, the channel frequency latch 402 Calculated by EPROM or ROM lookup table or other microprocessor. can be loaded from the calculated and latched one.

The output of channel frequency latch/102 is coupled to binary adder 404. Current Those skilled in the art will be aware of the functional blocks in the following description of digital quadrature local oscillator 400. All bond lines between tracks are actually binary words to multiple pins and are a single connection. You will understand that there is no such thing. The output of the Korean device 404 is the phase accumulator 40 It is combined with 6. Phase accumulator 406 is configured as an N-bit binary latch. This is the address of the next location in the ROM to be addressed. used to hold. In this way, the phase accumulator 406 Outputs are cosine coarse value ROM418, sine coarse value ROM416, and sine product value ROM4 14 (the product value cosine ROM is approximated by 1, so it is not necessary) ).

Additionally, the output of phase accumulator 406 is sent back to adder 404 to channel The channel frequency information in the channel frequency latch 402 is expressed as a binary number. (modulo 2N>.The output of the phase accumulator 406 is It is updated once. Clock pulses are generally at the sampling frequency. This 2 As a result of the base addition, phase accumulator 406 stores the last address and channel frequency ratio. The binary sum (proportional to the phase) of the binary vector in the switch is held. Become. This number is the quadrature local oscillator signal cos 2πf nT and 5ir12πfo It shows the next address necessary to create nT.

In the preferred embodiment, the ROM is sized to convert the digital dither signal into a phase accumulator. In addition to the output of mulrator 406, the result can be truncated before being addressed to the ROM table. or equivalently, the frequency resolution can be reduced by increasing the size of the ROM. It can be improved without increasing the quality. The frequency resolution of the local oscillator is It is defined by the data path width of the mulrator (N>) and the required sampling speed f8.

The most straightforward way to increase frequency resolution is to add significantly more bits to the phase accumulator. In addition to this, the dents in the ROM table should be made too large. However, this is the size of the ROM. Because the increments must be doubled for each bit added to the phase accumulator. The solution can be expensive. Other options set the bits to phase add to the mulrator but truncate additional bits before doing the ROM lookup. That is. This can severely round the phase and create spurs in the local oscillator output. become. To avoid this spur, the low-level dither signal must be cleared before truncating. added to the emulator output.

In accordance with the principles of the present invention, the binary dither signal is By adding it to the output of It is possible to increase the frequency resolution of digital oscillators without introducing . To do this, the digital oscillator 400 is supplied with a uniform probability density pseudo of L bits wide. The L-pimil dither source 408, which generates a quasi-random "white noise" signal, is I'm getting 2 digits. The dither source 408 is a phase accumulator 4067J). sample to generate a new dither word for each code output. clocked at a clock frequency f. N-bit dither word is dither source 40 Adding M=N-L to zero to the L-bit dither word output from 8 formed by. This composite N-bit dither signal is applied to an N-bit binary adder 410. is added to the N-bit output of phase accumulator 406, modulo 2N. Ru. The sum output of adder 410 is then truncated to M bits (truncation not shown) . In practice, this truncation process simply occurs at the output of digital adder 410. This is achieved by ignoring the lowest digits. The truncation operation itself is ROM-sized. Take into account that the intensity has decreased.

Quantizing or truncating a binary phase word distorts the resulting sine or cosine waveform. Or noise is generated. Since the phase is a periodic function (sawtooth), it is not caused by quantization. The noise is also periodic, with some irregularities. Periodic noise is the output of the oscillator. This creates discrete "spurs" in the dregs vector whose level is below a certain threshold. Exceeding this is undesirable in most applications. Before phase addition Adding a dither signal makes the phase noise irregular, making the output more desirable white. A noise spectrum results. A binary phase word is represented by an N-bit binary word. It will be done. The dither signal consists of L bits of pseudo-random binary words; is added to an N-bit phase word. From this process the binary word N=L+ M bits result. This binary word is then truncated to a binary phase word of M pi]. However, it is relatively free of the spurious signals mentioned above.

The effect of phase matrixing on the oscillator output noise can be shown by the following analysis. . The required oscillator output is described by the following equation:

w(n) −8j27U fonT=. jφ(n) phase angle with error B(n) If you make it a child, the actual output will be written as follows.

The error introduced is ♂(n> is very small (<<1) In that case, ej’e(n) is 1+jc )(n), so The spectrum of E(n) is simply the frequency of the spectrum of phase quantization noise n) can be viewed as a transformation (and insignificant scaling by j). this , if e(n) is random or "white", then E(0) is also That's how it will be. Furthermore, the power of F(n) is equal to the power of δ(n), and the phase noise The output noise level generated by sound can be easily estimated.

The selection of the power level of the dither signal is based on the noise whitening effect and the output noise power level. A compromise between the two will come into play. Increases dither power (more bits in dither signal) (by increasing the number), the noise becomes whiter, but the total phase noise The power of the body increases as well. If the dither signal exhibits a uniform probability probability, then If we choose L = N' - M, this will completely whiten the phase quantization noise. This is the minimum dither signal needed to produce the desired level of dither power. I know how to cheat. Therefore, in the preferred embodiment, the number of dither bits is Equal to the number of bits discarded in the truncation process (). Dither signal other than uniform probability accuracy It should also be noted that . However, uniform density is the most easily This is desirable because it allows When L = N - M, the change in phase noise (power) is equal to twice the isolateral phase change of the signal. Desired frequency determined from N and f For resolution, L and N1, and therefore the required ROM size, are determined by the oscillator output. Depends on the acceptable level of white noise in the power.

For example, in the case of f, -20MH7, N-20 bits, the frequency resolution is 19.0 It is 7H2. Truncated to M-17 bits without dithering (ROM size reduced to 1/8 This results in a spur in the oscillator output, which is generated for one particular frequency. is 98 dB lower than the desired signal level. Add a dither signal of 3 bits before truncation. When the error signal increases, the error signal turns white and the spur is removed. According to the principles of the invention, the The frequency resolution of a digital optical oscillator is simply Adding more bits to frequency and phase latches and dither signals This may result in an unexpected increase in size. The size of the ROM determined by M is It doesn't change. The M-bit binary word remaining after truncation has its output stored in ROM41. 8.416 Combined with ROM address latch 412 connected to Onibi 414 ing. Upon receiving the address, ROMs 418, 416 and 414 outputs the digital binary words present in the address to its respective output port. Ru. A digital quadrature signal is then generated arithmetically from the three binary numbers.

As mentioned earlier, the output signals of ROMs 416.1 and 418 are the cosine and is a binary number proportional to sine and sine. The output signal of ROM414 is proportional to the sine of the fine phase. It is a binary number. To minimize the error of the fine cosine approximation, use the fine phase value is determined by values concentrated around the positive axis. The output of ROM address latch 412 is M Number of M bits divided into C bit coarse address and Mf bit fine address , where M=Mc+N4f. The coarse phase is 2π (an integer corresponding to Po It is. The fine phase is 2πcpf-2N4f-1)/2N4, and Pf is N4f It is an integer corresponding to the precise address of bits. For example, N'lc = 10. M If f = 7, the entries in the ROM table are structured as shown in Tables 1 and 2 below. will be accomplished.

Table 1 To generate a cosine waveform (i.e., the real component of a complex waveform), the positive phase (lIIR The output of OM418 and sine product (ilOM414 is first multiplied by multiplier 426) let The output of Toki''!426 is sent to the adder circuit 440, where it is added to the cosine coarse R Subtract from the output of OM416 (two's complement form). From this sieve, the cosine value is This is output to the ball l~441 and connected to the right angle mixer 9304 in Figure 3. It will be done. To generate the sine value of digital right angle LO, use cosine coarse ROM416 and sine The output from the product value ROM 414 is multiplied by the r3 generator 428! i) [Put together.

The output of the multiplier 428 is sent to an adder circuit 442, where the positive phase (iIROM41 It is added to the output of 8. Addition σ circuit 442 connects discrete time sine via connection 443. outputs a value digital word, which is coupled to quadrature mixer 306 in FIG. It will be done. 1) Therefore, the discrete time values of the sine and cosine signals are measured in a sensible manner. Thus, full 90' phase control is achieved using minimal ROM space.

Latches 420.422.424.434.6 and 438 are the high It has a pipeline configuration that facilitates high-speed operation. Delays 430 and 436 are various signals Provided to equalize path delays.

Frequency-resolved ROM LO is a ROM that maintains acceptable frequency resolution. decrease a. For example, to realize a digital right-angle LO operating at 20MH7. In order to It is possible to obtain the pleasure value sine RO! vM14 can be configured with 128x8 ROMT: Wear. From now on, using approximately 34,000 ROMs, the frequency will be approximately 20H7. Resolution can be obtained. The configuration of the number-resolving ROM is as follows, excluding the phase combinator. There is no feedback circuit, so it can operate at high sampling speeds. is desirable. This allows the rest of the LO circuit (particularly multipliers 426 and 428 to is the main speed bottleneck) to achieve very high speed operation. can be done. The pipeline configuration is well understood by those skilled in the art, and the multiplication It consists of introducing a latch at a certain critical point, such as inside the white meat. did Therefore, the number resolution ROM LO indicates the predetermined frequency 82'? f discrete time digital A quadrature signal can be written as an outgoing signal.

Digital adders suitable for use in conjunction with the apparatus of the present invention include several 74L A type configured by connecting 3181 type 4-bit logic unit devices in parallel. It is.

These devices are located at Motro, Private Box 2092, Phoenix, AL 85036. Titled ``Mo1-0-La Schottky TTL Data Book'' available from La Co., Ltd.1 The information is shown and explained in the Data Manual. ROM418.416 and 4 14, California 94088 → Nonnyvale, East Argus ・Avenue 811, 1 Box 3409, Cidanetics Corporation "Signetics Bipolar Memory Data Manual J ( 82L3181 described in 1984). can be achieved. 426 and 1428 and I, for example, Caliph 4 T.R. Gubrico Inc., PO Box 2472, La Jolla, Nia 9203B MPYO manufactured by Holated's D.R.Grebru electronics group This can be realized by I6K.

The amount of coarse value ROM required takes advantage of the symmetry of the cosine and sine waveforms, which The size of the unit in the first octant (i.e., the first 45°) of the unit circle can be further reduced by storing only the value of the phasor at the moment. Current The manufacturer believes that a unit-sized phasor is a sine or cosine that rotates through 360°. It is necessary to define L2 to represent the value of . Due to the symmetrical nature of the sine waveform, the unit circle The values of the cosine and sine waveforms on the first octant are the same as the values of the waveforms on the other octants. be. However, the sign changes and the roles are reversed (T, that is, sine becomes cosine, and The opposite is true). Therefore, the only place-valued phasor needed is which octant has an indicator of whether a phasor is currently present, according to the current octant. The outputs of the coarse cosine ROM 416 and coarse sine ROM 418 are made negative, that is, the sign is changed. Any circuits to be replaced) and/or replaced are those in the first octant.

The octant indicator is easily created using the three binary bits of the ROM address. be able to. For example, the three most significant bits (MSBs) are The remaining bits can be used to display the data and the remaining bits can be stored in ROM for the digit value phaser. can be used to address.

Figure 4b shows a type of digital dither generation compatible with the digital oscillator of the present invention. It is a schematic diagram of an example of a container. The digital gamma iser signal has several known pseudo-random - Can be generated using any of the sequence generation techniques. some form of data The generator or random number generator is RADJOELECTRONIC3AND Cf) Ml(tJNlcATIONs, Vol, 25. No, 4. pp.

88-90.G in 1982, 1. In Donov's paper "Fast Random Number Generator" shown and explained.

Referring now to FIG. 4b, a frame that can be advantageously utilized in embodiments of the present invention Feedback Shift 1 ~ Register Pseudo Random Sequence Generator as Schematic is shown. The sequence generator in Figure 4b is an L-bit digital dither generator. It is used to provide a signal to binary adder 410 of Figure 4a. Dither generator 4 ．． 08 by a plurality of interconnected flip-flops 464 to 499. It includes an R-bit shift register 460 that can be configured. of the present invention In the preferred embodiment, the dither signals of the parallel three bits 1 to 1 are each connected to a flip-flop. The outputs of 478, 491, and 499 are taken out from the shift register. Exclusive The inputs to OR gate 462 are flip-flops 464.493.49B and 499 output.

The output of exclusive OR gate 462 is coupled to the input of flip-flop 464. Ru. The shift register generates a 3-bit pseudo-random dither signal, which is added to the output of phase accumulator 406 in FIG. 4a. Examples of the present invention Flip-flops 464-499 and exclusive OR gates used in Not only the 462 but also other devices can be any of several well-known logic devices. can. However, high speed TTL is particularly suited to embodiments of the present invention. other logic Constructions using families will also be apparent to those skilled in the art. Dither generator of Figure 4b is a digital dither generator that operates satisfactorily in combination with the digital oscillator of the present invention. This is shown as an example of one type of vessel. Those skilled in the art will appreciate that the digital dither generator is In order to whiten the phase noise resulting from truncation by 1, the period is at least 2. 1 pseudorandom number of L bits that is long as N number and whose probability probability is uniform Many other digital dither generators are also advantageous for sequencing. It is clear that it can be used.

As shown in Figure 3, the intermediate frequency (IF) filter section It receives data at a rate of samples/second and converts the received signal to dc (zero IF frequency). The received signal is low-pass filtered to extract the desired signal, and the signal is converted into the buffer shown in Figure 1. to the back end 120 at a (dramatically) lower sampling rate. Like In a new implementation, lowpass filtering and sample rate reduction are not separate operations; The pulling speed is determined by the amount of unwanted signals (which can cause aliasing if not removed). As > is filtered, it gradually decreases between filter sections. input sump operating at a ring speed (f, -20 MHz in the hook-shaped embodiment described here) The filter section is only the first part. Other circuits operating at this speed are quadrature local oscillators. It is a shaker (LO) and a mixer. In this way, digital zero IFi selection It is this high speed circuit that sets the upper limit on the overall operating speed of the section. High-speed operation is based on For modern digital receivers, front-end sample-hold and A This minimizes intermodulation problems that occur in the D converter and allows reception of sufficiently wideband signals. It is very important to make sure that

FIG. 5a is a block diagram of the "fast" narrowband low-pass filters 308 and 310 of FIG. It is. Quadrature local oscillator 302 and mixers 304 and 306 are non-feedback circuits (mainly ROMs and multipliers) in pipeline or other form Its speed can be increased by parallel configuration. However, the low-pass filter section 3 Since 08.310 is configured as an iterative (infinite impulse response) filter, , it is not possible to increase the speed by using a pipeline method.

Its speed is determined by the maximum delay around the closed (feedback) path. Book When implementing the low-pass filter of the invention, this path includes two digital adders and one Includes latches. Limits the AD sampling rate and therefore It is this path that has the potential to limit the overall performance of data reception. This emergency Due to problems in achieving high speeds, the filter is two 10MHz TTL filters. RU i+ was obtained by inserting the . Usually the sampling rate is lower The aliasing problem associated with adding zeros near unwanted filter poles is In addition, J2 is relieved.

The "high speed" low frequency section 546 of Figure 5a has two half speeds as shown in Figure 5b. and a mixing filter.

This modification allows the digital IF section to operate twice as fast as it would otherwise be possible. This gives rise to the possibility of improving the performance before digital reception of the present invention. Ru. The "resolved" filter of the present invention is illustrated in conjunction with FIGS. 3 and 5. FIG.

Other filter decomposition techniques are available, e.g. N　ACOtlSTIC3, 5PEECH, AtsushiD　5IGNALPROCE SSrNG, Vol, ASSP-24, No. 2. April 1976 Noem. Belanga, G. Bonarotto, and M. Koudrikos, “In Polyphase Networks” "Digital Filtering: Sample Rate Modification and Application to Filter Banks" ing.

Mixing filter 554 is necessarily a non-repetitive filter. This>J? The combined filter is shown in Figure 8. As shown in more detail, f,/2 (z=-1) uses two zeros. Such a filter uses an adder and a You can just configure (without multipliers) with a switch and thus add Minimal hardware is required.

Disassembly requires additional hardware, but requires two 1/2 speed circuits. The power to do is the same as a single full speed circuit (considering the additional power of the mixing filter) Therefore, power consumption only nominally increases (in case of CM OS).

FIG. 6 is drawn in vi size to show the decomposition process in detail. especially , 6a, Fig. 1, when the input Kazan springing speed f is 20 MHz, the first The response of the original configuration of the two-pole section is shown. Figure 6b shows two 10MHz Figure 6c continues to show the ``decomposition'' properties resulting from the ``mixing'' filter. This shows the data response. Finally, Figure 6d is a combination of Figures 6b and 6C (V). straw, cascade), which is 10Mt-(z). arises from the two zeros at f,/2, canceling the two nearby poles). The facts cannot be distinguished from Figure 6a.

The decomposition filter can be expressed as follows.

2N.

y(n)=Σy(ni)hd(i) 10X(n)i・1 Here, X and y are the multi-h12 filter input and output, respectively (i.e. , these have a real part and an imaginary part).

Also, hd is expressed as the polynomial coefficient of the decomposition filter, and ND=2 is the original full speed filter. It is the order. The 20MH2 decomposition filter is in terms of z-2 (as shown in the next section). Therefore, it can be realized using a 10 MH2 circuit. child In the circuit of hd(i)=hh(+/2), i even number Oi odd number Here hh is the original high speed coefficient.

Next, the decimating (taking 1/10th) filter can be expressed as follows: can.

2N.

y (n) − Σ￥ (n-i) hh (i/2) + x (n) i=2 Step 2 If we change the variable i to 2, this sum becomes simple as follows.

y(n)=Σy(n-2j)hi(j) 10X(n)j・1 From this formula, the input X and output y of the decimating filter are shown in Figure 5a. It can be broken down into two streams as shown below.

x'V' (m) = x (2m+y) V(y)(m)=’! (2m+y) however y=mod　(n,2>?/) of the decimating filter on O(0,1) Substituting 2m+1 for n in the summation, we get D V(n) = UV (2m-2j+1) hh (1+x(2m+y)j・1 is obtained.

Finally, the two decomposition decimating, filters (y=0.1) are expressed as follows: I can do it.

j・1 Assuming that the desired filter has poles z=z, the corresponding filter characteristic is It can be expressed as follows.

If this pole is "repeated" 180" apart, the following properties are obtained.

), respectively, Z2. =z 2 (lWi two 1s /2 speed filter.

The low-pass filter section of the digital zero IFJ selection section configuration of the present invention uses the following format. , which is written in terms of coefficients a and b. Here b=ca.

The coefficient for the pair z, Z,'' of (※) is a@2d b=d2−+−q2 It is.

Therefore, the coefficient of the 1/2 speed filter is the coefficient for the full speed case by analogy with the full speed case. It can be expressed in terms of numbers.

This design is shown in Figure 5b. The second order IIR filter is IEEEETRANSACTI ONS ON CIRCUITS AND 5YSTEH3, Vol, CAS- 27°N0112. December 1975 Agarwal, A, C, Bur Rus C.S.'s paper "A new repetitive digital digital signal with very low sensitivity and rounded noise" Tal filter structure”. Agarwal and Burrus proposed The proposed filter structure H is constructed around all feedback loops for the purpose of the present invention. Fixed to minimize lag. The structure of the filter l1r4 of the present invention is shown in FIG. vinegar.

All digital filter structures are basically built from the same three components. It is. namely adders, multipliers, and delay circuits (generally latches or R AM). All factors that affect the performance of digital filters are The seed parameters are quantized, i.e. they are not available in the analog filter. It has to do with the fact that it has finite precision rather than infinite precision that can be used. De The finite precision of a digital filter basically depends on the configuration of the digital filter. This results in three major performance effects that must be controlled.

Truncation rounding of coefficients is one of these effects. appears in the digital filter Constant-valued coefficients determine its frequency response. Digitize these coefficients with a finite number of bits rounding makes the response of the filter permanently predictable. Change. This is similar to changing the RLC value with an analog filter. . However, digital filters are subject to temperature fluctuations like analog filters. You will not suffer any damage. In general, the higher the Q of the filter (i.e. , if the bandwidth becomes narrow compared to the sampling rate), then why not adopt a special structure? However, the rounding of the coefficients further distorts the frequency response. Filter structure wisely The selection of IF filters is generally extremely narrow band, i.e. high Q. In light of the fact that it is a filter, it is necessary for important matters.

Rounded noise is another property that must be controlled with digital filters. It is an ability characteristic. The data entering the digital filter is rounded to a finite number of bits. and must almost always perform coarse rounding at some point within the filter. . This rounding operation creates an error signal, or noise signal, in the digital filter. The number is generated. For example, if the length of the digital word used in the filter is 16 If the coefficient is represented by 10 bits, then each multiplication operation results in a 25-bit product, which is rounded to 16 bits before the result is returned to memory. There must be.

The last major effect that must be controlled by a digital filter is overflow. level. The fact that data samples are represented by a finite number of bits There is a maximum allowed absolute value for each node in the filter, which is overflow phenomenon (generally when using two's complement binary arithmetic (poor-around). This maximum allowable data value is Combined with the level of rounding noise, it determines the dynamic range of the filter.

Several conventional structures can be used to construct digital filters. Ru. A straightforward design method is to divide the first- and second-order direct form filter sections into a given filter order. It is a cascade connection until the number is reached. The advantage of this method is its simplicity and regularity. and the actual filter δΩ 31 is easy to use. However, the traditional method , most of the time, to realize a narrowband filter, a high-precision filter (for example, 16 bits) is required. There are a number of drawbacks arising from the fact that a filter coefficient representation is required. others Highly complex multiplication (for example, 16/20 bits) is applied to the feedback path of the filter section. ) is necessary.

Multiplication imposes severe speed and time constraints on the operation of the filter. Additionally, speed logic Pipeline configurations commonly used in circuits can be used for feedback loops. I can't do it.

Finally, high precision, high speed multipliers consume enormous amounts of power.

Referring now to FIG. 7, the digital low-pass filter section 700 is shown in block diagram form. It is depicted in The filter used in DZISS has a narrow bandwidth and High-speed, sensitive to negative effects of parameters related to digital filters An iterative filter that is optimized to have a low (feedback, scaled, and summed at key points in the structure). 7th The second-order narrowband low-pass infinite impulse response (IIR) filter in the figure is decomposed in Figure 5b. Used for "fast" low-pass filters, operating at the speed of an AD converter. This high speed operation Disassembly helps achieve this, but requires additional hardware. i.e. , two secondary IIR parts instead of one, and an otherwise unnecessary secondary FI The R section must be added.

Digital low pass filter 700 is implemented by functional blocks 550 and 552 in FIG. 5b. Perform the function you drew. The digital low-pass filter 700 consists of four digital adders ( two's complement) 704.708.712, and 716.2 digital delays. It consists of latches 710 and 718 and two binary shifters 706 and 714. It is. As noted earlier in the description of the digital quadrature layer oscillator 40Q, FIG. Individual connections of low-pass filters 308, 310, 312, and 313 shown in is a multi-bit digital word, not a single wire.

The input signal to the digital filter 700 is the reciprocal input signal of the digital adder 704. Added to cuff 02. The second inverting input to digital adder 704 is a digital is taken from the filter circuit delay 718 and fed back from the output cuff 20 of the filter circuit. . The difference (two's complement) obtained from digital adder 704 is then added to gain element 706 added to the input.

Gain element 706 transfers the shifted first sum signal to one of digital adders 70B. given as input.

Bit shifter 706 shifts the data word output from digital adder 704. All bits are N. bit (shift to the right (i.e., towards the least significant bit) and is multiplied by a coefficient C equal to 2-14C. This bit shift decodes the data lines. This is achieved by appropriately determining the path from the digital adder 704 to the adder 708. be done. In this way, high-speed operation of the digital filter section 700 is facilitated. Ru. This is because the bits are This is because there is no time delay associated with shifter 706.

Digital adder 708 lags the shifted first sum signal and is held at 710. The last outputs of the digital adders 708 are added together. Roughly, digital addition The last output of the circuit 708 is applied to a digital adder 712. De The second inverting input to digital adder 712 is taken from digital delay 718 However, this is taken from the digital filter output cuff 20, as described above. De The result of digital adder 712 is a bit series coupled to digital adder 716. Added to lid 714. Bit shifter 714 outputs the output from digital adder 712. Shift all bits of the input data word to the right into N8 bits 1 and 2. 'a is multiplied by 2a. Bit shifter 714 is not subject to time delay. This also facilitates high-speed operation. bit shifters 706 and 714, respectively. The associated parameter N and Na are the frequency distribution results of the digital filter section 700. control and generate the appropriate response for the intended application, as shown in the previous analysis. It is possible to select Digital adder 716 receives the second shifted sum signal is added to the previous output of 716 held in delay 718. The output of delay 718 is It is also the output of the digital low-pass filter section 700, and is first input to the adder circuit 704. A band-limited representation of the applied input signal 702 is shown.

Figure 8 shows a sampling rate of Block of a quadratic mixed finite impulse response (FIR) filter with a notch at /2 It's a diagram.

The input 802 to filter 800 is connected to the output of filter 700, as shown in Figure 5b. 20. According to FIG. 8, the digital filter 800 digital delays 810 and 814 and digital adders 812 and 816, respectively. It includes coupled digital shifters 804, 806, and 808.

Digital shifters 804, 806, and 808 each have a gain of 1/'4.1. /2 and 1/4 are used at 1 node, on the unit circle, at 1/2 of the sampling frequency. A filter with two zeros is realized. These digital filters Shift input 802 to the right by 2.1 and 2 bits, respectively. like this "Human shift" can be achieved by connecting wires through appropriate routes. These gain operations do not consume any real time and do not require any real hardware.

The first partial sum is calculated using the scaled output of gain element 806 as the first input. The previous or last scale of gain element 804 obtained from gain element 810 is formed in adder 812 using the output as the second input. Similarly, Output 818 connects the scaled output of gain element 808 to the first input and delays The first partial sum before the adder 812, that is, the last one, which is 1 from the element 814, is obtained as a second partial sum formed in adder 816 using as the second input Ru. The transfer function of this filter can be written as: To calculate the output, use this: compared to two additions and one latch operation in the IIR part. , only one addition and one latch operation are required, so the FIR mixing filter easily operates at full input sampling rate (20MH2). Another design It is possible to operate the calculator at a lower sampling rate using a separate control circuit. 　□I can. This allows the FIR filter to incorporate decimation into the filter operation. By combining these, it is possible to operate at a slower speed. figure However, the output required by subsequent filter sections operating at low sampling rates is Only force can be calculated. In CM OS 6m configuration, power consumption depends on operating speed. It generally decreases as the temperature decreases. Therefore, the power consumption of the FIR mixing filter The cost of the control circuit to be installed can be reduced.

The "fast" filters 308 and 310 and the "slow" low pass filter 312 of FIG. It is desirable to reduce the sampling rate, or decimate, between 313 and 313. Yes. As is well known to those skilled in the art, the degree of possible reduction in sampling rate is ” Determined by the amount of attenuation performed by the low-pass filter.

For example, if you use an input sampling rate of 20 MHz, you can use a "fast" filter. If we combine them as a decomposition filter with the coefficients listed in Table 3 below, we get 2MH7. Output sampling rate can be used, 100% by "fast" filter Aliasing protection over Db can be provided.

"Low speed" The low-pass filters 312 and 313 are realized by several stages of two-pole filter sections. be able to. For example, in the case of three stages, each of the stages 9a, 9b, and 9 It has the structure shown in Figure C and uses the coefficients listed in Table 3. Here, set low speed 1, low speed 2, and and low speed 3 correspond to figures 9a, 9b and 9c, respectively. Thus the sump The ring speed can be reduced from 2 MHz to 80 kHz.

An alternative hardware-saving configuration is the sample flow for in-phase and quadrature samples. , and the use of three-stage time-division multiplexing filtering. . This includes a filter that operates at two speeds that are faster than the non-multiplexed design. is necessary, but the sampling rate is 10 times lower than a fast filter, so this The multiplex filter will also operate at a speed of 115 in the 16th wave stage.

Figure 9a shows the first time division multiplexing format used in the time division multiplexing format of the "slow" low pass filter. FIG. 2 is a block diagram of a heavy second-order low-pass IIR filtering setup. From Figure 9a to Figure 9C, the 7th Figure 3 shows a time division multiplexed format of a filter structure similar to that depicted in the figure. The structure in Figure 7 and The main difference from the multiplex format in Figure 9 is that the length of the delay element is doubled. . So instead of using z-1 elements implemented in single latch hardware, , using z-2 elements implemented as two latches configured in series. this The effect of the structure is that the filter alternately processes each sample with in-phase sample processing and quadrature thumping. It is to process the file. In the following description, the operation of FIG. 9 will be explained in detail. digi After being processed by a filter 900a, the signal passes through the 26th wave stage 900b and then to the 90th wave stage 900b. It is coupled to the 36th wave stage indicated by 0G. Digital filters 900a, 900 The overall filter structure of bS and 900c is the same and therefore digital -Filter 900a (will be explained in detail).

However, the data diameter of digital filters 900a, 900b, and 900C The path and filter responses are shown in Figures 9a, 9b, and 9C and Table 3, respectively. Like, it's slightly different.

The digital low-pass filter 900a includes four digital adders (two's complement a) 904. a, 908a, 912a, and 916a, 910a and 918a (two each) 4 (hard digital latches), and 2 (hard binary shifters 906a and 914a). It consists of The input signal to the digital filter 900a is a digital It is applied to non-inverting input 902a of adder 904a. Digital processing device 904 The second inverting input to a is taken from digital latch pair 918a and is connected to the filter circuit. is fed back from the output 920a of the path. obtained from digital adder 904a. The resulting difference (two's complement) is then input to the digital adder 908a as one input. is applied to the input of shifter 906a from P1 to provide a shifted first sum signal.

Bit shifter 906a outputs the data word from digital adder 904a. All bits of N. Shift one bit to the right ('g, toward the least significant bit). and multiply by a factor equal to 2'c. Bit shift is done by digital adder 90 This can be implemented by appropriately routing data lines from 4a to adder 908a. child In this manner, high-speed operation of the digital filter section 900a is easily performed.

It is similar to the time-delay cage system present in coefficient multiplication performed in conventional multiplier circuits. This is because the lid 906a does not exist.

Digital adder 908a adds digital adder 90 to the shifted first sum signal. The output of 8a is held in latch pair 910a and added after two sample times have elapsed. The Furthermore, the output of digital adder 908a held in latch 910a is digital. is added to digital adder 912a. Second inversion to digital adder 912a The input is taken from latch pair 918a, which, as previously described, is a digital It is taken from the output 920a of the filter. The result of digital adder 912a is A bit shifter 914a is coupled to a digital adder 912a. B The shifter 914a generates a delay between the data output from the digital adder 912a. This also facilitates high-speed operation. It is attached to focus shifters 906a and 914a. The related parameters No and Na are the frequencies of the digital filter section 900a. control the number response, but should be selected to produce a response appropriate for the intended application. Can be done. Digital adder 916a delays the second shifted sum signal 9]8 Add to the previous output of 916a held in a. The output of delay 918a is digital. It is also the output of the low-pass filter section 900a, and is first added to the input of the adder circuit 904a. 9 represents a band-limited form of the resulting input signal 902a.

Those skilled in the art will appreciate that it is possible, for example, to It will be clear that significant sample rate reductions can be made. sump Slowly reducing the sampling rate will result in an output sampling rate for the input sampling rate. The considerable advantage is that it provides much more flexibility in determining the speed ratio. Cheating. This reduces the △D sampling rate, which constrains the output sampling rate. It can be set almost arbitrarily to match a preselector passband.

The output of the "slow" low-pass filter section Sufficient attenuation is added to the channel, so that the decoder from 2MH2 to 80kHz/＼ The aliasing caused by simation is centered around the desired frequency centered at approximately zero frequency. It does not interfere with the band.

After filter processing and decimation by the high-speed selection unit 114 in FIG. The digital signal includes a received digital signal with quadrature components. Receive data Due to the quadrature nature of digital signals, the phase information present in the original RF signal is lost through a series of processing steps. The data will be saved securely. The received quadrature digital signal is connected to the digital receiver bar shown in Figure 1. coupled to the backend 120. This digital reception is done by the backend (as mentioned above) Programmable general-purpose digital signal processing, such as 1. C.

It is conveniently structured. The radio back end 120 can recover data or generates the digital baseband signal used to generate the audio signal Perform any further processing necessary. In addition, the backend 120 of the radio is a recovery signal. Performs R final demodulation pre-filtering and demodulation post-processing. Figures 10 and 11 are digital signals. @Processing 1. A digital filter suitable for making the final pre-demodulation selection in relation to C. details of the data structure. FIG. 12 shows a diagram suitable for demodulating FM signals according to the teachings of the present invention. details of one suitable technique.

Figure 10 shows that the sampling rate can be roughly reduced from 80kHz7 to 40kHz7. Add further attenuation to make the 10 shows a fifth-order non-repetitive filter 1000 that produces only processing distortion. This filter is 40k It operates at a relatively low output sampling rate of Hz (complex samples). , a general-purpose digital signal processing device. This kind of processing equipment Typically pipelined multiplication operations 1004.1010.1016.1026.1 030.1036, and the accumulation operation 1006.1012.1020.1024, The "direct form" filter structure was chosen because it is well suited for and 1032.

FIG. 11 shows a direct filter structure 1100 with four ones and four zeros. show. This structure is used to smooth the passband response of a composite receiver filter. , a series of multiplication operations by a general-purpose digital signal processing device 1104.1112.11 18.1120, 1126.1132.1140.1146, and 1150, Accumulation operation 1106.1114.1116.1112.1108.1130°11 36, and 1144. Single precision (typically 16 bits 1 ~ Word length) calculations do not have sufficient dynamic range for mobile radio applications. Therefore, it is necessary to use double precision arithmetic with a DSP architecture. For those skilled in the art, By selecting different filter coefficients for the back-end DSP, the bandwidth of the R-end selector can be varied. It will be clear that it can be programmed. Also, different downsump Different wired gain using ring speed or multiplier-less low-pass filter section to obtain different selection bandwidths using can be done.

Figure 12 is a diagram of a digital FM demodulator that is compatible with the digital radio structure of this defense. It is. In practice, digital demodulation is performed by, among other things, digital signal processing equipment. That is one mission. According to FIG. 12, the limiter section 1202 has an in-phase channel opposite Scaling stage 1204 with calculation generator 1210 and product multiplier 1212 It has The product multiplier uses a scaled and rotated in-phase (bi) product. The reciprocal of the scaled and rotated signal is Multiplied by a scaled and rotated out-of-phase (Q′) component that produces a term equal to the value are combined.

Digital multiplier 1212 calculates the (, shadow width) of the input signal vector that may exist. Operates to ideally limit fluctuations.

The terms sent from digital multiplier 1212 are rotated and scaled signal vectors. This represents the pressure cut of the sample.

This term is an inverse pressure equal to the phase angle of the rotated and scaled signal vector. Processing is performed at the cut-off stage 1214. This quantity is coarsely calculated by digital adder 1214. The input signal vector when added to the coarse phase value output from phase accumulator 1206 represents the total phase angle of the sample. Generated 1 at the output of digital adder 1218 - the delay caused by the existing signal vector samples and the digital delay 1210 The difference signal from the output represents one sample of the output demodulated message.

Figures 13a to 13c show details of the phasor principle relevant to the present invention. This is a diagram. Now, referring to Figure 13a, the power of the scaler 1204 is the size It is possible to scale the amplitude of the input signal vector whose value varies to the shaded area shown in the figure. It is necessary. The coarse phase accumulator 1206 stores the coarse phase angle φ1 of the signal vector. , reverse pressure cutting generation stage 1212 The output of is equal to the fine phase φf of the signal vector, as shown in FIG. 13b. this The signal vector φf is transformed into a range of −π/4≦φf≦1π/4 (first 3b). Generated by the output of digital adder 1214 The sum of these two quantities produced gives the total phase angle φ(n) of the input signal vector samples. represent. The current phase, shown in FIG. 13C, generated by digital adder 1218 The sample φ(n) and the phase sample φ(n-1 ) represents one sample of the demodulated output message.

A stream of samples representing the demodulated output message is typically followed by a Fl wave. As shown, low-pass filtering can be used to remove noise outside the message band.

It is understood by those skilled in the art that the digital demodulator described in the diagram above is a discrete hardware digital demodulator. It is clear that this can be implemented using multipliers, adders, registers, etc. Let's go. The digital demodulator of the present invention is known as a digital signal processing device. It is suitable for implementation using a class of equipment. The invention is made by Massachusetts NECE, Natick Executive Park 1, Natick, State 01760 NEC07720 available from electronics U, S, A, and Texas Instruments, Texas 752265, Class, Private Box 225012 Various well-known digital signals such as the Ding MS32010 available from Luments, Inc. It can be satisfactorily implemented using a code processing device. Digital signal processing equipment In general, in addition to the hardware high-speed digital multiplier, a predetermined algorithm is used. has the ability to process digital data flows.

Figures 14a and 14b show the present invention in which the groove bottom is formed using a digital signal processing device. 7j is a flowchart showing details of the background processing of FIG. In the detailed description of the invention, in-phase and and the phase-shifted signal vector rotations are hereafter referred to as components I and Q, respectively. I'll decide. The algorithm of the present invention begins at 1402, where the digital The signal processor executes a decision 1404 to determine the sign of the I component. Judgment 1404 Based on the results, the sign of the Q component is determined in decisions 1406 and 1448. Next, ■ The difference between the component and the Q component is calculated from the values of Q-I, I-Q, Q-1, and Q0I, respectively. By item numbers 1410, 1408.1472, and 1450 that generate the numerical value I can't stand it. The sign of each result is determined respectively 1430.1412.1474 , and 1452. Based on the results of these judgments, the larger absolute The component with the value (■ or Q) is known and the signal vector lies in the octant (octant tant, ie, a multiple of π/4) is also known. If this value is less than O , are complemented with item numbers 142o, 1486.1476, and 1462, respectively. . ■The value representing the maximum absolute value of the channel or Q channel is item number 14. 42.1432.1422.1414.1488.1478.1466, or 1454 into the program stack and will be called ffisMAX in the future. Ru. The ¥i amount SMAX is item number 1444.1434.1424.1416. 149Q, 1480.1466, or 1456 to scale subroutine to determine the correct amount of scaling to apply to the input signal vector samples. used for covering. The scale subroutine generates a properly scaled signal base. Return the 1-herel component ■ and Q.

Next, fill in the octant of the signal vector, and the coarse phase value is the term 11446.1. 436.1426.1418.1492.1482.1468 or 1460 is stored in a temporary storage location.

This value is always a multiple of π/2 radians over the range -π≦φ(C)≦π.

Next, the signal vectors have item numbers 144.0, 1428.1492.1484. 1470. Or the negative of the coarse phase value saved by 1460 (only the city is geometric is rotated to The resulting scaled and rotated signal components are henceforth referred to as I ' and Q' signal vector components. The effect of this vector rotation is the signal vector The rotated signal vector components Bi and Q' are located in the range of -π/4≦Of≦π/4. The rotation is to produce a complex vector with a phase angle.

Figures 15a and 15b are the scale subs described in connection with Figure 14a above. It is a flowchart of routine operation.

The scale subroutine 1500 examines the value of SMAX and constructs a signal vector. Find the correct scaling to add to minutes I and Q. How this subroutine works depends on the resolution or number of bits used to represent the signal vector components. . The operation of the scale subroutine requires a length of 32 pixels to represent the signal vector components. A case will be explained in which words l~ are used. Scale at 1502 ・When entering the subroutine, the most significant word (MSW) of number = s MA It is compared with O by 1504. If M S W of S M A X is greater than O For example, discard the lowest word (IsW) of SMAX and set MSW according to item number 1506. and then compare it with the scaling threshold. MSW of S M A X is equal to O If you know, discard MSW and set LSW to the scaling threshold in item number 1528. Compare with. The results of the comparisons generated from item numbers 1506 and 1528, respectively, are Tested against O by 1' section 1508 and 1530, respectively, and the results were ○. If the signal vector components are found to be large, no scaling of the signal vector components is necessary; The routine passes through item number 1550 and the routine executes subroutine 1500f: Activate. It comes out at a certain point. Words held by SMAX (i.e. MSW or LS If W) is less than the threshold, then the word is judged 1510. and 1 532 tests to see if its absolute value is greater than 255. This is SM This is equivalent to checking whether the upper 8 bits of the AX retention word are 0 or more. . If the result of this test is true (i.e., MSW or LSW of SMAX (greater than 255), the retained words will be 1514 or 1536, respectively. It is divided by 256. This transfers the upper 8 bits of the SMAX retention word to this word. This has the effect of shifting to the lower 8 bits of the code.

The result of decision 1510 or 1532 indicates that the retained word is less than 255. In this case, no division is performed. This quantity is now the value stored in the ROM data table. 1516.1512.1538 or 1534 Used as address offset, scaling factor is item number 1520.154 0 is retrieved from the ROM. This coefficient is the previous decision 1510 or 1532 is adjusted to the correct value needed to scale this signal vector component. . Finally, the signal vector components are item numbers 1522 and 1524, or 1542 and 154. 6 to the correct range for use in the approximation applied inside the demodulator. The routine returns as soon as it is called through item number 1526 or 1548. .

Next, with reference to FIG. 16a, find the reciprocal of the vector component. This process 1 This is done by applying a sixth-order Chebyshev polynomial approximation to the number f(X)=1/x.

The polynomial that approximates this function is as follows.

f (X) = (1/X) ~ ([[[[C7(X-1)・C6] (x-1)+C5](x-1)4C4] (x-1)+C3] (X-1)+C2] (X-1)→C1) However, Yes, ci=+1. ooooo, C2=-1,0027, C3=+1.0 0278°C4=-0,91392, C5=+0.91392. C6=-1, 62475° According to the principle of the present invention, the Q' component is programmed by item number 1604. It is pushed into the stack storage area, and the number (I'-1) is calculated by item number 1606. However, this quantity will be referred to as several sets ARG from now on. Coefficient C7 is data RO in item number 1608. It is taken out from M, and ARG and multiplication are combined in item number 1610 to create the quantity lower MP.

The number of layers C6 is fetched from the data ROM in item number 1612, and the number of layers C6 is fetched from the data ROM in item number 1614. P is added to yield a new value of TMP. This pattern is item number 1616 to 1 644, the Q' component is retrieved from the program stack storage at item number 1648. Then, in item number 1650, TMP and multiplication are combined to obtain the quantity tanφf=Q'/I ’ is repeated sequentially until it yields an approximation to ’.

Now install the reverse pressure cut of the number 111 in item number 1650.

This process is a function This is done by performing a fifth-order Chebyshev polynomial approximation for .

The polynomial that approximates this function is:

↑an’(x)～ x ([[[C6 (y) ten C5]y ten c4]y+C3]y→C21y→C1)C 6=-0,01343, C5-→0.05737. C4-0,12109°C 3-÷0.19556. C2=-0,33301, C1-+0.99997 number The maximum The value of the square Hy=x− will be referred to as ARG/S’; calculated. A chain method similar to the calculation of the reciprocal value explained earlier is used to calculate the number m (Q' Calculate the reverse pressure cut of /I') using item numbers 1656 to 1692. This place The result of the calculation is the phase angle of the rotated signal vector or the input signal vector → non-pull It is a signed value representing the phase angle of . Coarse phase of input signal vector samples The value of is retrieved from the temporary storage location by item number 1694 and is retrieved from the temporary storage location by item number 1696. It is added to the result of the reverse pressure cutting line.

This result represents the phase angle of the input signal vector samples. Previous input signal vector The phase angle φ, −1 of the sample is called from the program stack by the term @1700. Served.

The phase samples of the annulus are pushed onto the program stack in term @1702. last , the difference between the previous phase sample and the current phase sample is calculated in item number 1704; Produces output samples of the demodulated message m(n).

Message sample m(n) is provided in the form of a sample of the demodulated audio signal. . The demodulated audio signal is converted back to analog form as shown above, and then amplified and amplified. It can be regenerated through a container. Instead, digital voice messages can be used later. The data may be stored digitally in digital memory 123 for use.

In a data communications system (not shown), the demodulated data symbols are coded for further processing. or to a computer terminal for immediate display. Ru.

To summarize, I wrote about the number of digital radio receptions.

The digital reception/Z-loss of the present invention is pre-selected by the output of the antenna and then digitally selected. We are considering the total number of digital radio receivers that operate on received signals that are converted to digital form.

The reception method of the present invention includes a preselector, a high-speed analog-to-digital (A/D) converter, Digital configuration intermediate frequency (IF) selection with substantially baseband frequency output a general-purpose digital signal processing device (DS) that performs demodulation and audio filtering. P> is provided. Other uses and modifications of this invention will occur to those skilled in the art, as well as the spirit of the invention. and will be clear without departing from the scope.

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Claims (12)

[Claims] 1. Virtually convert wideband analog signals, including the required narrowband analog signals, into digital an apparatus for processing a narrowband analog signal, the apparatus comprising: and filter means for receiving and filtering the broadband analog signal; (b) coupled to said filter means for periodically sampling said broadband analog signal; digitizing means for converting the sample into a broadband digital signal; (c) coupled to said digitizing means to generate the desired sample narrowband digital signal; digital means for selecting from a sample broadband digital signal; (d) digital processing means for demodulating the sampled narrowband digital signal; The device characterized in that it comprises: 2. The digital means include digital oscillator means and a digital multiplier/mixer. and digital narrowband filter means. equipment. 3. Virtually digitalizes a wideband analog signal containing the desired narrowband analog signal. (a) includes the required narrowband analog signal; (b) receiving and filtering a wideband analog signal; Periodically sampling a signal and converting it into a sampled wideband digital signal and (c) converting the desired sampled narrowband digital signal into a sampled wideband digital signal. (d) demodulating the sampled narrowband digital signal; step, The method, characterized in that it comprises: 4. The selecting step further includes a step of generating a digital local oscillator signal. The digital local oscillator signal is multiplied by a sampled wideband digital signal. The steps of creating a sample product signal and digitally narrowband filtering the sample product signal to provide support. and generating a sample narrowband digital signal. Method described. 5. Digitally converts a wideband radio frequency (RF) signal containing the desired narrowband signal. A substantially digital device that processes (a) an antenna hand for receiving a (RF) signal comprising said broadband (RF) signal; (b) coupled to said antenna means to provide said broadband (RF) antenna; filter means for filtering the signal; (c) coupled to said filter means to periodically sample said broadband RF signal; , digitizing means for converting the sample into a broadband digital signal; (d) in combination with said digitizing means, a desired sample narrowband digital signal; digital means for selecting a sample from the broadband digital signal; (e) digital processing means for demodulating the sampled narrowband digital signal; A substantially digital device comprising: 6. The digital means include a digital quadrature oscillator, a digital quadrature multiplier/mixer, and a digital quadrature narrowband low-pass filter. Substantially digital device as described. 7. Virtually disables wideband radio frequency (RF) signals containing the desired narrowband signals. A digital processing method, (a) receiving an (RF) signal including the broadband RF signal; (b) filtering the broadband RF signal; and (c) filtering the broadband RF signal. ) is a step that periodically samples a signal and converts it into a sampled wideband digital signal. (d) converting the desired sampled narrowband digital signal into the sampled wideband digital signal; (e) selecting from the sample narrowband digital signal; a step of digitally demodulating; The method, characterized in that it comprises: 8. The selecting step further includes a step of generating a digital local oscillator signal. The digital local oscillator signal is multiplied by a sampled wideband digital signal. The steps of creating a sample product signal and digitally narrowband filtering the sample product signal to provide support. and generating a sample narrowband digital signal. Method described. 9. A method for digitally demodulating a received angularly modulated signal, the method comprising: (a) A digit showing the composite signal vector of a signal centered at approximately zero frequency. inputting the rectangularized samples; (b) scaling the sample to a required size within a predetermined range; (c) there is a scaled composite signal vector with coarse phase range values; calculating the nearest octant; (d) Rotately scale the scaled composite signal vector to −π/4 and +π/4. a step of making the range fall between; (e) Compute a second value equal to the exact phase of the rotationally scaled signal vector. step and (f) Equivalent to the phase angle of the signal vector by finding the inverse right intercept of the second value; calculating a third value including a new fine phase angle value; (g) Adding the values of fine phase angle and coarse phase angle equals the phase angle of the input signal vector creating a composite phase angle sample; (h) filtering a series of phase angle samples to produce a series of demodulated message samples; step and (i) outputting the demodulated message samples to an output register; A demodulation method characterized by comprising: 10. A digital demodulator device with improved linearity, comprising: (a) Enter a sample input vector containing a quadrature signal centered at approximately zero frequency. (b) means for quantizing the input sample quadrature signal within a predetermined range; scaler means, (c) a phase controller that generates the current coarse phase value related to the input vector of the quadrature FM signal; (d) accumulating said input vector in the range between -π/4 and +π/4; (e) a vector rotation means for rotating to a quadrant within the enclosure; and (e) the rotation input signal vector. means for determining a fine phase value based on; (f) adding means for adding the fine and coarse phase values and outputting a composite phase value; (g) filtering a series of phase angle samples to create a series of demodulated message samples; A digital demodulator device comprising filter means. 11. A method for digitally demodulating a received FM signal, the method comprising: (a) Digitized composite signal vector of signals centered at approximately zero frequency inputting a right-angle sample indicating the torque; (b) scaling the sample to the required size within a predetermined range; (c) A scaled composite signal vector exists, with coarse phase range values. , calculating the nearest octant; (d) Put the scaled composite signal vector into the range between −π/4 and +π/4. a step of rotating and scaling the (e) Compute a second value equal to the exact phase of the rotationally scaled signal vector. step and (f) Equivalent to the phase angle of the signal vector by finding the inverse right intercept of the second value; calculating a third value including a new fine phase angle value; (g) Adding the fine phase angle value and the coarse phase angle value equals the phase angle of the input signal vector creating a composite phase angle sample; (h) subtract the value of the previous composite phase angle sample from the current composite phase angle sample; a step of creating a tone message sample; (i) outputting the demodulated message samples to an output register; A digital demodulation method comprising: 12. A digital FM demodulator device with improved linearity, comprising: (a) A sample containing a quadrature FM digital signal centered at approximately zero frequency. (b) means for inputting said input sample quadrature signal to a predetermined input vector; scaler means for quantizing within the range of; (c) a phase controller that generates the current coarse phase value related to the input vector of the quadrature FM signal; (d) accumulating said input vector in the range between -π/4 and +π/4; (e) vector rotation means for rotating into an enclosed quadrant; and (e) said rotational input signal vector. means for determining the fine phase value based on; (f) adding means for adding the fine and coarse phase values and outputting a composite phase value; (g) Subtract the value of the previous composite phase angle sample from the current composite phase angle sample, and filter means for creating tone message samples; A digital FM demodulator comprising: