JPH0730499A - Digital quardature detection device - Google Patents

Abstract

PURPOSE:To obtain a digital quadrature detection device having a highly accurate orthogonality and capable of obtaining I and Q components having a large signal to quantization noise power rate without using an A/D converter for many quantized bits. CONSTITUTION:An IF signals is over-sampled by sampling frequency more than four times of IF frequency fIF and four times of IF signal band width and quantized by the number of quantization bits smaller than the word length of required I and Q components through an A/D conversion means 4. Only a frequency component of f>0 is extracted by a narrow band complex coefficient band pass digital filter 5 to reduce the sampling frequency up to the signal band width or the like. Consequently quantized noise is reduced and the amplitude resolution of a digital signal can be maintained by extending the word lengths of the real part and imarginary part of an output signal outputted from the filter 5. A complex sine wave signal is multiplied in accordance with the center frequency of the output signal. The real part of the signal is the required in-phase component and its imargenary part is the orthogonal component.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital quadrature detector which receives a modulated signal and obtains its in-phase component (I component) and quadrature component (Q component) by digital signal processing.

[0002]

2. Description of the Related Art FIG. 8 shows, for example, PJvan Gerwin, NA.
Papers by M. Verhoeckx, HAvan Essen, FAM Snijders "
Microprocessor Implementation of High-Speed DataMo
dems "IEEE Transactions on Communications, vol.COM-2
5 is a block diagram showing a configuration of a digital quadrature detection device disclosed in “No. 2, pp. 238-250, february 1977” and “Application of Digital Signal Processing” edited by Institute of Electronics, Information and Communication Engineers.

This digital quadrature detector uses RF (R
narrow band modulation signal r
The mixer 1 has a mixer 1 for mixing (t) with a sine wave signal cos (2π (fc −f _IF ) t). The mixer 1 has an IF (Intermediadi) with a band-limited center frequency f _0.
An analog band pass filter 2 for converting into an at frequency signal (x) t is connected. And
The analog bandpass filter 2 is connected to a sampler 8 that samples the analog bandpass signal that has passed through the analog bandpass filter 2 at a predetermined sampling frequency and converts it into a discrete time signal. A / D converter 9 for converting a digital signal into a digital signal
Are connected.

Further, the A / D converter 9 is connected with a complex coefficient band pass digital filter 10 which inputs the output x (mT) of the A / D converter 9 and generates an analytic signal x _A (mT). The complex coefficient bandpass digital filter 1
At 0, the complex sine wave signal exp is added to the analytic signal x _A (mT).
A multiplier 7 for multiplying [-j2πf _IF mT] is connected. The multiplier 7 is connected to a decimator 15 that extracts the output signal of the multiplier 7 at every sample number according to the degree of reduction of the sampling frequency.

Next, the operation will be described.

At the received carrier frequency fc, the bandwidth B (B
RF (Radio Frequency) of << fc)
The narrow band modulation signal r (t) is mixed with the sine wave signal cos (2π (fc −f _IF ) t) by the mixer 1 and the center frequency f band-limited by the analog band pass filter 2 is obtained.
₀ IF (Intermediate Frequency)
y) converted to signal (x) t. Note that f ₀ and f _IF may be different. The IF signal (x) t is converted into a digital signal by the sampler 8 and the A / D converter 9 and becomes x (mT).

If the desired I component / Q component word length determined from the allowable quantization noise power of the I component / Q component is b ₃ bits, the number of quantization bits in the A / D converter 9 becomes the same. However, this b ₃ is not a value with a margin in order to reduce the influence of the rounding noise power due to the filtering following the A / D converter 9. When a margin is to be provided, c = 1 to 4, the word lengths of the I and Q components are (b ₃ + c) bits, and the number of quantization bits in the A / D converter 9 is b ₃ . The sampling frequency fsc, which is the reciprocal of the sampling period T, needs to satisfy the expression (1).

Fsc ≧ 2f ₀ + B (1) The band pass signal x (mT) can be generally expressed as in Expression (2).

X (mT) = a (mT) cos {2πf _IF mT + φ (mT)} = a (mT) cosφ (mT) cos (2πf _IF mT) −a (mT) sinφ (mT) sin (2πf _IF mT ) (2) where a (mT) is the envelope and φ (mT) is the phase. Also, I component I (mT) and Q component Q of x (mT)
(MT) is expressed as follows: I (mT) = a (mT) cosφ (mT) (3) Q (mT) = a (mT) sinφ (mT) (4)

A method of generating I (mT) and Q component Q (mT) from x (mT) will be described below.

The Hilbert transform of x (mT) is x _H (m
T), a complex signal x _A (mT) having x (mT) as a real part and x _H (mT) as an imaginary part is called an analytic signal.

X _A (mT) = x (mT) + jx _H (mT) (5) When the Fourier transform of x (mT) is X (f), the Fourier transform of the analytic signal x _A (mT) X _A ( f) is the following equation (6)
become that way.

[0013]

[Equation 1] That is, the spectrum at 0 <f / fsc <0.5 is twice that of x (mT), and the spectrum at −0.5 <f / fsc <0 is 0.

For such an analytic signal x _A (mT), a low-pass signal y (m
T) is defined.

Y (mT) = x _A (mT) exp [−j2πf _IF mT] = α (mT) + jβ (mT) (7) where α (mT) and β (mT) are real values. . In this case, there is at x (mT) = Re [y (mT) exp [j2πf IF mT]] = α (mT) co s (2πf IF mT) -β (mT) sin (2πf IF mT) ... (8) . Here, Re [•] means an operation that takes the real part of a complex number.

From equations (2) to (4) and equation (8), α (m
It can be seen that T) and β (mT) are the I component and the Q component of x (mT), respectively. That is, the bandpass signal x (m
When the complex sine wave signal exp [−j2πf _IF mT] is applied to the analytic signal x _A (mT) corresponding to T), it is shown that the real part is the I component and the imaginary part is the Q component. In FIG. 8, the analytic signal x _A (mT) is generated by the complex coefficient bandpass digital filter 10 having x (mT) as an input. Therefore, the frequency characteristic of the complex coefficient bandpass digital filter 10 is 0 <f / fsc <0.5, and the other regions are stopbands. The output signal y (mT) obtained by multiplying the output signal x _A (mT) of the complex coefficient band pass digital filter 10 by the complex sine wave signal exp [−j2πf _IF mT] in the multiplier 7 is y (mT) = I (mT) + jQ (mT) (9) Since the bandwidth of y (mT) is generally narrower than the sampling frequency fsc, the decimator 15 takes out a signal every several samples, and the sampling frequency fsc.
It may be lowered to a smaller fs'. In FIG. 8, 1 / T '=
fsc '. However, fsc 'is about the same as or slightly larger than the bandwidth of y (mT). The real part and the imaginary part of the output of the decimator 15 are the I component (I (nT ')) and the Q component (Q (nT
´)).

The advantage of performing quadrature detection by digital signal processing as described above is that, unlike analog processing, the quadrature component of the I component and Q component can be maintained high, and the A / D converter has one advantage.
This is because there are only a few parts and there are few adjustment points for gain and phase. As a technique similar to the above-mentioned conventional example, Japanese Patent Laid-Open No. 64-5
7185 and Japanese Patent Laid-Open No. 1-300611.

[0018]

The conventional digital quadrature detector is constructed as described above and has the above-mentioned advantages, but the orthogonality between the obtained I component and Q component and the digital signal are obtained. The quantization noise power that cannot be avoided by processing depends on the number of quantization bits in the A / D converter and the exchange accuracy. In order to improve the orthogonality between the I component and the Q component and increase the signal-to-quantization noise power ratio, an A / D converter with high precision and a large number of quantization bits may be used. Increase the number of quantization bits in the
There are some problems in increasing the conversion accuracy as follows.

By changing the number of quantization bits to A / D
The hardware scale of the converter is increased, and the cost is increased. Further, extremely high-precision processing technology is required in the manufacture of integrated circuits, which makes it difficult to manufacture a high-precision A / D converter. Before performing A / D conversion, an analog pre-filter is required to prevent aliasing due to sampling, but if the Nyquist frequency at the upper limit of the signal band is close,
A high order filter is required. The number of amplifying elements in the high-order active filter also increases, and noise and distortion generated in the amplifier cannot be ignored. As a result, there is a problem that the signal-to-noise power ratio is reduced. Also,
When the sampling frequency is reduced by the decimator 15,
Although aliasing due to the received signal does not occur, there is a problem that the signal-to-noise ratio is further deteriorated because aliasing occurs due to quantization noise and rounding noise.

The present invention has been made in order to solve the above problems, and has high precision orthogonality and signal-to-quantity without using an A / D converter having a large number of quantization bits. An object of the present invention is to obtain a digital quadrature detection device which can obtain an I component and a Q component having a large digitized noise power ratio.

[0021]

According to a first aspect of the present invention, there is provided a digital quadrature detection device which receives a received IF frequency f _IF.
Sampling means for sampling the analog band-pass signal at a predetermined sampling frequency to convert it into a discrete time signal, and quantizing the discrete time signal with a predetermined number of quantization bits shorter than the word length of the desired in-phase component and quadrature component. A /
D conversion means, band pass type band limiting / sampling frequency reducing means for performing band pass type band limiting on the output signal of the A / D converting means and reducing sampling frequency, and the band pass type band limiting / sampling frequency The band-pass type band limiting / sampling frequency reducing means comprises an multiplying means for multiplying the output signal of the reducing means by a complex sine wave signal of a predetermined frequency, and the band-pass type band limiting / sampling frequency reducing means, with respect to the sampling frequency _fs1 of the input signal 0 <f / f _s1 <0.
5 has a band-pass characteristic of passing only a predetermined frequency component of 5, and extends the word length of the output signal of the band-pass type band limiting / sampling frequency reducing means from the tone of the input signal. .

According to a second aspect of the present invention, there is provided a digital quadrature detection device, wherein sampling means is provided for sampling the received analog band pass signal of the IF frequency f _{IF at} a predetermined sampling frequency and converting it into a discrete time signal, and a desired in-phase signal. A / D conversion means for quantizing the discrete-time signal with a predetermined number of quantization bits shorter than the word length of the component and the orthogonal component, and band-pass type band limitation for the output signal of the A / D conversion means, and Low-pass type band limiting / sampling frequency reducing means for reducing the sampling frequency, and a band for performing band-pass band limiting on the output signal of the low-pass type band limiting / sampling frequency reducing means and reducing the sampling frequency. Pass type band limiting / sampling frequency reducing means and output of the band pass type band limiting / sampling frequency reducing means No. and a complex sine wave signal of a predetermined frequency are multiplied, and the low-pass type band limiting / sampling frequency reducing means has a low-pass characteristic of a predetermined cut-off frequency, and its output signal The word length is extended from the word length of the input signal, and the band pass band limiting / sampling frequency reducing means _sets 0 <f / f _s2 <0.5 of the input signal to the sampling frequency f _s2 of the input signal.
Of the band-pass type band limiting / sampling frequency reducing means, the word length of the output signal is expanded from the tone of the input signal.

A digital quadrature detector according to the present invention comprises sampling means for sampling the received analog band pass signal of the IF frequency f _{IF at} a predetermined sampling frequency f _s1 and converting it into a discrete time signal. A / D conversion means for quantizing the discrete-time signal with a predetermined number of quantization bits shorter than the word lengths of the in-phase component and the quadrature component, and a band-pass band for the output signal of the A / D conversion means. Band-pass type band limiting / sampling frequency reducing means for limiting and reducing the sampling frequency, wherein the IF frequency f _IF is an integer multiple of 1 or more of the sampling frequency f _s3 of the desired in-phase component and quadrature component, and sampling frequency f _s1 of the sampling means for converting the discrete-time signal by sampling the analog bandpass signal, the a Greater than a value obtained by adding the bandwidth of the analog bandpass signal to twice the central frequency of the log bandpass signal, the bandpass band limited sampling frequency reduction means, the sampling frequency f _s1 of the input signal, The input signal has a band-pass characteristic of passing only a predetermined frequency component of 0 <f / _fs1 <0.5, and the word length of the output signal of the band-pass type band limiting / sampling frequency reducing means is It is characterized by expanding from the tone.

The digital quadrature detection apparatus according to the present invention comprises sampling means for sampling the received analog band pass signal of IF frequency f _{IF at} a predetermined sampling frequency f _s1 and converting it into a discrete time signal, Of A / D conversion means for quantizing the discrete-time signal with a predetermined number of quantization bits shorter than the word lengths of the in-phase component and the quadrature component, and a low-pass type for the output signal of the A / D conversion means. Low-pass type band limiting / sampling frequency reducing means for performing band limiting and reducing the sampling frequency, and band-pass type band limiting for an output signal of the low-pass type band limiting / sampling frequency reducing means, and and a band-pass band-limiting sampling frequency reduction means for reducing the sampling frequency, the IF frequency f _IF is desired phase component and linear 1 or more integer multiples and the sampling frequency f _s1 of the sampling means for converting the analog bandpass signal sampling and discrete-time signals, the sampling frequency of the desired phase and quadrature components of the components of the sampling frequency f _s3 is a non-prime integer multiple of f _s3 , and the sampling frequency f _s1 is greater than twice the center frequency of the analog band pass signal plus the bandwidth of the analog band pass signal, and the low pass band limiting / sampling is performed. The frequency reducing means _sets the sampling frequency f _s2 of the input signal to 0 <
It has a band-pass characteristic of passing only a predetermined frequency component of f / f _s2 <0.5, and extends the word length of the output signal of the low-pass band limiting / sampling frequency reducing means from the tone of the input signal. It is characterized by that.

According to a fifth aspect of the present invention, there is provided a digital quadrature detector which has a bandwidth corresponding to the degree of reduction of the sampling frequency or the bandwidth of the input signal of the required band pass type band limiting / sampling frequency reducing means. A band in which the center frequency of the pass band limiting / sampling frequency reducing means is equal to the center frequency or IF frequency f _{IF of the} input signal and the pass band exists in a predetermined range between 0 and 1/2 of the sampling frequency of the input signal. The band pass band limiting / sampling frequency reducing means is configured by connecting in series a pass digital filter and decimation means for extracting the output signal of the band pass digital filter at every sample number according to the degree of reduction of the sampling frequency. The word length of the output signal of the bandpass digital filter is the input It is characterized in that is extended from the word length of the item.

According to a sixth aspect of the present invention, there is provided a digital quadrature detection device, wherein a low pass digital filter having a cutoff frequency corresponding to the degree of reduction of the sampling frequency and an output signal of the low pass digital filter are reduced in the sampling frequency. And a decimation means for taking out every number of samples according to the frequency, are connected in series to constitute the low-pass type band limiting / sampling frequency reducing means, and the word length of the output signal of the low-pass digital filter is input to the input. It is characterized by being extended from the word length of the signal.

According to a seventh aspect of the present invention, there is provided a digital quadrature detection apparatus which comprises a bandpass digital filter having a predetermined bandwidth and a center frequency, and a decimation for extracting every predetermined number of samples connected in series to the bandpass digital filter. And a plurality of sets are connected in series to constitute the band pass type band limiting / sampling frequency reducing means, and the word lengths of the output signals of the plurality of band pass digital filters are expanded from the word lengths of the input signals. It is characterized by that.

A digital quadrature detector according to the present invention comprises a low-pass digital filter having a predetermined bandwidth, and decimation means connected in series to the band-pass digital filter to take out every predetermined number of samples. By connecting a plurality of sets in series, the low-pass band limiting
The sampling frequency reducing means is constituted, and the word length of the output signal of the plurality of low-pass digital filters is extended from the word length of the input signal.

According to a ninth aspect of the present invention, in the digital quadrature detector, the band pass type band limiting / sampling frequency reducing means and the band pass type band limiting / sampling frequency reducing means set the sampling frequency to an integer (D) of the input signal. ₂ ) A switch that distributes the input signal for each sample to an integer (D ₂ ) path when it is reduced to the reciprocal (1 / D ₂ ) and a plurality of switches connected to the integer (D ₂ ) path, respectively. (D ₂₎ and the number of digital filters, a plurality (D ₂₎ pieces of summing the output signal of the digital filter is composed of an adding unit, a plurality (D ₂₎ pieces of output of the output signal or said adding means of the digital filter It is characterized in that the word length of the signal is extended from the word length of the input signal of the band pass type band limiting / sampling frequency reducing means.

According to a tenth aspect of the present invention, in the digital quadrature detection device, the low pass band limiting / sampling frequency reducing means, and the low pass band limiting / sampling frequency reducing means set the sampling frequency to an integer of the input signal. They are respectively connected to the input signal and a switch for distributing the passage integer (D ₁₎ present in each sample, an integer (D ₁₎ to the passageway when attempting to reduce the reciprocal ₍₁ / D 1) of (D ₁₎ a plurality (D ₁₎ pieces of digital filters, a plurality (D ₁₎ pieces of summing the output signal of the digital filter is composed of an adding unit, a plurality (D ₁₎ number of output signals or said adding means of the digital filter The word length of the output signal of is extended from the word length of the input signal of the low pass band limiting / sampling frequency reducing means.

In the digital quadrature detector according to the present invention, the low-pass type band limiting / sampling frequency reducing means has a low-pass digital filter and a low-pass filter having a cutoff frequency according to the degree of reduction of the sampling frequency. The output signal of the band-pass digital filter is connected in series with decimation means for extracting the output signal at every sample number according to the degree of reduction of the sampling frequency, and is connected in series with the low-pass digital filter and the band-pass digital filter with a predetermined bandwidth. A plurality of decimation means for extracting every predetermined number of samples are connected in series,
Alternatively a low-pass band-limiting sampling frequency reduction means integral of the input signal sampling frequency (D ₁₎ of the reciprocals integer input signals for each sample when the ₍₁ / D 1) to attempt to reduce the (D ₁₎ A switch for allocating to a plurality of channels, a plurality (D ₁ ) of digital filters respectively connected to the integer (D ₁ ) channels, and an addition means for adding output signals of the plurality of (D ₁ ) digital filters. In addition, the band pass type band limiting / sampling frequency reducing means has a bandwidth corresponding to the degree of reduction of the sampling frequency or the bandwidth of the input signal of the required band pass type band limiting / sampling frequency reducing means, and the band pass type band or equal and passband center frequency as the center frequency or iF frequency f _iF of the input signal of the limiting sampling frequency reduction means 0 A band pass digital filter existing in a predetermined range between 1/2 of the sampling frequency of the input signal and a decimation means for taking out the output signal of the band pass digital filter at every sample number according to the degree of reduction of the sampling frequency are connected in series. A bandpass digital filter having a predetermined bandwidth and a center frequency, and a plurality of decimation means connected in series to the bandpass digital filter for extracting a predetermined number of samples and connected in series, or a bandpass type When the band limiting / sampling frequency reducing means attempts to reduce the sampling frequency to the reciprocal (1 / D ₂ ) of the integer (D ₂ ) of the input signal, the input signal is divided into integer (D ₂ ) paths for each sample. Switch, integer (D ₂ )
It is characterized by comprising a plurality of (D ₂ ) digital filters and an addition means for adding output signals of the plurality of (D ₂ ) digital filters, which are respectively connected to the passages of the book.

[0032]

In the digital quadrature detector according to the first and fifth aspects of the present invention, the IF signal is the IF frequency f _IF of 4
Doubled and oversampled at a sampling frequency of 4 times the bandwidth of the IF signal or more, and the desired I
Quantization is performed with a quantization bit number smaller than the word length (bit number) of the component and the Q component. The oversampled signal is f> by a narrow band complex coefficient bandpass digital filter whose passband is only the signal band of frequency f> 0.
Only the frequency component of 0 is extracted, and the sampling frequency is reduced to the signal bandwidth. This reduces the quantization noise and makes the amplitude resolution of the digital signal by making the word lengths of the real and imaginary parts of the complex coefficient bandpass digital filter output signal longer than that of the complex coefficient bandpass digital filter input signal. maintain. Although the frequency component of the sampling frequency f _IF moves after the sampling frequency is reduced, if the frequency f _b corresponding to f _IF in the baseband is not 0, it is multiplied by a complex sinusoidal signal of an appropriate frequency to correspond to f _b . The frequency component to be moved is moved to 0. The real part of the signal thus obtained is the desired I component, and the imaginary part is the Q component.

In the digital quadrature detection device according to the present invention as defined in claims 2, 5, and 6, the IF signal is converted into an IF signal.
Oversampling at a sampling frequency that is 8 times the frequency f _IF and 8 times or more the bandwidth of the IF signal, and the number of quantization bits that is smaller than the desired I component and Q component word length (bit number) by the A / D conversion means. Quantize with. In order to reduce the amount of signal processing calculation and the amount of hardware in the subsequent complex coefficient band pass digital filter, the band of the oversampled signal is once limited by the low pass digital filter, and the sampling frequency is appropriately reduced. At this time, the quantization noise is reduced by the low pass digital filter. The low pass digital filter output signal is made longer than that of the input signal to maintain the amplitude resolution of the digital signal. The signal thus obtained is extracted by a narrow band complex coefficient band pass digital filter having a signal band of frequency f> 0 as a pass band, and only the frequency component of f> 0 is extracted, and the sampling frequency is reduced to a signal bandwidth equivalent. To do. This reduces quantization noise and maintains the amplitude resolution of the digital signal by making the word length of the complex coefficient bandpass digital filter output signal longer than that of the complex coefficient bandpass digital filter input signal. The frequency component of f _IF before the sampling frequency reduction moves after the sampling frequency reduction, but if the frequency f _b corresponding to f _IF in the base band is not 0, it is multiplied by a complex sine wave signal of an appropriate frequency to f _b. The frequency component corresponding to is moved to zero. The real part of the signal thus obtained is the desired I component, and the imaginary part is the Q component.

In the digital quadrature detector according to the present invention, the multiplication of the processed received signal and the complex sine wave signal is unnecessary by appropriately selecting the center frequency and sampling frequency of the IF signal. I have to.

In the digital quadrature detector according to the present invention as defined in claims 7 and 8, the sampling frequency is reduced little by little, whereby the transition band width of each band pass digital filter is set wide and each band pass digital filter is set. The order can be kept low and the amount of signal processing calculation can be small. Amplitude resolution is maintained by making the word length of the output signal of each reduction band pass digital filter longer than that of the input signal in accordance with the degree of reduction of the sampling frequency.

In the digital quadrature detector according to the present invention as defined in claims 9 and 10, the input signal is distributed to a plurality of digital filters for each sample for parallel processing, and the outputs thereof are added to limit the band. And the sampling frequency is reduced at the same time. Amplitude resolution is maintained by making the word length of the output signal of the band limiting / sampling frequency reducing means longer than that of the input signal.

[0037]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. First, oversampling A / D in which sampling is performed at a sampling frequency larger than twice the Nyquist frequency, A / D conversion with low resolution (quantization bit number) is performed, and the sampling frequency is reduced after band limitation by a digital filter. The conversion technology will be described. The reason why the oversampling technique is drawing attention is that the A / D is required in order to obtain a high accuracy and a large signal to quantization noise power ratio.
It is difficult to increase the resolution of the converter (increase the number of quantization bits), but it is easier to create an A / D converter with low resolution (low quantization bit number) but high sampling frequency. Is. In addition, since the sampling frequency is considerably higher than the signal band to be converted, the restrictions on the characteristics of the analog filter before sampling are relaxed, and only low-order ones are required. Therefore, it becomes easy to form an integrated circuit.

Next, the principle of oversampling will be briefly described.

A / which performs linear quantization of the quantization step Δ
Consider a D converter. When the quantization noise power N _Q assuming that quantization noise is uniformly distributed between the areas ± Δ / 2, the N _Q = Δ ^2/12. It is known that this is in good agreement with reality when the input signal amplitude is several times larger than the quantization step. Assuming that the quantization noise is white noise, the sampling frequency is f _s , the required band is −f _B ≦ f ≦ f _B , and the other bands are removed by a low-pass digital filter. power N _{Q ^{is, N Q = (Δ 2/}} 12) the _{(2f B / f s) ...} (10). For a sine wave signal, the maximum signal-to-quantization noise power ratio S / N _Q obtained with a b-bit A / D converter is

[Equation 2] Becomes

According to equation (11), if the sampling frequency is made higher than the required band for A / D conversion and then low-pass filtering is performed, the quantization noise power becomes small, and as a result, It can be seen that the resolution increases. For example, quadrupling the sampling frequency improves the signal to quantization noise power ratio by about 6 dB. This corresponds to an increase in resolution by 1 bit. Even if the number of quantization bits is reduced by 1, the same resolution can be obtained by quadrupling the sampling frequency. Thus, a low-quantization bit number but high-speed A / D converter and a low-pass digital filter are used 8, and a low-speed multi-quantization bit number of A / D is used.
The same effect as when using the D converter can be obtained. This utilizes the fact that the quantization noise power in the signal band decreases when the sampling frequency is increased because the quantization noise power does not depend on the sampling frequency.

The above is a multi-bit A / for performing linear quantization.
Although the case where the D converter is used, the equations that give the quantization noise power and the signal-to-quantization noise power ratio are different even in the oversampling A / D converter using ΔΣ modulation.
Even if a bit quantizer is used, the quantization noise level in the signal band becomes extremely low, and therefore the resolution can be increased by oversampling.

In the case of an A / D converter using a second-order ΔΣ modulation and a 1-bit quantizer, the maximum signal-to-quantization noise power ratio S / N _Q for a sine wave signal is

[Equation 3] It is known that Here, _assuming that f _s / 2f _B = 128, the signal-to-quantization noise power ratio S / N _Q is about 94d.
B, the resolution equivalent to 15 bits when oversampling is not performed can be obtained.

Example 1. FIG. 1 shows claims 1 and 5.
It is a block diagram which shows the structure of the digital quadrature detection apparatus which concerns on invention of description.

The digital quadrature detector uses an RF narrow band modulation signal r (t) and a sine wave signal cos (2π (fc-
f _IF ) t) is mixed, and the mixer 1 is connected to an analog band pass filter 2 for converting into an IF signal (x) t having a band-limited center frequency f ₀ . . The analog bandpass filter 2 is connected to a sampler 3 as sampling means for sampling the analog bandpass signal passed through the analog bandpass filter 2 at a predetermined sampling frequency and converting it into a discrete time signal. An A / D converter 4 for converting the discrete time signal from 3 into a digital signal is connected.

Further, the A / D converter 4 receives the output x (kT ₁ ) of the A / D converter 4 and outputs a signal x _C (nT ₃ ) having a band pass type band pass characteristic. The limiting / sampling frequency reducing device 101 is connected, and the band pass type band limiting / sampling frequency reducing device 101 outputs the complex sine wave signal exp to the output signal x _C (nT ₃ ).
A multiplier 7 is connected as a multiplication means for multiplying [-j2πnf _b / f _s3 ]. Then, the band pass type band limiting / sampling frequency reduction device 101 takes out the band pass digital filter 5 and the output signal x _A (kT ₁ ) of the band pass digital filter 5 at every sample number corresponding to the degree of reduction of the sampling frequency. The decimator 6 serves as decimation means.

Next, the operation of this embodiment will be described.

Carrier frequency fc, bandwidth (B << fc)
Of the received RF signal r (t) is mixed with the sine wave signal cos (2π (fc −f _IF ) t) by the mixer 1, and the center frequency f is band-limited by the analog bandpass filter 2.
The IF signal (x) t of ₀ is converted. Note that f ₀ and f _IF
May differ from. Note that (x) t is sampled by the sampler 3 at the sampling frequency f _s . f _s should be at least 4 times the IF frequency and 4 times the bandwidth of (x) t for oversampling.

The A / D converter 4 converts the signal sampled by the sampler 3 into a digital signal. When a multi-bit A / D converter that performs linear quantization is used, the number of quantization bits b ₁ in the A / D converter 4 is a desired I component determined from the allowable quantization noise power of I component / Q component. the number of bits of the Q component b ₃ (> b _1), when the sampling frequency f _s3, the integer value of _{b 3 -log 4 (f s1 /} f s3) or the minimum is a measure. On the contrary, the quantization bit number b ₁ in the A / D converter 4 and the desired I component / Q component bit number b
You may decide f _s1 from ₃ . However, this b ₃ is not a value with a margin in order to reduce the effect of rounding noise. To give a margin, set c = 1 to 4 and
The word lengths of the I and Q components are (b ₃ + c) bits, and the number of quantization bits in the A / D converter 4 is b ₁ as described above.

In selecting f _s1 and f _s3 , f _s1 / f _s3
The value of is preferably an integer value of 2 or more for the sake of simplification of the circuit. Here, description will be given assuming that such selection is made.

In the case of the A / D converter using the second-order ΔΣ modulation / 1-bit quantizer, the sampling frequency f _s1 in the sampler 3 is determined from the desired bit number b ₃ of the I component / Q component and the sampling frequency f _s3. .

[0051]

[Equation 4] The degree is a guideline. As a matter of course, the A / D converter other than the one excited here can be used.

[0052] inputted to the A / D converted band pass digital signal _{x (kT 1) (T 1} = 1 / f s1) bandpass bandlimited sampling frequency reduction device 101. This band pass type band limiting / sampling frequency reducing device 10
1, the center frequency is f ₀ or f _IF , the pass band width is almost the same as or slightly wider than the reception signal bandwidth B, and −0.
5 <f / f _s1 <0 has no passband, and the impulse response is a complex coefficient bandpass digital filter 5 having a complex number,
The decimator 6 is connected in series. In the complex coefficient bandpass digital filter 5, the input signal x
(KT ₁ ) is converted into an analytic signal x _A (kT ₁ ). x
_A (kT ₁ ) has a plurality of values, and a signal having a plurality of values is shown by a thick line in FIG.

Then, the decimator 6 reduces the sampling frequency f _s1 to f _s3 = f _s1 / D. This is an operation of taking the output signal x _A (kT ₁ ) of the complex coefficient band pass digital filter 5 every (D−1). Note that f _s3 is the bandwidth B of x _A (kT ₁ ).
Is about the same as or slightly larger, and D is 2
The above is an appropriate integer.

The complex coefficient band-pass digital filter 5 suppresses the quantization noise outside the signal band and the DC component generated at the time of A / D conversion by setting the pass band to the same level as the bandwidth of the received signal. Then, in the complex coefficient bandpass digital filter 5, a product-sum operation of the signal and the filter coefficient is performed, whereby the signal word length inside the digital filter becomes longer by the filter coefficient word length. This is usually rounded to some word length at the output of the digital filter 5 which is shorter than that. At this time, the word length of the output signal x _A (kT ₁ ) of the complex coefficient band-pass digital filter 5 is b at least as long as the sampling frequency is reduced from the word length of the input signal x (kT ₁ ) of the digital filter 5. Set to ₃ bits. If a margin is provided to reduce the effect of rounding noise, it is increased by several bits. If this is not done, the quantization noise reduction effect of the complex coefficient bandpass digital filter 5 does not appear. On the contrary, even if the sampling frequency is reduced by performing such an operation, aliasing noise due to aliasing does not occur, and therefore, the resolution of the amplitude in the digital signal can be maintained, so that there is a highly accurate orthogonality and the signal-quantum It is possible to obtain the I component and the Q component having a large noise power ratio.

FIG. 2 shows the output signal x of the complex coefficient bandpass digital filter 5 by reducing the sampling frequency.
_A (kT ₁ ) and output signal x _C (nT ₃ ) of the decimator 6
Shows the relationship between the spectrum of _{(T 3 = 1 / f s3} ). Note that FIG. 2 is an example in which the sampling frequency is reduced to 1/4 (D = 4). Where IF frequency and x
The center frequencies f ₀ of _A (kT ₁ ) are assumed to match. The spectrum of the output signal x _A (kT ₁ ) of the complex coefficient bandpass digital filter 5 is drawn by a solid line,
The broken line and the alternate long and short dash line are the spectrum of x _C (nT ₃ ) due to the folding caused by reducing the sampling frequency to ¼, and among these, the one of the alternate long and short dash line in the base band is necessary.

[0056] When in the range of IF frequencies f (K-0.5) for integer K which is _{IF f s3 <f IF <(} K + 0.5) f s3, x A of f _IF of (kT ₁₎ The frequency component moves to f _b in the baseband due to decimation.

F _b = f _IF −Kf _s3 (14) F _{b in the} equation (14) does not always become 0. Therefore, the frequency component of f _b is moved to 0 by multiplying x _C (nT ₃ ) by the complex sine wave signal exp [−j2πnf _b / f _s3 ] by the multiplier 7. The real part of the output signal y (nT ₃ ) of the multiplier 7 is the desired I component I (n
T ₃ ) and the imaginary part is the Q component Q (nT ₃ ).

As described above, by introducing the oversampling technique into the digital quadrature detection processing, the A / D conversion is performed with the quantization bit number lower than the desired I component / Q component signal word length. That is, A / of the multi-quantization bit number
It has high-precision orthogonality without using a D converter,
It is possible to realize a digital quadrature detection device that can obtain an I component and a Q component having a large signal-to-quantization noise power ratio.

Example 2. FIG. 3 is a block diagram showing the configuration of a digital quadrature detection device according to the invention described in claims 2, 5, and 6. It should be noted that the same components as those in FIG.

Reference numeral 102 is a low-pass type band limiting / sampling frequency reducing device, 103 is a band-pass type band limiting / sampling frequency reducing device, and low-pass type band limiting / sampling frequency reducing device 102 is a low-pass type. The bandpass digital filter 11 and the decimator 12 are included, and the bandpass band limiting / sampling frequency reduction device 103 is composed of a complex coefficient bandpass digital filter 13 and a decimator 14. As described above, the purpose of connecting the low-pass band limiting / sampling frequency reducing device 102 and the band-pass band limiting / sampling frequency reducing device 103 in series is to convert an oversampled band-pass signal into an analytic signal. This is to reduce the amount of signal processing calculation in the complex coefficient bandpass digital filter 13 and to simplify the hardware.

Next, the operation of this embodiment will be described.

The assumption that the received RF signal r (t) having the carrier frequency f _c and the bandwidth B is converted into the IF signal x (t) is the same as that in the first embodiment, and therefore its explanation is omitted.

(X) t is sampled by the sampler 3 at the sampling frequency f _s1 . f _s1 is at least 8 times the IF frequency and 8 times the bandwidth of (x) t for oversampling.

The A / D converter 4 converts the signal sampled by the sampler 3 into a digital signal. When a multi-bit A / D converter that performs linear quantization is used, the number of quantization bits b ₁ in the A / D converter 4 is the desired I component
The number of bits of the Q component b ₃ (> b _1), when the sampling frequency f _s3, the integer value of _{b 3 -log 4 (f s1 /} f s3) or the minimum is a measure. Conversely, the A / D converter 4 quantization bits b ₁ to the bit number b ₃ of the desired I component · Q component in may be determined f _s1. However, this b ₃
Is not a value with a margin in order to reduce the effect of rounding noise. When a margin is provided, c = 1 to 4 and the word lengths of the I and Q components are (b ₃ + c) bits, A
The number of quantization bits in the / D converter 4 is b ₁ as described above.
And f _s1 and f _s3 , and in selecting the sampling frequency f _s2 at the output of the decimator 12 described later, f
It is desirable that the values of _s1 / f _s2 and f _s2 / f _s3 be integer values of 2 or more for simplification of the circuit. Hereinafter, these ratios will be described as being integers.

In the case of the A / D converter using the secondary ΔΣ modulation / 1-bit quantizer, the sampling frequency f _s1 in the sampler 3 is determined from the desired bit number b ₃ of the I component / Q component and the sampling frequency f _s3. . The standard is calculated by the above equation (13). As a matter of course, the A / D converter other than the one excited here can be used.

In order to reduce the amount of signal processing calculation in the complex coefficient bandpass digital filter 13 for converting the oversampled bandpass signal into an analytic signal and to simplify the hardware, the output signal of the A / D converter 4 x (kT
₁ ) (T ₁ = 1 / f _s1 ) is once reduced to the sampling frequency f _s2 (= f _s1 / D ₁ ) by the low pass band limiting / sampling frequency reducing device 102. D ₁ is an integer of 2 or more. Hereinafter, the degree of reduction of the sampling frequency such as D ₁ will be referred to as a decimator ratio. The decimator ratio is a value greater than 1.

In the low pass band limiting / sampling frequency reducing device 102, the low pass digital filter 11 is used.
And a decimator 12 are connected in series, and in order to prevent aliasing due to quantization noise, low-pass band limiting is performed by the low-pass digital filter 11.
The decimator 12 reduces the sampling frequency to f _s2 .
This is an operation for taking every (D ₁ -1) output signals of the low-pass digital filter 11. Note that it is necessary to satisfy f _s2 > 2f ₀ + B.

The cut-off frequency f _s1 / 2D _{1 of the} low-pass digital filter 11 is set to be equal to or lower than. The coefficient of the low-pass digital filter 11 is a real number. The delay operator for the sampling frequency f _s1 will be denoted as z1 and the delay operator for the sampling frequency f _s2 will be denoted as z2.

Inside the low-pass digital filter 11, a product-sum operation of the signal and the filter coefficient is performed, whereby the signal word length inside the digital filter becomes longer by the filter coefficient word length. This is usually rounded to a certain word length at the output of the digital filter 11.
At this time, the word length (b ₂ bits) of the output signal of the low-pass digital filter 11 is made longer than the word length (b ₁ bit) of the input signal of the digital filter 11 by the amount obtained by reducing the sampling frequency. That is, the bit rate is not lowered by setting b ₂ ≧ b ₁ + log ₄ D ₁ . By doing so, the resolution of the digital signal amplitude can be maintained even if the sampling frequency is reduced.

Then, the output signal x ₂ (mT ₂ ) of the low pass band limiting / sampling frequency reducing device 102 is
x ₂ (mT ₂ ) A band-pass type band limiter that passes only the band of 0 <f / f _s2 <0.5, converts it into an analytic signal, and lowers the sampling frequency to the same level as the signal band B.
Input to the sampling frequency reduction device 103.

The band pass type band limiting / sampling frequency reducing device 103 in FIG. 3 has a center frequency f ₀ or f
_{At IF} , the passband width is about the same as the signal bandwidth B and -0.5 <
For f / f _s2 <0, a complex coefficient band pass digital filter 13 having no pass band and a decimator are connected in series.

Complex coefficient band pass digital filter 13
, The input signal x ₂ (mT ₂ ) is the analytic signal x _A2
Converted to (mT ₂ ). x _A2 (mT ₂ ) has a plurality of values, and a signal having a plurality of values is indicated by a thick line in FIG.

Then, the decimator 14 reduces the sampling frequency f _s2 to f _s3 = f _s2 / D ₂ . This is a sample of the output signal x _A2 (mT ₂ ) of the complex coefficient band pass digital filter 13 (D ₂ −
1) It is an operation to take every other piece. Note that f _s3 is x _A2 (mT
₂ ) The bandwidth B is approximately the same value, and D ₂ is an appropriate integer of 2 or more.

Complex coefficient band pass digital filter 13
By setting the pass band of the same as the bandwidth of the IF signal, the quantization noise outside the signal band and the DC offset component generated during A / D conversion are suppressed. Then, the word length of the output signal x _C3 (nT ₃ ) of the complex coefficient band pass digital filter 13 is the same as the case of the low pass digital filter 11, and the input signal x ₂ (mT ₂ of the complex coefficient band pass digital filter 13 is ) The sampling frequency is made smaller than the word length to make it longer. That is, the bit rate is not lowered by setting b ₃ ≧ b ₂ + log ₄ D ₁ . By doing so, the resolution of the digital signal amplitude can be maintained even if the sampling frequency is reduced. If a margin is provided to reduce the effect of rounding noise, it is increased by several bits.

Complex coefficient band pass digital filter 13
Output signal x _A2 (mT ₂ ) and the output signal x _C3 (n of the band pass type band limiting / sampling frequency reduction device 103
The relationship of the spectrum of T ₃ ) is the output signal x of the complex coefficient band pass digital filter 13 in the above-mentioned embodiment.
_A (kT ₁ ) and output signal x _C (nT ₃ ) of the decimator 6
Is the same as the relationship.

The frequency component of f _IF of the output signal x _A2 (mT ₂ ) of the complex coefficient band pass digital filter 5 moves to f _b in the base band after decimation. This f _b
Does not always become 0. Therefore, the multiplier 7
_A complex sine wave signal exp [-j2πnf _{b is} added to _C3 (nT ₃ ).
The frequency component of f _b is moved to 0 by multiplying / f _s3 ]. The real part of the output signal y (nT ₃ ) of the multiplier 7 is the desired I component I (nT ₃ ), and the imaginary part is the Q component Q (nT ₃ ).
₃ )

As described above, by introducing the oversampling technique into the digital quadrature detection processing, the A / D conversion is performed with a quantization bit number lower than the desired I component / Q component signal word length. That is, A / of the multi-quantization bit number
It has high-precision orthogonality without using a D converter,
It is possible to realize a digital quadrature detection device that can obtain an I component and a Q component having a large signal-to-quantization noise power ratio. Furthermore, a low-pass type band limiting / sampling frequency reducing device 102
By providing, the sampling frequency can be lowered to some extent in advance at the input of the complex coefficient bandpass digital filter 13. Therefore, the constraint on the characteristic of the complex coefficient bandpass digital filter 13 is looser than that of the conventional example. That is, it does not have to be a narrow transition bandwidth filter. Therefore, the order of the complex coefficient bandpass digital filter 13 is reduced, and the amount of hardware can be reduced. As a result, the amount of signal processing calculation required for filtering in the complex coefficient bandpass digital filter 13 can be reduced. The filtering process in the band pass type band limiting / sampling frequency reducing device 103 handles complex numbers, whereas the filtering process in the low pass type band limiting / sampling frequency reducing device 102 is a real-valued signal process. Even if two band pass type band limiting / sampling frequency reducing means are combined, there is an advantage that the amount of calculation is smaller than in the case of the first embodiment.

Example 3. FIG. 4 is a block diagram showing the configuration of a digital quadrature detection device according to the invention of claim 3. It should be noted that the same components as those in FIG. In this embodiment, the IF frequency f _IF
By appropriately selecting the sampling frequency f _s1 in the sampler 3 and the sampler 3, the complex sine wave signal exp [−j2πnf _b / f _s3 ] is added to the output signal x _C (nT ₃ ) of the band pass type band limiting / sampling frequency reducing device 101. The multiplier 7 for multiplication is omitted.

As shown in FIG. 2, band pass type band limiting
When the output signal x _A (kT ₁ ) of the bandpass digital filter 5 of the sampling frequency reduction device 101 is reduced to the sampling frequency f _s3 (= f _s1 / D), a folded spectrum is generated. The frequency component of f _IF of x _A (kT ₁ ) moves by decimation, but if f _b existing in the base band −f _s3 / 2 ≦ f ≦ f _s3 / 2 is 0, the band pass in FIG. In the multiplier 7 following the band limiting / sampling frequency reducing device 101, x _C (nT ₃ ) and the complex sine wave signal exp [-j
2πnf _b / f _s3 ] is no longer necessary. In this case, the real part of the output signal x _A (nT ₃ ) of the band pass type band limiting / sampling frequency reduction device 101 shown in FIG. 4 is the desired I component I (nT ₃ ), and the imaginary part is the Q component Q (nT _3). )
Becomes The thick line indicates a complex signal.

Next, the condition for the frequency f _b in FIG. 2 to become 0 is determined.

In order that the frequency f _b becomes 0, the equation (1
From 4), the IF frequency f _IF is the output signal x _C (nT ₃ ) of the band pass type band limiting / sampling frequency reducing device 101.
It suffices if it is an integral multiple of the sampling frequency f _s3 of. Further, since the decimation ratio in the band pass type band limiting / sampling frequency reducing device 101 is an integer, the sampling frequency f _s1 in the sampler 3 is the band pass type band limiting / sampling frequency reducing device 10.
It may be an integral multiple of 2 or more of the sampling frequency f _s3 in one output.

That is, the condition that multiplication by the multiplier in FIG. 1 and the complex sine wave signal exp [-j2πnf _b / f _s3 ] is unnecessary is as follows: (1) IF frequency f _IF is the desired I component, Q component _{Must be} an integer multiple of 1 or more of the sampling frequency f _s3 of.

(2) The sampling frequency f _s1 in the sampler 3 is an integer multiple of 2 or more of the desired I component and Q component sampling frequencies f _s3 , and the center frequency f of the IF signal is
₀ , where f _s1 > 2f ₀ + B when the bandwidth is B.

Thus, the IF frequency f _IF and the sampler 3
If the sampling frequency f _s1 in 1 is selected, a multiplier for multiplying the received signal by the complex sine wave signal is not required, and the circuit scale can be reduced, which is advantageous for downsizing.

Example 4. FIG. 5 is a block diagram showing the configuration of a digital quadrature detection device according to the invention of claim 4. The same components as those in FIG. 3 are designated by the same reference numerals and the description thereof will be omitted. In the present embodiment, the output signal x of the band pass type band limiting / sampling frequency reducing device 103 x
_The complex sine wave signal exp [-j2πnf _{b is} added to _C (nT ₃ ).
The multiplier 7 for multiplying / f _s3 ] is omitted.

Appropriately select the center frequency f _{0 of the} IF signal x (t), the sampling frequency f _s1 in the sampler 3, and the sampling frequency f _s2 after being reduced by the low pass band limiting / sampling frequency reducing device 102. Thus, the multiplier 7 can be omitted.

As shown in FIG. 2, band pass type band limiting
When the output signal x _A2 (mT ₂ ) of the complex coefficient band pass digital filter 13 of the sampling frequency reduction device 103 is reduced to the sampling frequency f _s3 (= f _s2 / D ₂ ), a folded spectrum is generated. The frequency component of f _IF of x _A2 (mT ₂ ) moves by decimation, but if f _b existing in the base band −f _s3 / 2 ≦ f ≦ f _s3 / 2 is 0, the band pass in FIG. In the multiplier 7 following the type band limiting / sampling frequency reducing device 103, x _C3 (nT ₃ ) and the complex sine wave signal exp [-j
2πnf _b / f _s3 ] is no longer necessary. In this case, the real part of the output signal x _C3 (nT ₃ ) of the bandpass band limiting / sampling frequency reducing device 103 shown in FIG. 5 is the desired I component I (nT ₃ ), and the imaginary part is the Q component Q (nT _3). ). The thick line indicates a complex signal.

Next, the condition for the frequency f _b in FIG. 2 to become 0 is determined.

In order that the frequency f _b becomes 0, the equation (1
From 4), the IF frequency f _IF is the output signal x _C3 (nT ₃ ) of the band pass type band limiting / sampling frequency reducing device 103.
The sampling frequency f _s3 may be an integer multiple of 1 or more. Further, since the decimation ratio in the low pass band limiting / sampling frequency reducing device 102 and the band pass type band limiting / sampling frequency reducing device 103 is an integer, the low pass type band limiting / sampling frequency reducing device 102 has a decimation ratio. The sampling frequency f _{s2 at} the output is an integer multiple of 2 or more of the sampling frequency f _s3 at the output of the band pass band limiting / sampling frequency reducing device 103, and the sampling frequency f _{s1 at the} sampler 3 is the low pass band limiting / sampling frequency. The sampling frequency f _{s2 at} the output of the reduction device 102
2 may be an integer multiple of 2 or more.

That is, in the multiplier of FIG. 3, the output signal x _C3 (nT ₃ ) of the band pass type band limiting / sampling frequency reducing device 103 and the complex sine wave signal exp [-j2π].
nf _b / f _s3 ] is not necessary. (1) The IF frequency f _IF is an integer multiple of 3 or more of the desired I component and Q component sampling frequencies f _s3 .

(2) When the sampling frequency f _s1 in the sampler 3 is an integer multiple which is not a prime number of the desired I component and Q component sampling frequency f _s3 , and the center frequency f ₀ of the IF signal and the bandwidth are B That is, f _s1 > 2f ₀ + B.

Thus, the IF frequency f _IF and the sampler 3
If the sampling frequency f _s1 in is selected, the multiplier for multiplying the received signal by the complex sine wave signal is not required, and the signal processing can be performed at higher speed. Also,
Since the means for multiplying the received signal by the complex sine wave signal and the means for storing the complex sine wave signal generation means or the means for storing the complex sine wave signal value are unnecessary, the circuit scale can be reduced.
It is advantageous for downsizing.

Example 5. FIG. 6 is a block diagram showing the configuration of band-pass type band limiting / sampling frequency reducing devices 101 and 103 according to the invention of claim 5.

The band pass type band limiting / sampling frequency reducing device 101 is constituted by connecting a plurality of band pass digital filters 21 to 2L and a plurality of decimators 31 to 3L in series. The center frequency of the pass band of the band-pass digital filters 21 to 2L is almost the same as the center frequency of the base discriminator meter output signal in the base band, and exists only at f> 0, and is almost the same as the bandwidth B of the received signal. Has a pass band width of. Although the transition band width differs depending on the filter, it can be made wider than the single complex coefficient bandpass digital filter as shown in FIG. 1 and the complex coefficient bandpass digital filter using a decimator.

Complex coefficient band pass digital filter 21
Since the coefficient of is a complex number, its output signal is also a complex number. Therefore, in FIG. 6, the arrow indicating the signal flow after the complex coefficient band pass digital filter 21 is indicated by a thick line.

In this embodiment, the sampling frequency is not set to 1 / D at one time, but the sampling frequency is set to 1 / D by repeating the operation of band limiting and sampling frequency reduction little by little. . In addition, D is an integer. If the sampling frequency to _{1 / D, D = D 1} · D 2 · ... · D when can be decomposed into a product of the L 2 or greater as _L, first the sampling frequency f _s1 Part 1 / D _{1 Is} f _s12
Then, the sampling frequency f _s12 is set to f _s13 , which is 1 / D ₂ of the sampling frequency, and the sampling frequency f _s12 is sequentially repeated L times. Note that L is an appropriate integer. Further, the integers D ₁ , D ₂ , ... In this embodiment are values different from the decimation ratios D ₁ , D ₂ in the above-mentioned embodiments ₂ , 4.

Each complex coefficient band pass digital filter 2
The word lengths of the output signals of 1 to 2 L are made longer than the word lengths of the input signals of the filters in both the real part and the imaginary part by reducing the sampling frequency. In FIG. 6, b ₁₁ ≧ b ₁ + log ₄ D ₁ , b ₁₂ ≧ b ₁₁ + log
_The bit rate is not reduced as ₄ D ₂ , ....

In such a configuration in which a plurality of complex coefficient bandpass digital filters and decimators are connected in series, when the decimation ratio D is large, each complex coefficient bandpass digital filter is not required to have a sharp cutoff characteristic. It has been found that the order is low, and thus the amount of calculation required for filtering can be made smaller than that in the configuration in which the single complex coefficient bandpass digital filter and the decimator shown in FIGS. 1 and 3 are connected in series.

Further, by properly selecting the center frequency of the complex coefficient band pass digital filter 21 of the first stage, the normalized center frequency of the complex coefficient band pass digital filters 22 to 2L of the second stage and thereafter (sampling of the input signal The center frequency normalized by the frequency) can be 0 or ± 0.5, and as a result, the digital filter 22 ...
2L can be a filter having only real numbers, and the amount of signal processing calculation can be further reduced.

In the above embodiments, the case where the band limiting / sampling frequency reducing means formed by connecting a plurality of band pass digital filters and a plurality of decimators in series has a band pass characteristic has been described, but the present invention is not limited to this. Alternatively, the low pass type band limiting / sampling frequency reducing means formed by connecting a plurality of low pass digital filters according to the present invention and a plurality of decimators in series may have band pass characteristics.

Example 6. FIG. 7 shows claims 7 and 9.
It is a block diagram which shows the structure of the band limitation / sampling frequency reduction apparatus 101 or 103 which concerns on the invention of description.
Since the reduction devices 101 and 103 have the same configuration, only the reduction device 101 will be described.

The band-pass type band limiting / sampling frequency reducing device 101 has a switch 70 for allocating the input signal x (k _T 1) to integer (D) paths 71 to 7D for each sample. Digital filters 81 to 8D are connected to the passages 71 to 7D, respectively. Further, the digital filters 81 to 8D are connected to an adder 80 as an adding means for adding the output signals of the D digital filters 81 to 8D. Incidentally, z3 is a delay operator for the sampling frequency f _s3 .

The switch 70 distributes the input signal x (kT ₁ ) of the band limiting / sampling frequency reducing device 101 to each of the D paths 71 to 7D one sample at a time. After allocating to the passage 7D, x (k
Allocate T ₁ ). Therefore, the sampling frequency of the signal passing through the paths 71 to 7D is 1 / D of the input signal x (kT ₁ ) of the band limiting / sampling frequency reducing device 101. That is, f _s1 / D = f _s3 . Each of the digital filters 81 to 8D also operates at a speed corresponding to the sampling frequency f _s3 . Therefore, here the delay operator z
It is expressed as 3.

The input timing of the input signal to the digital filter 81 is earlier than the signal input timing to the digital filter 82 by T ₁ . Digital filter 8
Similarly, the signal input timing to 2 is also advanced by the digital filter 83. The same applies hereinafter. At the output of each digital filter 81 to 8D, like the input signals,
The timings of the signals in the adjacent paths are shifted by T _1. Therefore, it is necessary to add D signals by the adder 80 and output them by D.
It takes time T ₁ (= T ₃ ). Therefore, the signal x _C (nT ₃ ) whose band-limited sampling frequency is reduced can be obtained from the output of this adder.

Since the coefficients of the digital filters 81 to 8D are complex numbers, their output signals are also complex numbers. Therefore, in FIG. 7, the arrows indicating the signal flow after each of the filters 81 to 8D are drawn with thick lines. The word length (b ₃ bits) of the output signal of each of the digital filters 81 to 8D is increased by reducing the sampling frequency in both the real part and the imaginary part. That is, the bit rate is not lowered by setting b ₃ ≧ b ₁ + log ₄ D. Impulse response p ₁ (n), p of each digital filter 81-8D
₂ (n), ..., p _D (n) are the band limits in FIG.
From the impulse response g (k) of the complex coefficient bandpass digital filter 5 of the sampling frequency reduction device 101, it can be calculated as shown in Expression (15).

P _i (n) = g (nD + i−1) (i = 1, 2, ..., D) (15) The advantage of such a structure is that each digital filter 81 to
Since it is not necessary to operate 8D as fast as the sampling interval T ₁ of the input signal x (kT ₁ ) of the switch 70, it is possible to support a high sampling frequency after all.

In the above embodiment, the band limitation
The case where the sampling frequency reduction device 101 has the band pass characteristic has been described, but the low band limiting / sampling frequency reduction device 102 having the low pass characteristic according to claims 8 and 10 may have the same configuration. it can. In this case, the complex coefficient band pass digital filter is replaced with a low pass digital filter having real number coefficients. The filter output signal is a real number.

Example 7. An embodiment of the invention according to claim 11 will be described.

As shown in FIG. 3 or 5, the band-pass type band limiting / sampling frequency reducing means 103 and the low-pass type band limiting / sampling frequency reducing means 102 have the same internal configuration. The band pass type band limiting / sampling frequency reducing means 103
And low-pass type band limiting / sampling frequency reducing means 1
The internal structure may be different from that of 02. For example, the low-pass band limiting / sampling frequency reducing means 102 may have the same configuration as that in FIG. 6, and the band-passing band limiting / sampling frequency reducing means 103 may have the same configuration as in FIG. 7 and vice versa. Good.

Example 8. In the above-described embodiment, the RF signal is converted into the IF signal, but depending on the sampling frequency that can be handled by the receiver or the A / D converter, the RF signal is directly converted into the digital signal and the quadrature detection processing is performed. It is also possible. In this case, the IF frequency f _{IF of the} signal is replaced with the carrier frequency f _c .

[0111]

As described above, according to the present invention, since the quantization noise is reduced in the digital quadrature detection processing, the number of quantization bits lower than the desired I component / Q component signal word length is obtained. A / D conversion can be used. In addition, it is fast and does not have many quantization bits.
High accuracy orthogonality is maintained by using the / D converter,
It is possible to easily obtain the I component and the Q component having a large signal-to-quantization noise power ratio.

Further, since the low pass band limiting / sampling frequency reducing means and the band pass type band limiting / sampling frequency reducing means are provided, the sampling frequency can be lowered in advance to some extent, and its complex coefficient band pass digital filter. The restriction of the characteristics of is removed, it is not necessary to use a digital filter with a narrow transition bandwidth for the digital filter, the order of the complex coefficient bandpass digital filter can be reduced, and the amount of calculation and the number of components required for filtering can be reduced. . As a result, signal deterioration due to the finite word length effect can be suppressed. Further, the filtering process in the low pass type band limiting / sampling frequency reducing means is a real number signal process, and the amount of calculation and the number of parts can be reduced.

By properly selecting the IF frequency and the sampling frequency in the sampler that follows,
It is not necessary to multiply the received signal by the complex sine wave signal, and the signal processing can be performed at higher speed. As a result, there is no need for means for multiplying the received signal by the complex sine wave signal, means for generating the complex sine wave signal, or means for storing the complex sine wave signal, and it is possible to reduce the circuit scale and achieve miniaturization. Further, it is possible to prevent the rounding noise from being generated.

Further, since the low pass band limiting / sampling frequency reducing means and the band pass type band limiting / sampling frequency reducing means are connected in series alternately with a plurality of digital filters and a plurality of decimators, the decimation ratio is large. In this case, a steep cutoff characteristic is not required for the digital filter, the filter order can be reduced, and thus the amount of calculation required for filtering can be further reduced, and the integrated circuit can be downsized and the finite word length effect can be obtained. Is also advantageous.

Then, a switch for dividing the input signal into the low-pass type band limiting / sampling frequency reducing means and the band-pass type band limiting / sampling frequency reducing means, and D parallel circuits connected to the respective channels. Since it is composed of various digital filters, it is not necessary to operate each digital filter as fast as the sampling interval of the input signal of the switch, and it is possible to cope with a high sampling frequency.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a digital quadrature detection device according to the inventions of claims 1 and 5.

FIG. 2 is a schematic diagram showing spectra before and after a sampling frequency of a bandpass signal is reduced.

FIG. 3 is a block diagram showing a configuration of a digital quadrature detection device according to the inventions of claims 2, 5 and 6.

FIG. 4 is a block diagram showing a configuration of a digital quadrature detection apparatus according to the invention of claim 3.

FIG. 5 is a block diagram showing a configuration of a digital quadrature detection device according to the invention of claim 4.

FIG. 6 is a block diagram showing a configuration of a band pass type band limiting / sampling frequency reducing device according to the invention of claim 7;

FIG. 7 is a block diagram showing a configuration of a band pass type band limiting / sampling frequency reducing device according to the invention of claim 9;

FIG. 8 is a block diagram showing a configuration of a conventional digital quadrature detection device.

[Explanation of symbols]

3,8 Sampler 4,9 A / D converter 5,10,13,21-2L Complex coefficient bandpass digital filter 6,12,14,15,31-3L Decimator 7 Multiplier 11 Low pass digital filter 70 Switch 80 adder 81 to 8D digital filter 101, 103 band pass type band limiting / sampling frequency reducing device 102 low pass band limiting / sampling frequency reducing device

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[Procedure amendment]

[Submission date] February 3, 1994

[Procedure Amendment 1]

[Document name to be amended] Statement

[Correction target item name] Full text

[Correction method] Change

[Correction content]

[Document name] Statement

Title: Digital quadrature detector

[Claims]

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital quadrature detector which receives a modulated signal and obtains its in-phase component (I component) and quadrature component (Q component) by digital signal processing.

[0002]

2. Description of the Related Art FIG. 8 shows, for example, PJvan Gerwin, NA.
Papers by M. Verhoeckx, HAvan Essen, FAM Snijders "
Microprocessor Implementation of High-Speed DataMo
dems "IEEE Transactions on Communications, vol.COM-2
5 is a block diagram showing a configuration of a digital quadrature detection device disclosed in “No. 2, pp. 238-250, february 1977” and “Application of Digital Signal Processing” edited by Institute of Electronics, Information and Communication Engineers.

This digital quadrature detector uses RF (R
narrow band modulation signal r
The mixer 1 has a mixer 1 for mixing (t) with a sine wave signal cos (2π (fc −f _IF ) t). The mixer 1 has an IF (Intermediadi) with a band-limited center frequency f _0.
An analog band pass filter 2 for converting into at frequency signal x (t) is connected. And
The analog bandpass filter 2 is connected to a sampler 8 that samples the analog bandpass signal that has passed through the analog bandpass filter 2 at a predetermined sampling frequency and converts it into a discrete time signal. A / D converter 9 for converting a digital signal into a digital signal
Are connected.

Further, the A / D converter 9 is connected with a complex coefficient band pass digital filter 10 which inputs the output x (mT) of the A / D converter 9 and generates an analytic signal x _A (mT). The complex coefficient bandpass digital filter 1
At 0, the complex sine wave signal exp is added to the analytic signal x _A (mT).
A multiplier 7 for multiplying [-j2πf _IF mT] is connected. The multiplier 7 is connected to a decimator 15 that extracts the output signal of the multiplier 7 at every sample number according to the degree of reduction of the sampling frequency.

Next, the operation will be described.

At the received carrier frequency fc, the bandwidth B (B
RF (Radio Frequency) of << fc)
The narrow band modulation signal r (t) is mixed with the sine wave signal cos (2π (fc −f _IF ) t) by the mixer 1 and the center frequency f band-limited by the analog band pass filter 2 is obtained.
₀ IF (Intermediate Frequency)
y) converted to signal x (t). Note that f ₀ and f _IF may be different. This IF signal x (t) is converted into a digital signal by the sampler 8 and the A / D converter 9 and becomes x (mT).

If the desired I component / Q component word length determined from the allowable quantization noise power of the I component / Q component is b ₃ bits, the number of quantization bits in the A / D converter 9 becomes the same. However, this b ₃ is not a value with a margin in order to reduce the influence of the rounding noise power due to the filtering following the A / D converter 9. When a margin is to be provided, c = 1 to 4, the word lengths of the I and Q components are (b ₃ + c) bits, and the number of quantization bits in the A / D converter 9 is b ₃ . The sampling frequency fsc, which is the reciprocal of the sampling period T, needs to satisfy the expression (1).

Fsc ≧ 2f ₀ + B (1) The band pass signal x (mT) can be generally expressed as in Expression (2).

X (mT) = a (mT) cos {2πf _IF mT + φ (mT)} = a (mT) cosφ (mT) cos (2πf _IF mT) −a (mT) sinφ (mT) sin (2πf _IF mT ) (2) where a (mT) is the envelope and φ (mT) is the phase. Also, I component I (mT) and Q component Q of x (mT)
(MT) is expressed as follows: I (mT) = a (mT) cosφ (mT) (3) Q (mT) = a (mT) sinφ (mT) (4)

A method of generating I (mT) and Q component Q (mT) from x (mT) will be described below.

The Hilbert transform of x (mT) is x _H (m
T), a complex signal x _A (mT) having x (mT) as a real part and x _H (mT) as an imaginary part is called an analytic signal.

X _A (mT) = x (mT) + jx _H (mT) (5) When the Fourier transform of x (mT) is X (f), the Fourier transform of the analytic signal x _A (mT) X _A ( f) is the following equation (6)
become that way.

[0013]

[Equation 1] That is, the spectrum at 0 <f / fsc <0.5 is twice that of x (mT), and the spectrum at −0.5 <f / fsc <0 is 0.

For such an analytic signal x _A (mT), a low-pass signal y (m
T) is defined.

Y (mT) = x _A (mT) exp [−j2πf _IF mT] = α (mT) + jβ (mT) (7) where α (mT) and β (mT) are real values. . In this case, there is at x (mT) = Re [y (mT) exp [j2πf IF mT]] = α (mT) co s (2πf IF mT) -β (mT) sin (2πf IF mT) ... (8) . Here, Re [•] means an operation that takes the real part of a complex number.

From equations (2) to (4) and equation (8), α (m
It can be seen that T) and β (mT) are the I component and the Q component of x (mT), respectively. That is, the bandpass signal x (m
When the analytic signal x _A (mT) corresponding to T) is multiplied by the complex sine wave signal exp [−j2πf _IF mT], it is shown that the real part is the I component and the imaginary part is the Q component. In FIG. 8, the analytic signal x _A (mT) is generated by the complex coefficient bandpass digital filter 10 having x (mT) as an input. Therefore, the frequency characteristic of the complex coefficient band pass digital filter 10 is 0 <f / fsc <0.5 in the pass band,
The other area is the stop zone. The output signal y (mT) obtained by multiplying the output signal x _A (mT) of the complex coefficient band pass digital filter 10 by the complex sine wave signal exp [−j2πf _IF mT] in the multiplier 7 is y (mT) = I (mT) + jQ (mT) (9) Since the bandwidth of y (mT) is generally narrower than the sampling frequency fsc, the decimator 15 takes out a signal every several samples, and the sampling frequency fsc.
It may be lowered to a smaller fs'. In FIG. 8, 1 / T '=
fsc '. However, fsc 'is about the same as or slightly larger than the bandwidth of y (mT). The real part and the imaginary part of the output of the decimator 15 are the I component (I (nT ')) and the Q component (Q (nT
´)).

The advantage of performing quadrature detection by digital signal processing as described above is that, unlike analog processing, the quadrature component of the I component and Q component can be maintained high, and the A / D converter has one advantage.
This is because there are only a few parts and there are few adjustment points for gain and phase. As a technique similar to the above-mentioned conventional example, Japanese Patent Laid-Open No. 64-5
7185 and Japanese Patent Laid-Open No. 1-300611.

[0018]

The conventional digital quadrature detector is constructed as described above and has the above-mentioned advantages, but the orthogonality between the obtained I component and Q component and the digital signal are obtained. The quantization noise power that cannot be avoided by processing depends on the number of quantization bits and the conversion accuracy in the A / D converter. In order to improve the orthogonality between the I component and the Q component and increase the signal-to-quantization noise power ratio, an A / D converter with high precision and a large number of quantization bits may be used. Increase the number of quantization bits in the
There are some problems in increasing the conversion accuracy as follows.

By changing the number of quantization bits to A / D
The hardware scale of the converter is increased, and the cost is increased. Further, extremely high-precision processing technology is required in the manufacture of integrated circuits, which makes it difficult to manufacture a high-precision A / D converter. Before performing A / D conversion, an analog pre-filter is required to prevent aliasing due to sampling, but if the upper limit of the signal band and the Nyquist frequency are close,
A high order filter is required. The number of amplifying elements in the high-order active filter also increases, and noise and distortion generated in the amplifier cannot be ignored. As a result, there is a problem that the signal-to-noise power ratio decreases. Also,
When the sampling frequency is reduced by the decimator 15,
Aliasing due to the received signal itself does not occur,
Since the aliasing is caused by the quantization noise and the rounding noise, there is a problem that the signal-to-noise ratio is further deteriorated. The present invention has been made to solve the above problems, and has high-accuracy orthogonality and signal-to-quantization noise power without using an A / D converter having a large number of quantization bits. It is an object of the present invention to obtain a digital quadrature detector capable of obtaining an I component and a Q component having a large ratio.

[0020]

According to a first aspect of the present invention, there is provided a digital quadrature detection device which receives a received IF frequency f _IF.
Sampling means for sampling the analog band-pass signal at a predetermined sampling frequency to convert it into a discrete time signal, and quantizing the discrete time signal with a predetermined number of quantization bits shorter than the word length of the desired in-phase component and quadrature component. A /
D conversion means, band pass type band limiting / sampling frequency reducing means for performing band pass type band limiting on the output signal of the A / D converting means and reducing sampling frequency, and the band pass type band limiting / sampling frequency The band-pass type band limiting / sampling frequency reducing means comprises an multiplying means for multiplying the output signal of the reducing means by a complex sine wave signal of a predetermined frequency, and the band-pass type band limiting / sampling frequency reducing means, with respect to the sampling frequency _fs1 of the input signal 0 <f / f _s1 <0.
5 has a band-pass characteristic of passing only a predetermined frequency component of 5, and extends the word length of the output signal of the band-pass type band limiting / sampling frequency reducing means from the tone of the input signal. .

According to a second aspect of the present invention, there is provided a digital quadrature detection apparatus, wherein sampling means is provided for sampling the received analog band pass signal of the IF frequency f _{IF at} a predetermined sampling frequency and converting it into a discrete time signal, and a desired in-phase signal. A / D conversion means for quantizing the discrete-time signal with a predetermined number of quantization bits shorter than the word lengths of the component and the orthogonal component, and a low-pass low-frequency limit for the output signal of the A / D conversion means. A low pass band limiting / sampling frequency reducing means for reducing the sampling frequency, and a band pass band limiting for the output signal of the low pass type band limiting / sampling frequency reducing means and reducing the sampling frequency. Band-pass type band limiting / sampling frequency reducing means and output of the band-pass type band limiting / sampling frequency reducing means No. and a complex sine wave signal of a predetermined frequency are multiplied, and the low-pass type band limiting / sampling frequency reducing means has a low-pass characteristic of a predetermined cut-off frequency, and its output signal The word length is extended from the word length of the input signal, and the band pass band limiting / sampling frequency reducing means _sets 0 <f / f _s2 <0.5 of the input signal to the sampling frequency f _s2 of the input signal.
Of the band-pass type band limiting / sampling frequency reducing means, the word length of the output signal is expanded from the tone of the input signal.

The digital quadrature detector according to the present invention comprises sampling means for sampling the received analog band pass signal of the IF frequency f _{IF at} a predetermined sampling frequency f _s1 and converting it into a discrete time signal, and A / D conversion means for quantizing the discrete-time signal with a predetermined number of quantization bits shorter than the word lengths of the in-phase component and the quadrature component, and a band-pass band for the output signal of the A / D conversion means. Band-pass type band limiting / sampling frequency reducing means for limiting and reducing the sampling frequency, wherein the IF frequency f _IF is an integer multiple of 1 or more of the sampling frequency f _s3 of the desired in-phase component and quadrature component, and sampling frequency f _s1 of the sampling means for converting the discrete-time signal by sampling the analog bandpass signal, the a Greater than a value obtained by adding the bandwidth of the analog bandpass signal to twice the central frequency of the log bandpass signal, the bandpass band limited sampling frequency reduction means, the sampling frequency f _s1 of the input signal, The input signal has a band-pass characteristic of passing only a predetermined frequency component of 0 <f / _fs1 <0.5, and the word length of the output signal of the band-pass type band limiting / sampling frequency reducing means is It is characterized by expanding from the tone.

The digital quadrature detector according to the present invention comprises sampling means for sampling the received analog band pass signal of the IF frequency f _{IF at} a predetermined sampling frequency f _s1 and converting it into a discrete time signal, Of A / D conversion means for quantizing the discrete-time signal with a predetermined number of quantization bits shorter than the word lengths of the in-phase component and the quadrature component, and a low-pass type for the output signal of the A / D conversion means. Low-pass type band limiting / sampling frequency reducing means for performing band limiting and reducing the sampling frequency, and band-pass type band limiting for an output signal of the low-pass type band limiting / sampling frequency reducing means, and and a band-pass band-limiting sampling frequency reduction means for reducing the sampling frequency, the IF frequency f _IF is desired phase component and linear 1 or more integer multiples and the sampling frequency f _s1 of the sampling means for converting the analog bandpass signal sampling and discrete-time signals, the sampling frequency of the desired phase and quadrature components of the components of the sampling frequency f _s3 is a non-prime integer multiple of f _s3 , and the sampling frequency f _s1 is greater than twice the center frequency of the analog band pass signal plus the bandwidth of the analog band pass signal, and the low pass band limiting / sampling is performed. The frequency reducing means _sets the sampling frequency f _s2 of the input signal to 0 <
It has a band-pass characteristic of passing only a predetermined frequency component of f / f _s2 <0.5, and extends the word length of the output signal of the low-pass band limiting / sampling frequency reducing means from the tone of the input signal. It is characterized by that.

According to a fifth aspect of the present invention, there is provided a digital quadrature detector having a bandwidth corresponding to the degree of reduction of the sampling frequency or the bandwidth of the input signal of the required band pass type band limiting / sampling frequency reducing means. A band in which the center frequency of the pass band limiting / sampling frequency reducing means is equal to the center frequency or IF frequency f _{IF of the} input signal and the pass band exists in a predetermined range between 0 and 1/2 of the sampling frequency of the input signal. The band pass band limiting / sampling frequency reducing means is configured by connecting in series a pass digital filter and decimation means for extracting the output signal of the band pass digital filter at every sample number according to the degree of reduction of the sampling frequency. The word length of the output signal of the bandpass digital filter is the input It is characterized in that is extended from the word length of the item.

According to a sixth aspect of the present invention, there is provided a digital quadrature detection apparatus, wherein a low pass digital filter having a cutoff frequency corresponding to the degree of reduction of the sampling frequency and an output signal of the low pass digital filter are reduced in the sampling frequency. And a decimation means for taking out every number of samples according to the frequency, are connected in series to constitute the low-pass type band limiting / sampling frequency reducing means, and the word length of the output signal of the low-pass digital filter is input to the input. It is characterized by being extended from the word length of the signal.

According to a seventh aspect of the present invention, there is provided a digital quadrature detector in which a band pass digital filter having a predetermined band width and a center frequency and a decimation for extracting a predetermined number of samples connected in series to the band pass digital filter. And a plurality of sets are connected in series to constitute the band pass type band limiting / sampling frequency reducing means, and the word lengths of the output signals of the plurality of band pass digital filters are expanded from the word lengths of the input signals. It is characterized by that.

A digital quadrature detector according to the present invention is a low-pass digital filter having a predetermined bandwidth, and decimation means connected in series to the band-pass digital filter to take out every predetermined number of samples. By connecting a plurality of sets in series, the low-pass band limiting
The sampling frequency reducing means is constituted, and the word length of the output signal of the plurality of low-pass digital filters is extended from the word length of the input signal.

According to a ninth aspect of the present invention, in the digital quadrature detector, the band pass type band limiting / sampling frequency reducing means, and the band pass type band limiting / sampling frequency reducing means use the sampling frequency as an integer (D) of the input signal. ₂ ) A switch that distributes the input signal for each sample to an integer (D ₂ ) path when it is reduced to the reciprocal (1 / D ₂ ) and a plurality of switches connected to the integer (D ₂ ) path, respectively. (D ₂₎ and the number of digital filters, a plurality (D ₂₎ pieces of summing the output signal of the digital filter is composed of an adding unit, a plurality (D ₂₎ pieces of output of the output signal or said adding means of the digital filter It is characterized in that the word length of the signal is extended from the word length of the input signal of the band pass type band limiting / sampling frequency reducing means.

According to a tenth aspect of the present invention, in the digital quadrature detector, the low pass type band limiting / sampling frequency reducing means and the low pass type band limiting / sampling frequency reducing means set the sampling frequency to an integer of an input signal. They are respectively connected to the input signal and a switch for distributing the passage integer (D ₁₎ present in each sample, an integer (D ₁₎ to the passageway when attempting to reduce the reciprocal ₍₁ / D 1) of (D ₁₎ a plurality (D ₁₎ pieces of digital filters, a plurality (D ₁₎ pieces of summing the output signal of the digital filter is composed of an adding unit, a plurality (D ₁₎ number of output signals or said adding means of the digital filter The word length of the output signal of is extended from the word length of the input signal of the low pass band limiting / sampling frequency reducing means.

In the digital quadrature detection apparatus according to the present invention, the low pass band limiting / sampling frequency reducing means has a low pass digital filter and a low pass filter having a cutoff frequency corresponding to the degree of reduction of the sampling frequency. The output signal of the low-pass digital filter is connected in series with decimation means for extracting every sample number according to the degree of reduction of the sampling frequency, or is connected in series with the low-pass digital filter and low-pass digital filter of a predetermined bandwidth. A plurality of decimation means connected in series for extracting every predetermined number of samples are connected in series, or a low-pass band limiting / sampling frequency reducing means sets the sampling frequency to an integer (D
₁ ) A switch that divides the input signal into integer (D ₁ ) channels for each sample when it is reduced to the reciprocal (1 / D ₁ ), and a plurality of switches connected to the integer (D ₁ ) channels ( D ₁ ) digital filters and multiple (D ₁ )
Input means of the band pass type band limiting / sampling frequency reducing means or the required band pass type band limiting / sampling frequency reducing means. And the center frequency of the band pass type band limiting / sampling frequency reducing means is equal to the center frequency or IF frequency f _{IF of the} input signal and the pass band is from 0 to 1 of the sampling frequency of the input signal. The band pass digital filter existing in a predetermined range between / 2 and the decimation means for extracting the output signal of the band pass digital filter at every sample number according to the degree of reduction of the sampling frequency are connected in series, or Bandpass digital filter with bandwidth and center frequency Decimation means for retrieving a predetermined number of samples every connected in series to the fine band-pass digital filter constituted by connecting a plurality of sets in series, or band-pass band-limiting sampling frequency reduction means integral of the input signal sampling frequency (D ₂ ) reciprocal (1
/ D ₂ ), a switch that distributes the input signal for each sample to an integer (D ₂ ) path when trying to reduce it, and a plurality of (D ₂ ) digital signals respectively connected to the integer (D ₂ ) paths. It is characterized by comprising a filter and an addition means for adding output signals of a plurality of (D ₂ ) digital filters.

[0031]

In the digital quadrature detector according to the first and fifth aspects of the present invention, the IF signal is the IF frequency f _IF of 4
Doubled and oversampled at a sampling frequency of 4 times the bandwidth of the IF signal or more, and the desired I
Quantization is performed with a quantization bit number smaller than the word length (bit number) of the component and the Q component. The oversampled signal is f> by a narrow band complex coefficient bandpass digital filter whose passband is only the signal band of frequency f> 0.
Only the frequency component of 0 is extracted, and the sampling frequency is reduced to the signal bandwidth. This reduces the quantization noise and makes the amplitude resolution of the digital signal by making the word lengths of the real and imaginary parts of the complex coefficient bandpass digital filter output signal longer than that of the complex coefficient bandpass digital filter input signal. maintain. The frequency component of f _IF before the sampling frequency reduction moves after the sampling frequency reduction, but f in the base band
If the frequency f _b corresponding to _IF is not 0, a complex sine wave signal of an appropriate frequency is multiplied to move the frequency component corresponding to f _b to 0. The real part of the signal thus obtained is the desired I component, and the imaginary part is the Q component.

In the digital quadrature detection device according to the present invention as defined in claims 2, 5, and 6, the IF signal is converted into an IF signal.
Oversampling at a sampling frequency that is 8 times the frequency f _IF and 8 times or more the bandwidth of the IF signal, and the number of quantization bits that is smaller than the desired I component and Q component word length (bit number) by the A / D conversion means. Quantize with. In order to reduce the amount of signal processing calculation and the amount of hardware in the subsequent complex coefficient band pass digital filter, the band of the oversampled signal is once limited by the low pass digital filter, and the sampling frequency is appropriately reduced. At this time, the quantization noise is reduced by the low pass digital filter. The low pass digital filter output signal is made longer than that of the input signal to maintain the amplitude resolution of the digital signal. The signal thus obtained is extracted by a narrow band complex coefficient band pass digital filter having a signal band of frequency f> 0 as a pass band, and only the frequency component of f> 0 is extracted, and the sampling frequency is reduced to a signal bandwidth equivalent. To do. This reduces quantization noise and maintains the amplitude resolution of the digital signal by making the word length of the complex coefficient bandpass digital filter output signal longer than that of the complex coefficient bandpass digital filter input signal. The frequency component of f _IF before the sampling frequency reduction moves after the sampling frequency reduction, but if the frequency f _b corresponding to f _IF in the base band is not 0, it is multiplied by a complex sine wave signal of an appropriate frequency to f _b. The frequency component corresponding to is moved to zero. The real part of the signal thus obtained is the desired I component, and the imaginary part is the Q component.

In the digital quadrature detector according to the present invention as defined in claims 3 and 4, the center frequency of the IF signal and the sampling frequency are appropriately selected so that multiplication of the processed reception signal and the complex sine wave signal is unnecessary. I have to.

In the digital quadrature detector according to the present invention as defined in claims 7 and 8, the sampling frequency is reduced little by little, whereby the transition band width of each band pass or low pass digital filter is set wide, and The band pass or low pass digital filter order can be kept low, and the amount of signal processing calculation can be small. The amplitude resolution is maintained by making the word length of the output signal of each band-pass or low-pass digital filter longer than that of the input signal according to the degree of reduction of the sampling frequency.

In the digital quadrature detector according to the present invention as defined in claims 9 and 10, the input signal is distributed to a plurality of digital filters for each sample for parallel processing, and the outputs thereof are added to limit the band. And the sampling frequency is reduced at the same time. Amplitude resolution is maintained by making the word length of the output signal of the band limiting / sampling frequency reducing means longer than that of the input signal.

[0036]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. First, oversampling A / D in which sampling is performed at a sampling frequency larger than twice the Nyquist frequency, A / D conversion with low resolution (quantization bit number) is performed, and the sampling frequency is reduced after band limitation by a digital filter. The conversion technology will be described. The reason why the oversampling technique is drawing attention is that the A / D is required in order to obtain a high accuracy and a large signal to quantization noise power ratio.
While it is difficult to increase the resolution of the converter (increase the number of quantization bits), it is easier to manufacture an A / D converter with a low resolution (lower number of quantization bits) but a higher sampling frequency. Is. In addition, since the sampling frequency is considerably higher than the signal band to be converted, the restrictions on the characteristics of the analog filter before sampling are relaxed, and only low-order ones are required. Therefore, it becomes easy to form an integrated circuit.

Next, the principle of oversampling will be briefly described.

A / which performs linear quantization of the quantization step Δ
Consider a D converter. When the quantization noise power N _Q assuming that quantization noise is uniformly distributed between the areas ± Δ / 2, the N _Q = Δ ^2/12. It is known that this is in good agreement with reality when the input signal amplitude is several times larger than the quantization step. Assuming that the quantization noise is white noise, the sampling frequency is f _s , the required band is −f _B ≦ f ≦ f _B , and the other bands are removed by a low-pass digital filter. power N _{Q ^{is, N Q = (Δ 2/}} 12) the _{(2f B / f s) ...} (10). For a sine wave signal, the maximum signal-to-quantization noise power ratio S / N _Q obtained with a b-bit A / D converter is

[Equation 2] Becomes

According to equation (11), if the sampling frequency is made higher than the required band for A / D conversion, and then low-pass filtering is performed, the quantization noise power becomes small, and as a result, equivalently. It can be seen that the resolution increases. For example, quadrupling the sampling frequency improves the signal to quantization noise power ratio by about 6 dB. This corresponds to an increase in resolution by 1 bit. Even if the number of quantization bits is reduced by 1, the same resolution can be obtained by quadrupling the sampling frequency. Thus, if an A / D converter with a low quantization bit rate but a high speed and a low-pass digital filter are used, an A / D converter with a low quantization bit rate but a high quantization bit number can be used.
The same effect as when using the D converter can be obtained. This utilizes the fact that the quantization noise power in the signal band decreases when the sampling frequency is increased because the quantization noise power does not depend on the sampling frequency.

The above is a multi-bit A / for performing linear quantization.
Although the case where the D converter is used, the equations that give the quantization noise power and the signal-to-quantization noise power ratio are different even in the oversampling A / D converter using ΔΣ modulation.
Even if a bit quantizer is used, the quantization noise level in the signal band becomes extremely low, and therefore the resolution can be increased by oversampling.

In the case of the A / D converter using the second-order ΔΣ modulation and the 1-bit quantizer, the maximum signal-to-quantization noise power ratio S / N _Q for a sine wave signal is

[Equation 3] It is known that Here, _assuming that f _s / 2f _B = 128, the signal-to-quantization noise power ratio S / N _Q is about 94d.
B, the resolution equivalent to 15 bits when oversampling is not performed can be obtained.

Example 1. FIG. 1 shows claims 1 and 5.
It is a block diagram which shows the structure of the digital quadrature detection apparatus which concerns on invention of description.

The digital quadrature detector uses an RF narrow band modulation signal r (t) and a sine wave signal cos (2π (fc-
f _IF ) t) is included in the mixer 1. The mixer 1 includes an IF signal x having a band-limited center frequency f _0.
An analog bandpass filter 2 for converting to (t) is connected. And, in the analog band pass filter 2,
A sampler 3 as sampling means for sampling the analog band-pass signal that has passed through the analog band-pass filter 2 at a predetermined sampling frequency and converting it into a discrete-time signal is connected, and the discrete-time signal from the sampler 3 is converted into a digital signal. An A / D converter 4 for conversion is connected.

Further, the A / D converter 4 receives the output x (kT ₁ ) of the A / D converter 4 and outputs a signal x _C (nT ₃ ). The limiting / sampling frequency reducing device 101 is connected, and the band pass type band limiting / sampling frequency reducing device 101 outputs the complex sine wave signal exp to the output signal x _C (nT ₃ ).
A multiplier 7 is connected as a multiplication means for multiplying [-j2πnf _b / f _s3 ]. Then, the band pass type band limiting / sampling frequency reduction device 101 takes out the band pass digital filter 5 and the output signal x _A (kT ₁ ) of the band pass digital filter 5 at every sample number corresponding to the degree of reduction of the sampling frequency. The decimator 6 serves as decimation means.

Next, the operation of this embodiment will be described.

Carrier frequency fc, bandwidth (B << fc)
Of the received RF signal r (t) is mixed with the sine wave signal cos (2π (fc −f _IF ) t) by the mixer 1, and the center frequency f is band-limited by the analog bandpass filter 2.
The IF signal x (t) of ₀ is converted. Note that f ₀ and f _IF
May differ from. Note that x (t) is sampled by the sampler 3 at the sampling frequency f _s . f _s should be at least 4 times the IF frequency and 4 times the bandwidth of x (t) for oversampling.

The A / D converter 4 converts the signal sampled by the sampler 3 into a digital signal. When a multi-bit A / D converter that performs linear quantization is used, the number of quantization bits b ₁ in the A / D converter 4 is a desired I component determined from the allowable quantization noise power of I component / Q component. the number of bits of the Q component b ₃ (> b _1), when the sampling frequency f _s3, the integer value of _{b 3 -log 4 (f s1 /} f s3) or the minimum is a measure. On the contrary, the quantization bit number b ₁ in the A / D converter 4 and the desired I component / Q component bit number b
You may decide f _s1 from ₃ . However, this b ₃ is not a value provided with a margin in order to reduce the effect of rounding noise. To give a margin, set c = 1 to 4 and
The word lengths of the I and Q components are (b ₃ + c) bits, and the number of quantization bits in the A / D converter 4 is b ₁ as described above.

In selecting f _s1 and f _s3 , f _s1 / f _s3
The value of is preferably an integer value of 2 or more for the sake of simplification of the circuit. Here, description will be given assuming that such selection is made.

In the case of the A / D converter using the second-order ΔΣ modulation / 1-bit quantizer, the sampling frequency f _s1 in the sampler 3 is determined from the desired bit number b ₃ of the I component / Q component and the sampling frequency f _s3. .

[0050]

[Equation 4] The degree is a guideline. Needless to say, A / D converters other than those exemplified here can be used.

The input to the A / D converted band pass digital signal _{x (kT 1) (T 1} = 1 / f s1) bandpass bandlimited sampling frequency reduction device 101. This band pass type band limiting / sampling frequency reducing device 10
1, the center frequency is f ₀ or f _IF , the pass band width is almost the same as or slightly wider than the reception signal bandwidth B, and −0.
5 <f / f _s1 <0 has no passband, and the impulse response is a complex coefficient bandpass digital filter 5 having a complex number,
The decimator 6 is connected in series. In the complex coefficient bandpass digital filter 5, the input signal x
(KT ₁ ) is converted into an analytic signal x _A (kT ₁ ). x
_A (kT ₁ ) has a plurality of values, and a signal having a plurality of values is shown by a thick line in FIG.

Then, the decimator 6 reduces the sampling frequency f _s1 to f _s3 = f _s1 / D. This is an operation of taking the output signal x _A (kT ₁ ) of the complex coefficient band pass digital filter 5 every (D−1). Note that f _s3 is the bandwidth B of x _A (kT ₁ ).
Is about the same as or slightly larger, and D is 2
The above is an appropriate integer.

The complex coefficient band-pass digital filter 5 suppresses the quantization noise outside the signal band and the DC component generated at the time of A / D conversion by setting the pass band to the same level as the bandwidth of the received signal. Then, in the complex coefficient bandpass digital filter 5, a product-sum operation of the signal and the filter coefficient is performed, whereby the signal word length inside the digital filter becomes longer by the filter coefficient word length. This is usually rounded to some word length at the output of the digital filter 5 which is shorter than that. At that time, the word length of the output signal x _A (kT ₁ ) of the complex coefficient band-pass digital filter 5 has both the real part and the imaginary part of the input signal x (k
The sampling frequency is reduced from the word length of T ₁ ) to be b ₃ bits. In addition, in order to reduce the effect of rounding noise, it is desirable to increase it by several bits as described above. If this is not done, the quantization noise reduction effect of the complex coefficient bandpass digital filter 5 does not appear. On the contrary, even if the sampling frequency is reduced by performing such an operation, aliasing noise due to aliasing does not occur, and therefore, the resolution of the amplitude in the digital signal can be maintained, so that there is a highly accurate orthogonality and the signal-quantum It is possible to obtain the I component and the Q component having a large noise power ratio.

FIG. 2 shows the output signal x of the complex coefficient bandpass digital filter 5 by reducing the sampling frequency.
_A (kT ₁ ) and output signal x _C (nT ₃ ) of the decimator 6
Shows the relationship between the spectrum of _{(T 3 = 1 / f s3} ). Note that FIG. 2 is an example in which the sampling frequency is reduced to 1/4 (D = 4). Where IF frequency and x
The center frequency f ₀ of _A (kT ₁ ) will be described as being in agreement. The spectrum of the output signal x _A (kT ₁ ) of the complex coefficient band-pass digital filter 5 is drawn by a solid line, and the broken line and the alternate long and short dash line show x _C (n by folding back caused by reducing the sampling frequency to ¼.
T ₃ ) spectrum, of which what is required is a chain line spectrum in the baseband.

[0055] When in the range of IF frequencies f (K-0.5) for integer K which is _{IF f s3 <f IF ≦ (} K + 0.5) f s3, x A of f _IF of (kT ₁₎ The frequency component moves to f _b in the baseband due to decimation.

F _b = f _IF −Kf _s3 (14) F _{b in the} equation (14) does not always become 0. Therefore, the frequency component of f _b is moved to 0 by multiplying x _C (nT ₃ ) by the complex sine wave signal exp [−j2πnf _b / f _s3 ] by the multiplier 7. The real part of the output signal y (nT ₃ ) of the multiplier 7 is the desired I component I (n
T ₃ ) and the imaginary part is the Q component Q (nT ₃ ).

As described above, by introducing the oversampling technique into the digital quadrature detection processing, the A / D conversion is performed with a quantization bit number lower than the desired I component / Q component signal word length. That is, A / of the multi-quantization bit number
It has high-precision orthogonality without using a D converter,
It is possible to realize a digital quadrature detection device that can obtain an I component and a Q component having a large signal-to-quantization noise power ratio.

Example 2. FIG. 3 is a block diagram showing the configuration of a digital quadrature detection device according to the invention described in claims 2, 5, and 6. It should be noted that the same components as those in FIG.

Reference numeral 102 is a low-pass type band limiting / sampling frequency reducing device, 103 is a band-pass type band limiting / sampling frequency reducing device, and low-pass type band limiting / sampling frequency reducing device 102 is a low-pass type. The bandpass digital filter 11 and the decimator 12 are included, and the bandpass band limiting / sampling frequency reduction device 103 is composed of a complex coefficient bandpass digital filter 13 and a decimator 14. As described above, the purpose of connecting the low-pass band limiting / sampling frequency reducing device 102 and the band-pass band limiting / sampling frequency reducing device 103 in series is to convert an oversampled band-pass signal into an analytic signal. This is to reduce the amount of signal processing calculation in the complex coefficient bandpass digital filter 13 and to simplify the hardware.

Next, the operation of this embodiment will be described.

Since the process of converting the received RF signal r (t) having the carrier frequency f _c and the bandwidth B into the IF signal x (t) is the same as that of the above-described first embodiment, the description thereof will be omitted.

X (t) is sampled by the sampler 3 at the sampling frequency f _s1 . f _s1 is at least 8 times the IF frequency for oversampling and x
It is 8 times or more the bandwidth of (t).

The A / D converter 4 converts the signal sampled by the sampler 3 into a digital signal. When a multi-bit A / D converter that performs linear quantization is used, the number of quantization bits b ₁ in the A / D converter 4 is the desired I component
The number of bits of the Q component b ₃ (> b _1), when the sampling frequency f _s3, the integer value of _{b 3 -log 4 (f s1 /} f s3) or the minimum is a measure. Conversely, the A / D converter 4 quantization bits b ₁ to the bit number b ₃ of the desired I component · Q component in may be determined f _s1. However, this b ₃
Is not a value with a margin in order to reduce the effect of rounding noise. When a margin is provided, c = 1 to 4 and the word lengths of the I and Q components are (b ₃ + c) bits, A
The number of quantization bits in the / D converter 4 is b ₁ as described above.
And f _s1 and f _s3 , and in selecting the sampling frequency f _s2 at the output of the decimator 12 described later, f
It is desirable that the values of _s1 / f _s2 and f _s2 / f _s3 be integer values of 2 or more for simplification of the circuit. Hereinafter, these ratios will be described as being integers.

In the case of the A / D converter using the secondary ΔΣ modulation / 1-bit quantizer, the sampling frequency f _s1 in the sampler 3 is determined from the desired bit number b ₃ of I component / Q component and the sampling frequency f _s3. . The standard is calculated by the above equation (13). Needless to say, A / D converters other than those exemplified here can be used.

In order to reduce the amount of signal processing calculation in the complex coefficient bandpass digital filter 13 for converting the oversampled bandpass signal into an analytic signal and to simplify the hardware, the output signal of the A / D converter 4 x (kT
₁ ) (T ₁ = 1 / f _s1 ) is once reduced to the sampling frequency f _s2 (= f _s1 / D ₁ ) by the low pass band limiting / sampling frequency reducing device 102. D ₁ is an integer of 2 or more. Hereinafter, the degree of reduction of the sampling frequency such as D ₁ will be referred to as the decimation ratio.
The decimation ratio is a value greater than 1.

In the low pass band limiting / sampling frequency reducing device 102, the low pass digital filter 11 is used.
And a decimator 12 are connected in series, and in order to prevent aliasing due to quantization noise, low-pass band limiting is performed by the low-pass digital filter 11.
The decimator 12 reduces the sampling frequency to f _s2 .
This is an operation for taking every (D ₁ -1) output signals of the low-pass digital filter 11. Note that it is necessary to satisfy f _s2 > 2f ₀ + B.

The cutoff frequency of the low-pass digital filter 11 is set to f _s1 / 2D ₁ or less. The coefficient of the low-pass digital filter 11 is a real number. In FIG. 3, the delay operator for the sampling frequency f _s1 is z
1, the delay operator for the sampling frequency f _s2 is z2
Is represented.

Inside the low-pass digital filter 11, a product-sum operation of the signal and the filter coefficient is performed, whereby the signal word length inside the digital filter becomes longer by the filter coefficient word length. This is usually rounded to a certain word length at the output of the digital filter 11.
At this time, the word length (b ₂ bits) of the output signal of the low-pass digital filter 11 is made longer than the word length (b ₁ bit) of the input signal of the digital filter 11 by the amount obtained by reducing the sampling frequency. That is, the bit rate is not lowered by setting b ₂ ≧ b ₁ + log ₄ D ₁ . By doing so, the resolution of the digital signal amplitude can be maintained even if the sampling frequency is reduced. In order to reduce the effect of rounding noise, it is desirable that b ₂ be several bits larger than the minimum value given by the above equation.

Then, the output signal x ₂ (mT ₂ ) of the low pass type band limiting / sampling frequency reducing device 102 is
x ₂ (mT ₂ ) A band-pass type band limiter that passes only the band of 0 <f / f _s2 <0.5, converts it into an analytic signal, and lowers the sampling frequency to the same level as the signal band B.
Input to the sampling frequency reduction device 103.

The band pass type band limiting / sampling frequency reducing device 103 in FIG. 3 has a center frequency f ₀ or f
_{At IF} , the passband width is about the same as the signal bandwidth B and -0.5 <
For f / f _s2 <0, a complex coefficient band pass digital filter 13 having no pass band and a decimator are connected in series.

Complex coefficient band pass digital filter 13
, The input signal x ₂ (mT ₂ ) is the analytic signal x _A2
Converted to (mT ₂ ). x _A2 (mT ₂ ) has a plurality of values, and a signal having a plurality of values is indicated by a thick line in FIG.

Then, the decimator 14 reduces the sampling frequency f _s2 to f _s3 = f _s2 / D ₂ . This is a sample of the output signal x _A2 (mT ₂ ) of the complex coefficient band pass digital filter 13 (D ₂ −
1) It is an operation to take every other piece. Note that f _s3 is x _A2 (mT
₂ ) The bandwidth B is approximately the same value, and D ₂ is an appropriate integer of 2 or more.

Complex coefficient bandpass digital filter 13
By setting the pass band of the same as the bandwidth of the IF signal, the quantization noise outside the signal band and the DC offset component generated during A / D conversion are suppressed. The word length of the output signal x _C3 (nT ₃ ) of the complex coefficient band pass digital filter 13 is the same as that of the low pass digital filter 11 in both the real part and the imaginary part of the complex coefficient band pass digital filter 13. The sampling frequency is made smaller than the word length of the input signal x ₂ (mT ₂ ). That is, the bit rate is not lowered by setting b ₃ ≧ b ₂ + log ₄ D ₁ . By doing so, the resolution of the digital signal amplitude can be maintained even if the sampling frequency is reduced. In addition, in order to reduce the effect of rounding noise, it is desirable to increase it by several bits as described above.

Complex coefficient band pass digital filter 13
Output signal x _A2 (mT ₂ ) and the output signal x _C3 (n of the band pass type band limiting / sampling frequency reduction device 103
The relationship of the spectrum of T ₃ ) is the output signal x of the complex coefficient band pass digital filter 13 in the above-mentioned embodiment.
_A (kT ₁ ) and output signal x _C (nT ₃ ) of the decimator 6
Is the same as the relationship.

Complex coefficient band pass digital filter 13
The frequency component of f _IF of the output signal x _A2 (mT ₂ ) of 1 moves to f _b in the baseband after decimation. This f
_b does not always become 0. Therefore, the multiplier 7 outputs the complex sine wave signal exp [-j2πnf to x _C3 (nT ₃ ).
_b / f _s3 ] to multiply the frequency component of f _b to 0
Move to. The real part of the output signal y (nT ₃ ) of the multiplier 7 is the desired I component I (nT ₃ ), and the imaginary part is the Q component Q (n
T ₃ ).

As described above, by introducing the oversampling technique into the digital quadrature detection processing, the A / D conversion is performed with the quantization bit number lower than the desired I component / Q component signal word length. That is, A / of the multi-quantization bit number
It has high-precision orthogonality without using a D converter,
It is possible to realize a digital quadrature detection device that can obtain an I component and a Q component having a large signal-to-quantization noise power ratio. Furthermore, a low-pass type band limiting / sampling frequency reducing device 102
By providing, the sampling frequency can be lowered to some extent in advance at the input of the complex coefficient bandpass digital filter 13. Therefore, the restrictions on the characteristics of the complex coefficient bandpass digital filter 13 are looser than those of the conventional example. That is, it does not have to be a narrow transition bandwidth filter. Therefore, the order of the complex coefficient bandpass digital filter 13 is reduced, and the amount of hardware can be reduced. As a result, the amount of signal processing calculation required for filtering in the complex coefficient bandpass digital filter 13 can be reduced. The filtering process in the band pass type band limiting / sampling frequency reducing device 103 handles complex numbers, whereas the filtering process in the low pass type band limiting / sampling frequency reducing device 102 is a real-valued signal process. Even if two band pass type band limiting / sampling frequency reducing means are combined, there is an advantage that the amount of calculation is smaller than in the case of the first embodiment.

Example 3. FIG. 4 is a block diagram showing the configuration of a digital quadrature detection device according to the invention of claim 3. It should be noted that the same components as those in FIG. In this embodiment, the IF frequency f _IF
By appropriately selecting the sampling frequency f _s1 in the sampler 3 and the sampler 3, the complex sine wave signal exp [−j2πnf _b / f _s3 ] is added to the output signal x _C (nT ₃ ) of the band pass type band limiting / sampling frequency reducing device 101. The multiplier 7 for multiplication is omitted.

As shown in FIG. 2, band pass type band limiting
When the output signal x _A (kT ₁ ) of the bandpass digital filter 5 of the sampling frequency reduction device 101 is reduced to the sampling frequency f _s3 (= f _s1 / D), a folded spectrum is generated. The frequency component of f _IF of x _A (kT ₁ ) moves by decimation, but if f _b existing in the base band −f _s3 / 2 ≦ f ≦ f _s3 / 2 is 0, the band pass in FIG. In the multiplier 7 following the band limiting / sampling frequency reducing device 101, x _C (nT ₃ ) and the complex sine wave signal exp [-j
2πnf _b / f _s3 ] is no longer necessary. In this case, the real part of the output signal x _A (nT ₃ ) of the band pass type band limiting / sampling frequency reduction device 101 shown in FIG. 4 is the desired I component I (nT ₃ ), and the imaginary part is the Q component Q (nT _3). )
Becomes The thick line indicates a complex signal.

Next, the condition for the frequency f _b in FIG. 2 to become 0 is determined.

In order that the frequency f _b becomes 0, the equation (1
From 4), the IF frequency f _IF is the output signal x _C (nT ₃ ) of the band pass type band limiting / sampling frequency reducing device 101.
It suffices if it is an integral multiple of the sampling frequency f _s3 of. Further, since the decimation ratio in the band pass type band limiting / sampling frequency reducing device 101 is an integer, the sampling frequency f _s1 in the sampler 3 is the band pass type band limiting / sampling frequency reducing device 10.
It may be an integral multiple of 2 or more of the sampling frequency f _s3 in one output.

That is, the condition that multiplication by the multiplier in FIG. 1 and the complex sine wave signal exp [-j2πnf _b / f _s3 ] is unnecessary is as follows: (1) IF frequency f _IF is desired I component, Q component _{Must be} an integer multiple of 1 or more of the sampling frequency f _s3 of.

(2) The sampling frequency f _s1 in the sampler 3 is an integral multiple of 2 or more of the desired I component and Q component sampling frequencies f _s3 , and the center frequency f of the IF signal is
₀ , where f _s1 > 2f ₀ + B when the bandwidth is B.

Thus, the IF frequency f _IF and the sampler 3
If the sampling frequency f _s1 in 1 is selected, a multiplier for multiplying the received signal by the complex sine wave signal is not required, and the circuit scale can be reduced, which is advantageous for downsizing.

Example 4. FIG. 5 is a block diagram showing the configuration of a digital quadrature detection device according to the invention of claim 4. The same components as those in FIG. 3 are designated by the same reference numerals and the description thereof will be omitted. In the present embodiment, the output signal x of the band pass type band limiting / sampling frequency reducing device 103 x
_The complex sine wave signal exp [-j2πnf _{b is} added to _C (nT ₃ ).
The multiplier 7 for multiplying / f _s3 ] is omitted.

By appropriately selecting the IF frequency f _IF , the sampling frequency f _s1 in the sampler 3, and the sampling frequency f _s2 after being reduced by the low pass band limiting / sampling frequency reducing device 102, the multiplier 7
Can be omitted.

As shown in FIG. 2, band pass type band limiting
When the output signal x _A2 (mT ₂ ) of the complex coefficient band pass digital filter 13 of the sampling frequency reduction device 103 is reduced to the sampling frequency f _s3 (= f _s2 / D ₂ ), a folded spectrum is generated. The frequency component of f _IF of x _A2 (mT ₂ ) moves by decimation, but if f _b existing in the base band −f _s3 / 2 ≦ f ≦ f _s3 / 2 is 0, the band pass in FIG. In the multiplier 7 following the type band limiting / sampling frequency reducing device 103, x _C3 (nT ₃ ) and the complex sine wave signal exp [-j
2πnf _b / f _s3 ] is no longer necessary. In this case, the real part of the output signal x _C3 (nT ₃ ) of the bandpass band limiting / sampling frequency reducing device 103 shown in FIG. 5 is the desired I component I (nT ₃ ), and the imaginary part is the Q component Q (nT _3). ). The thick line indicates a complex signal.

Next, the condition for the frequency f _b in FIG. 2 to become 0 is determined.

In order that the frequency f _b becomes 0, the equation (1
From 4), the IF frequency f _IF is the output signal x _C3 (nT ₃ ) of the band pass type band limiting / sampling frequency reducing device 103.
The sampling frequency f _s3 may be an integer multiple of 1 or more. Further, since the decimation ratio in the low pass band limiting / sampling frequency reducing device 102 and the band pass type band limiting / sampling frequency reducing device 103 is an integer, the low pass type band limiting / sampling frequency reducing device 102 has a decimation ratio. The sampling frequency f _{s2 at} the output is an integer multiple of 2 or more of the sampling frequency f _s3 at the output of the band pass band limiting / sampling frequency reducing device 103, and the sampling frequency f _{s1 at the} sampler 3 is the low pass band limiting / sampling frequency. The sampling frequency f _{s2 at} the output of the reduction device 102
2 may be an integer multiple of 2 or more.

That is, in the multiplier of FIG. 3, the output signal x _C3 (nT ₃ ) of the band pass type band limiting / sampling frequency reducing device 103 and the complex sine wave signal exp [-j2π].
nf _b / f _s3 ] is not necessary. (1) The IF frequency f _IF is an integer multiple of 3 or more of the desired I component and Q component sampling frequencies f _s3 .

(2) When the sampling frequency f _s1 in the sampler 3 is an integer multiple that is not a prime number of the desired I component and Q component sampling frequency f _s3 , and the center frequency f ₀ of the IF signal and the bandwidth are B That is, f _s1 > 2f ₀ + B.

Thus, the IF frequency f _IF and the sampler 3
If the sampling frequency f _s1 in is selected, the multiplier for multiplying the received signal by the complex sine wave signal is not required, and the signal processing can be performed at higher speed. Also,
Since the means for multiplying the received signal by the complex sine wave signal and the means for storing the complex sine wave signal generation means or the means for storing the complex sine wave signal value are unnecessary, the circuit scale can be reduced.
It is advantageous for downsizing.

Example 5. FIG. 6 is a block diagram showing the configuration of band-pass type band limiting / sampling frequency reducing devices 101 and 103 according to the invention of claim 5.

The band pass type band limiting / sampling frequency reducing device 101 is constructed by alternately connecting a plurality of band pass digital filters 21 to 2L and a plurality of decimators 31 to 3L in series. The center frequency of the pass band of the band-pass digital filters 21 to 2L is approximately the same as the center frequency of the preceding decimator output signal in the base band, and has a pass band width similar to the band width B of the received signal. Although the transition band width differs depending on the filter, it can be made wider than the single complex coefficient bandpass digital filter as shown in FIG. 1 and the complex coefficient bandpass digital filter using a decimator.

Complex coefficient band pass digital filter 21
Since the coefficient of is a complex number, its output signal is also a complex number. Therefore, in FIG. 6, the arrow indicating the signal flow after the complex coefficient band pass digital filter 21 is indicated by a thick line.

In the present embodiment, the sampling frequency is not set to 1 / D at once, but the sampling frequency is set to 1 / D by repeating the operation of band limiting and sampling frequency reduction L times. . In addition, D is an integer. If the sampling frequency to _{1 / D, D = D 1} · D 2 · ... · D when can be decomposed into a product of the L 2 or greater as _L, first the sampling frequency f _s1 Part 1 / D _{1 Is} f _s12
Then, the sampling frequency f _s12 is set to f _s13 , which is 1 / D ₂ of the sampling frequency, and the sampling frequency f _s12 is sequentially repeated L times. Note that L is an appropriate integer. Further, the integers D ₁ , D ₂ , ... In this embodiment are values different from the decimation ratios D ₁ , D ₂ in the above-mentioned embodiments ₂ , 4.

Each complex coefficient band pass digital filter 2
The word lengths of the output signals of 1 to 2 L are made longer than the word lengths of the input signals of the filters in both the real part and the imaginary part by reducing the sampling frequency. In FIG. 6, b ₁₁ ≧ b ₁ + log ₄ D ₁ , b ₁₂ ≧ b ₁₁ + log
_The bit rate is not reduced as ₄ D ₂ , .... Rather, it is desirable to make it a few bits larger than the minimum value given by these equations.

In such a configuration in which a plurality of complex coefficient bandpass digital filters and decimators are connected in series, when the decimation ratio D is large, each complex coefficient bandpass digital filter is not required to have a sharp cutoff characteristic. It has been found that the order is low, and thus the amount of calculation required for filtering can be made smaller than that in the configuration in which the single complex coefficient bandpass digital filter and the decimator shown in FIGS. 1 and 3 are connected in series.

Further, by appropriately selecting the center frequency of the complex coefficient band pass digital filter 21 of the first stage, the normalized center frequency of the complex coefficient band pass digital filters 22 to 2L of the second stage and thereafter (sampling of the input signal The center frequency normalized by the frequency) can be 0 or ± 0.5, and as a result, the digital filter 22 ...
2L can be a filter having only real coefficients, and the amount of signal processing calculation can be further reduced.

In the above embodiments, the case where the band limiting / sampling frequency reducing means formed by connecting a plurality of band pass digital filters and a plurality of decimators in series has a band pass characteristic has been described, but the present invention is not limited to this. Alternatively, the same structure can be applied to the reduction pass type low frequency band limiting / sampling frequency reducing means according to the sixth aspect of the present invention. That is, a plurality of low-pass digital filters and a plurality of decimators can be alternately connected in series.

Example 6. FIG. 7 shows claims 7 and 9.
It is a block diagram which shows the structure of the band limitation / sampling frequency reduction apparatus 101 or 103 which concerns on the invention of description.
Since the reduction devices 101 and 103 have the same configuration, only the reduction device 101 will be described.

The band-pass type band limiting / sampling frequency reducing device 101 has a switch 70 for allocating the input signal x (kT ₁ ) to the integer (D) paths 71 to 7D for each sample. Digital filters 81 to 8D are connected to the passages 71 to 7D, respectively. Further, the digital filters 81 to 8D are connected to an adder 80 as an adding means for adding the output signals of the D digital filters 81 to 8D. Incidentally, z3 is a delay operator for the sampling frequency f _s3 .

The switch 70 sequentially distributes the input signal x (kT ₁ ) of the band limiting / sampling frequency reducing device 101 sample by sample to the D paths 71 to 7D. After allocating to the passage 7D, x (k
Allocate T ₁ ). Therefore, the sampling frequency of the signal passing through the paths 71 to 7D is 1 / D of the input signal x (kT ₁ ) of the band limiting / sampling frequency reducing device 101. That is, f _s1 / D = f _s3 . Each of the digital filters 81 to 8D also operates at a speed corresponding to the sampling frequency f _s3 . Therefore, here the delay operator z
It is expressed as 3.

The input signal input timing to the digital filter 81 is earlier than the signal input timing to the digital filter 82 by T ₁ . Digital filter 8
Similarly, the signal input timing to 2 is also advanced by the digital filter 83. The same applies hereinafter. At the output of each digital filter 81 to 8D, like the input signals,
The timings of the signals in the adjacent paths are shifted by T _1. Therefore, it is necessary to add D signals by the adder 80 and output them by D.
It takes time T ₁ (= T ₃ ). Therefore, the signal x _C (nT ₃ ) whose band-limited sampling frequency is reduced can be obtained from the output of this adder.

Since the coefficients of each digital filter 81 to 8D are complex numbers, their output signals are also complex numbers. Therefore, in FIG. 7, the arrows indicating the signal flow after each of the filters 81 to 8D are drawn with thick lines. The word length (b ₃ bits) of the output signal of each of the digital filters 81 to 8D is increased by reducing the sampling frequency in both the real part and the imaginary part. That is, the bit rate is not lowered by setting b ₃ ≧ b ₁ + log ₄ D. In order to reduce the effect of rounding noise, it is desirable that b ₃ be several bits larger than the minimum value given by this equation. Impulse response p ₁ (n), p _{2 of} each digital filter 81-8D
, (N), ..., p _D (n) can be calculated from the impulse response g (k) of the complex coefficient bandpass digital filter 5 of the band limiting / sampling frequency reduction device 101 in FIG.

P _i (n) = g (nD + i−1) (i = 1, 2, ..., D) (15) The advantage of such a structure is that each digital filter 81 to
Since it is not necessary to operate 8D as fast as the sampling interval T ₁ of the input signal x (kT ₁ ) of the switch 70, it is possible to support a high sampling frequency after all.

In the above embodiment, the bandwidth limitation
The case where the sampling frequency reduction device 101 has the band pass characteristic has been described, but the low band limiting / sampling frequency reduction device 102 having the low pass characteristic according to claims 8 and 10 may have the same configuration. it can. In this case, the complex coefficient band pass digital filter is replaced with a low pass digital filter having real number coefficients. The filter output signal is a real number.

Example 7. An embodiment of the invention according to claim 11 will be described.

As shown in FIG. 3 or 5, the band pass type band limiting / sampling frequency reducing means 103 and the low pass type band limiting / sampling frequency reducing means 102 have the same internal configuration. The band pass type band limiting / sampling frequency reducing means 103
And low-pass type band limiting / sampling frequency reducing means 1
The internal structure may be different from that of 02. For example, the low-pass band limiting / sampling frequency reducing means 102 may have the same configuration as that in FIG. 6, and the band-passing band limiting / sampling frequency reducing means 103 may have the same configuration as in FIG. 7 and vice versa.

Example 8. In the above-described embodiment, the RF signal is converted into the IF signal, but depending on the sampling frequency that can be handled by the receiver or the A / D converter, the RF signal is directly converted into the digital signal and the quadrature detection processing is performed. It is also possible. In this case, the IF frequency f _{IF of the} signal is replaced with the carrier frequency f _c .

[0110]

As described above, according to the present invention, since the quantization noise is reduced in the digital quadrature detection processing, the number of quantization bits lower than the desired I component / Q component signal word length is obtained. A / D conversion can be used. In addition, it is fast and does not have many quantization bits.
High accuracy orthogonality is maintained by using the / D converter,
It is possible to easily obtain the I component and the Q component having a large signal-to-quantization noise power ratio.

Further, since the low pass band limiting / sampling frequency reducing means and the band pass type band limiting / sampling frequency reducing means are provided, the sampling frequency can be lowered to some extent in advance, and its complex coefficient band pass digital filter It is possible to relax the restriction on the characteristics of, to eliminate the need to use a complex coefficient digital filter with a narrow transition bandwidth, reduce the order of the complex coefficient bandpass digital filter, and reduce the amount of calculation and the number of components required for filtering. it can. As a result, signal deterioration due to the finite word length effect can be suppressed. Further, the filtering process in the low pass type band limiting / sampling frequency reducing means is a real number signal process, and the amount of calculation and the number of parts can be reduced.

Further, by properly selecting the IF frequency and the sampling frequency in the sampler following the IF frequency,
The multiplication of the digitized signal and the complex sine wave signal becomes unnecessary, and the signal processing can be performed at a higher speed. As a result, there is no need for means for multiplying the received signal by the complex sine wave signal, means for generating the complex sine wave signal, or means for storing the complex sine wave signal, and it is possible to reduce the circuit scale and achieve miniaturization. Further, it is possible to prevent the rounding noise from being generated.

Further, since the low pass band limiting / sampling frequency reducing means and the band pass type band limiting / sampling frequency reducing means are connected in series alternately with a plurality of digital filters and a plurality of decimators, the decimation ratio is large. In this case, a steep cutoff characteristic is not required for the digital filter, the filter order can be reduced, and thus the amount of calculation required for filtering can be further reduced. In terms of miniaturization by an integrated circuit and finite word length effect, Is also advantageous.

Then, a switch for dividing the input signal into the low-pass type band limiting / sampling frequency reducing means and the band-pass type band limiting / sampling frequency reducing means and D parallel paths connected to the respective channels. Since it is composed of various digital filters, it is not necessary to operate each digital filter as fast as the sampling interval of the input signal of the switch, and it is possible to cope with a high sampling frequency.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a digital quadrature detection device according to the inventions of claims 1 and 5.

FIG. 2 is a schematic diagram showing spectra before and after a sampling frequency of a bandpass signal is reduced.

FIG. 3 is a block diagram showing a configuration of a digital quadrature detection device according to the inventions of claims 2, 5 and 6.

FIG. 4 is a block diagram showing a configuration of a digital quadrature detection apparatus according to the invention of claim 3.

FIG. 5 is a block diagram showing a configuration of a digital quadrature detection device according to the invention of claim 4.

FIG. 6 is a block diagram showing a configuration of a band pass type band limiting / sampling frequency reducing device according to the invention of claim 7;

FIG. 7 is a block diagram showing a configuration of a band pass type band limiting / sampling frequency reducing device according to the invention of claim 9;

FIG. 8 is a block diagram showing a configuration of a conventional digital quadrature detection device.

[Explanation of Codes] 3,8 Sampler 4,9 A / D Converter 5,10,13,21 to 2L Complex Coefficient Band Pass Digital Filter 6,12,14,15,31 to 3L Decimator 7 Multiplier 11 Low Band Passing digital filter 70 Switch 80 Adder 81-8D Digital filter 101, 103 Band pass type band limiting / sampling frequency reduction device 102 Low pass type band limiting / sampling frequency reducing device

Claims (11)

[Claims] 1. Sampling means for sampling an analog band-pass signal of a received IF frequency f _{IF at} a predetermined sampling frequency and converting it into a discrete time signal, and a predetermined quantum shorter than a word length of a desired in-phase component and quadrature component. A / D conversion means for quantizing the discrete-time signal with the number of digitized bits, and band-pass type band limiting / sampling for band-passing the output signal of the A / D converting means and reducing the sampling frequency. A frequency reducing means; and a multiplying means for multiplying the output signal of the band-pass type band limiting / sampling frequency reducing means by a complex sine wave signal of a predetermined frequency. , passing the sampling frequency f _s1 of the input signal, only a predetermined frequency component of 0 <f / f _s1 <0.5 input signals Digital quadrature detection apparatus characterized by being having a bandpass characteristic to be extended from the tone of the input signal word length of the output signal of the band-pass band-limiting sampling frequency reduction means. 2. Sampling means for sampling an analog band-pass signal of a received IF frequency f _{IF at} a predetermined sampling frequency and converting it into a discrete-time signal, and a predetermined quantum shorter than a word length of a desired in-phase component and quadrature component. A / D conversion means for quantizing the discrete-time signal with the number of digitized bits, and a low-pass type band restriction for band-passing the output signal of the A / D converting means and reducing the sampling frequency. Sampling frequency reducing means, band pass type band limiting / sampling frequency reducing means for performing band limiting on the output signal of the low pass type band limiting / sampling frequency reducing means and reducing the sampling frequency; Multiply the output signal of the band-pass type band limiting / sampling frequency reducing means by the complex sine wave signal of a predetermined frequency And means, wherein the low pass band limited sampling frequency reduction means comprises a low-pass characteristic of the predetermined cutoff frequency, to extend from the word length of the input signal word length of the output signal,
The band pass type band limiting / sampling frequency reducing means, with respect to the sampling frequency f _{s2 of the} input signal,
The input signal has a band-pass characteristic of passing only a predetermined frequency component of 0 <f / _fs2 <0.5, and the word length of the output signal of the band-pass type band limiting / sampling frequency reducing means is set to the input signal. A digital quadrature detector characterized by being extended from the tone. 3. Sampling means for sampling an analog band-pass signal of the received IF frequency f _{IF at} a predetermined sampling frequency f _s1 and converting it into a discrete time signal, and a predetermined shorter than the word length of the desired in-phase component and quadrature component. A / D conversion means for quantizing the discrete-time signal with the number of quantization bits, and a band-pass type for performing band-pass band limitation on the output signal of the A / D conversion means and reducing the sampling frequency. Band limiting / sampling frequency reducing means, wherein the IF frequency f _IF is an integer multiple of 1 or more of a sampling frequency f _s3 of a desired in-phase component and quadrature component, and the analog band-pass signal is sampled to obtain a discrete time. The sampling frequency f _s1 in the sampling means for converting the signal into an analog signal is twice the center frequency of the analog bandpass signal. The value is larger than the value obtained by adding the bandwidth of the band-pass signal, and the band-pass type band limiting / sampling frequency reducing means has a sampling frequency f _{s1 of the} input signal.
The band length of the input signal is 0 <f / f _s1 <0.5, and the word length of the output signal of the band pass type band limiting / sampling frequency reducing means is A digital quadrature detector characterized in that is extended from the tone of the input signal. 4. Sampling means for sampling an analog band-pass signal of a received IF frequency f _{IF at} a predetermined sampling frequency f _s1 and converting it into a discrete time signal, and a predetermined length shorter than a desired in-phase component and quadrature component word length. A / D conversion means for quantizing the discrete-time signal with the number of quantization bits, and low-pass for performing low-pass band limitation on the output signal of the A / D conversion means and reducing the sampling frequency. Pass band type band limiting / sampling frequency reducing means, and band pass type band limiting / sampling for performing band pass type band limiting on the output signal of the low pass type band limiting / sampling frequency reducing means and reducing the sampling frequency comprising a frequency reduction means, wherein the IF frequency f _IF is an integer of 1 or more of the sampling frequency f _s3 orthogonal components and a desired phase component In it and the sampling frequency f _s1 of the sampling means for converting the analog bandpass signal sampling and discrete-time signal is an integer multiple not prime the sampling frequency f _s3 of the desired phase and quadrature components and the sampling frequency f _s1 is larger than a value obtained by adding the bandwidth of the analog band pass signal to twice the center frequency of the analog band pass signal, and the low pass band limiting / sampling frequency reducing means sets the sampling frequency f of the input signal. _With respect to _s2 , it has a band-pass characteristic of passing only a predetermined frequency component of 0 <f / f _s2 <0.5 of the input signal, and the output signal of the low-pass band-limiting / sampling frequency reducing means is A digital quadrature detector characterized by expanding the word length from the tone of an input signal. 5. The center frequency of the band pass type band limiting / sampling frequency reducing means having a bandwidth corresponding to the degree of reduction of the sampling frequency or the bandwidth of the input signal of the necessary band pass type band limiting / sampling frequency reducing means. Is equal to the center frequency or IF frequency f _{IF of the} input signal and the pass band is in a predetermined range between 0 and 1/2 of the sampling frequency of the input signal, and the output of the band pass digital filter. The decimation means for extracting the signal at every sample number according to the degree of reduction of the sampling frequency is connected in series to constitute the band pass type band limiting / sampling frequency reducing means, and the word of the output signal of the band pass digital filter is formed. The length of the input signal is extended from the word length of the input signal. The digital quadrature detection device according to any one of claims 1 to 4. 6. A low-pass digital filter having a cut-off frequency according to the degree of reduction of the sampling frequency, and decimation means for taking out an output signal of the low-pass digital filter for every number of samples according to the degree of reduction of the sampling frequency. , Are connected in series to configure the low-pass band limiting / sampling frequency reducing means, and the word length of the output signal of the low-pass digital filter is extended from the word length of the input signal. The digital quadrature detection device according to claim 2 or 4. 7. A plurality of groups are connected in parallel, and a bandpass digital filter having a predetermined bandwidth and a center frequency, and decimation means connected in series to the bandpass digital filter for taking out every predetermined number of samples are connected in parallel. 5. A band pass type band limiting / sampling frequency reducing means is constituted, and a word length of an output signal of the plurality of band pass digital filters is expanded from a word length of its input signal. A digital quadrature detector according to any one of the preceding claims. 8. A low pass digital filter having a predetermined band width and a decimation means connected in series to the band pass digital filter for taking out every predetermined number of samples, are connected in series to form the low pass digital filter. 5. The band length limiting / sampling frequency reducing means is configured, and the word length of the output signal of the plurality of low-pass digital filters is expanded from the word length of the input signal. A digital quadrature detector described. 9. The band pass type band limiting / sampling frequency reducing means reduces the sampling frequency to the reciprocal (1 / D ₂ ) of the integer (D ₂ ) of the input signal. When an attempt is made, a switch that distributes the input signal to the integer (D ₂ ) paths for each sample, a plurality (D ₂ ) of digital filters respectively connected to the integer (D ₂ ) paths, and a plurality ( D ₂ ) adder means for adding the output signals of the digital filters, and the word length of the output signals of the plurality of (D ₂ ) digital filters or the output signals of the adder means is band-pass band-limiting / sampling. The digital quadrature detection according to any one of claims 1 to 4, wherein the digital quadrature detection is extended from the word length of the input signal of the frequency reducing means. Location. 10. The low pass band limiting / sampling frequency reducing means uses the low pass type band limiting / sampling frequency reducing means as a reciprocal number (1 / D ₁ ) of an integer (D ₁ ) of an input signal. A switch for allocating the input signal to the integer (D ₁ ) paths for each sample when reducing the signal to a plurality of channels, and a plurality (D ₁ ) of digital filters respectively connected to the integer (D ₁ ) paths, multiple (D ₁₎ pieces of summing the output signal of the digital filter is composed of an adding unit, a plurality (D ₁₎ pieces of word length of the output signal of the output signal or said adding means of the digital filter is a low-pass band 5. The digital quadrature detection device according to claim 2, wherein the digital quadrature detection device is extended from the word length of the input signal of the limiting / sampling frequency reducing means. 11. The low-pass band limiting / sampling frequency reducing means reduces the sampling frequency of a low-pass digital filter having a cutoff frequency corresponding to the degree of reduction of the sampling frequency and an output signal of the low-pass digital filter. The decimation means for extracting every sample number according to the frequency is connected in series, and the decimation means for extracting every predetermined sample number connected in series to the low-pass digital filter of the predetermined bandwidth and the band-pass digital filter is connected. A plurality of sets are connected in series, or when the low-pass band limiting / sampling frequency reducing means tries to reduce the sampling frequency to the reciprocal (1 / D ₁ ) of the integer (D ₁ ) of the input signal. Switch that distributes each sample to an integer (D ₁ ) passage, an integer (D ₁ ) A plurality of (D ₁ ) digital filters and a plurality of (D ₁ )
₁ ) Addition means for adding the output signals of the digital filters, and the band pass type band limiting / sampling frequency reducing means is a means for reducing the sampling frequency or the required band pass type band limiting / sampling frequency reducing means. It has a bandwidth corresponding to the bandwidth of the input signal, the center frequency of the band-pass type band limiting / sampling frequency reducing means is equal to the center frequency of the input signal or the IF frequency f _IF , and the pass band is 0 to the sampling frequency of the input signal. The band pass digital filter existing in a predetermined range between ½ of and the decimation means for extracting the output signal of the band pass digital filter at every sample number according to the degree of reduction of the sampling frequency are connected in series. Bandpass digital filter with a bandwidth and center frequency of Constituted by connecting a decimation means for retrieving a predetermined number of samples every connected in series to pass digital filter to the plurality of sets in series, or band-pass band-limiting sampling frequency reduction means integral of the input signal sampling frequency (D ₂ ) Switch to divide the input signal into integer (D ₂ ) channels for each sample when it is reduced to the reciprocal (1 / D ₂ ), and a plurality (D ₂ ) respectively connected to the integer (D ₂ ) channels. 5. The digital quadrature detection device according to claim _{2, further} comprising: ₂ ) number of digital filters and addition means for adding output signals of a plurality of (D ₂ ) number of digital filters.