NL194632C - Subscriber unit for a wireless digital telephone communication system. - Google Patents

Description

1 194632

Subscriber unit for a wireless digital telephone communication system

The invention relates to a subscriber unit for a wireless digital telephone communication system, wherein the subscriber unit comprises coding / decoding means and an associated processing unit for recoding an input signal to provide digital input symbols, FIR means which respond to the processing unit for providing FIR filtered digital input symbols, a radio unit for sending a signal comprising the information contained in the FIR filtered digital input symbols, to a second unit within the system and for demodulating a received from the second unit output signal, and wherein the processing unit assembles digital output signals from the demodulated output signal.

Such a subscriber unit is known from U.S. Pat. No. 4,825,448.

The known subscriber unit comprises a baseband processor chip and a modem processor chip. The baseband processor chip performs the recoding of the digital speech input signal including the coding and decoding function, the synthesis of the digital output symbols and various baseband control functions. The modem processor chip further performs filtering of the digital input symbols based on finite impulse response (FIR filtering) and demodulation of the output signal received from a second unit within the system. The modem processor chip generally acts as the main controller of the system.

The known subscriber unit works in an analog environment. The fixed mid-frequency signal is analogously modulated and later combined with a variable radio-frequency signal.

The invention has for its object to provide a subscriber unit of the type mentioned in the preamble, which is less expensive.

This object is achieved according to the invention in that the FIR means are realized as an FIR chip, which comprises: means for internal address decoding to enable the processing unit to access internal functions of the FIR chip; control and status registers that allow the processing unit to read the status of the FIR chip and control its internal functions; said means for filtering with finite impulse response of the digital input symbols; and means for controlling the timing that allow the processing unit to control the FIR filter means.

According to the invention, the intermediate frequency signal is digitally modulated and later combined with a fixed radio frequency signal. For this purpose, according to the invention, a separate FIR filter chip is provided, which performs the FIR filtering, which filtering according to the state of the art is implemented by software in the modem processor. By removing the time-consuming FIR filtering from the modem processor and by performing the demodulation function with the same processor that performs the baseband processing function, only one processor chip is needed. According to the invention, therefore, a unique individual FIR chip is provided which performs the necessary functions for FIR filtering.

Additional features of the present invention are described with respect to the description of the preferred embodiment.

The invention will be further elucidated with reference to the drawing, in which: figure 1 is a block diagram of a preferred embodiment of the subscriber unit according to the present invention; Figure 2 is a block diagram of the FIR chip which is part of the embodiment shown in Figure 1; Figure 3 is a block diagram of the DIF chip which is part of the embodiment shown in Figure 1; Figure 4 illustrates the processing tasks performed by the processor chip shown in the embodiment of Figure 1; Figure 5 illustrates the processing routines that are part of the modem processing task shown in Figure 4.

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The following is a definition of abbreviations and acronyms used in this text: A / D analog to digital 5 AGC automatic gain control ASIC application-specific integrated circuit BPSK binary phase shift modulation CCT channel control task CCU channel control unit CRC cyclic redundancy check DAC digital-to-analog converter DDS direct digital synthesizer

Dl F digital center frequency DIP dual in-line housing DOR data output ready DPSK differential phase shift modulation DSP digital signal processing EPROM erasable read-out memory

Flr finite impulse response I / O input / output LSB least significant bit MPT modem processing task MSB most significant bit MUX multiplexer 25 PCM pulse code modulation PLL phase lock loop PWM pulse width modulation QPSK quadrature phase shift modulation RAM random access memory RCC radio control channel RELP residual excised linear RF RF RX receive RXCLK receive clock signal RXSOS receive start or slot SCT subscriber control task SLIC subscriber line interface circuit SPC signal processing control SPT signal processing task SPTCTL signal processing task controller SSB transmit switch sample buffer TDM time division multiplexing TX transmit TXCLK transmit X-ray universal-axis X-axis X-axis X-axis X-ray universal X-axis V-axis X-axis universal circuit 50 With reference to Figure 1, a preferred embodiment of the subscriber unit according to the present invention comprises a telephone interface 10, a SLIC as well as codec circuit 11, a processor chip 12, a fast memory 13, a slow memory 14, an address decoder 15, an FIR chip 16, a DIF chip 17, a DAC 18, an A / D converter 19 , a radio 20, a bell circuit 21, and an oscillator 22.

55 The FIR chip 16, which is an ASIC chip, is coupled to the DIF chip 17 by lines 23 and 24, to the processor chip 12 by means of processor bus 25 and line 26, to the A / D converter 19 through line 27, at the LSIC and the codec circuit 11 through line 29, at the radio 20 through line 30, and at the bell circuit 21 through line 31.

The telephone interface circuit 10 is coupled to a telephone 32, which converts sound waves into a speech input signal, and converts a speech output signal into sound waves.

The SLIC and the codec circuit 11 are coupled to the telephone interface circuit 10 for converting the speech input signal into a digital baseband input signal which is applied to the processor chip 12.

In another embodiment (not shown), the processor chip is also directly coupled to a UART for otherwise receiving digital input signals directly from, and for transmitting digital output signals directly to, a digital I / O signal device.

The processor chip 12 comprises a digital signal processor of the type NMS320C25, which recodes the digital baseband input signal in accordance with a RELP algorithm, in order to provide data to be transmitted, in the form of digital input symbols on the processor bus 25. The use of a Digital signal processor for performing a RELP algorithm is described in International Patent Application No. PCT / US 85/02168, international publication number WO86 / 02726, published May 9, 1986.

The FIR chip 16 subjects the digital input symbols to FIR filtering and provides 1.Q data to the DIF chip 17 via lines 24.

The DIF chip 17 interpolates the filtered digital input symbols and modulates a digital mid-frequency signal with the interpolated input symbols to provide a modulated digital input signal.

The DAC 18 converts the modulated digital input signal into a modulated analog input signal.

The radio 20 transmits the modulated analog input signal to the base station; and receives and demodulates a modulated analog output signal from the base station.

The oscillator 22 is a free-running oscillator, which provides clock signals to the processor chip 12.

A description of the relationship between the subscriber unit and the base station is described in U.S. Patent No. 4,777,633.

The A / D converter 19 converts the demodulated received analog output signal into a digital output signal containing digital output symbols; The processor chip 12 generates a digital baseband output signal from the digital output symbols by means of synthesis. Synthesis of RELP-recoded symbols by means of a digital signal processor is also described in international publication number WO86 / 02726. The processor chip 12 further performs echo cancellation as described in U.S. Patent No. 4,697,216.

The SLIC and the codec circuit 11 convert the digital baseband output signal into the speech output signal provided by the telephone interface circuit on the telephone 32.

The FIR chip 16 consolidates the functionality of a circuit in a VLSI device in order to reduce the production costs of the subscriber unit by eliminating many individual, medium-integrated components.

40 Referring to Figure 2, the FIR chip 16 comprises a multi-loadable buffer 33, an internal decoding module 34, a receive sample buffer 35, control and status registers 36, an external address decoding module 37, a monitoring time control module 38, a receive time control module 39, a transmit timing module 40, an FIR transmit filter 42, a codec timing module 44, and a call control module 45.

45 The FIR chip 16 provides generation of a 45 millisecond frame marking signal, generation of a 11.25 millisecond slot marking signal, generation of a 16 kHz symbol clock signal, time correction circuits, receive sample buffering, generation of an 8 kHz codec time control signal, processor interface decoding, call timer generation, external address decoding, and generation of a reset signal for the monitoring timer. The FIR chip 16 buffers two 5-bit transmission symbols 50 at a speed of 8 kHz. The FIR chip 16 provides conversion and filtering of the transmission symbols into I and Q data symbols, each of these symbols having a width of 10 bits and the speed being 160 kHz. The I and Q data are interwoven and output to the DIF chip 17 at a speed of 320 kHz. The FIR chip 16 also buffers receive data samples at a speed of 64 kHz; and four receive data samples are read by the processor chip 12 at a speed of 16 kHz. Time control 55 clock signals as well as time control signals are generated by the FIR chip 16 from an incoming master clock signal of 3.2 MHz. The processor chip 12 is synchronized at these data rates by means of slot and symbol interrupts generated by the FIR chip 16. The 8 kHz strobe of the codec and the processor 8 as well as the codec clock signal are generated by the FIR chip 16 and synchronized with the time of the incoming receive samples. The FIR chip 16 also generates control and timing signals for controlling the shape and timing of the ring voltage provided by the ring circuit 21. The monitoring timing module 38 provides a reset signal in the event that the processor chip 12 does not receive the instructions in an appropriate manner.

The multi-loadable buffer 33 buffers a 3.2 MHz master clock signal received on line 23a of the DIF chip 17, a 3.2 MHz advanced clock signal received on line 23b of the DIF chip 17, and a reset signal which is received on line 51 of the monitoring timer 38. Unless otherwise indicated, all timing within the FIR chip 16 is derived from the 3.2 MHz clock signal on line 23a. The forwarded 3.2 MHz clock signal on line 23b is ahead of the 3.2 MHz clock signal on line 23a with a cycle of a reference signal of 21.76 MHz present within the DIF chip 17. The clock signal of 3.2 MHz is derived from the reference of 21.76 MHz in the DIF chip 17 and the minimum pulse width is therefore 276 nanoseconds. The forwarded 3.2 MHz clock signal from line 23b is provided from the buffer 33 via internal line 47 to the FIR transmit filter 42, and the code timing module 44. The FIR transmit filter 42 is implemented, at least in part, by means of a ROM which is pseudo-static and requires its activation input to be deactivated by the 3.2 MHz forward clock signal on line 47 between successive accesses.

The HW reset signal on line 51 resets all internal circuits of the FIR chip 16 and provides a hardware reset to the modules of Figure 1.

The internal clock signals are either buffered versions of the 3.2 MHz master clock signal received on line 23a or divisions of this clock signal.

The internal address decoding module 34 allows the processor chip 12 to access the internal functions of the FIR chip 16 for controlling these functions and determining their status. The internal address decoding module 34 receives processor addresses and processor strobe signals on bus 25. The internal address decoding module 34 provides output signals on internal bus 48.

The output signals on bus 48 of the internal address decoding module 34 include a read activation signal at the receive sample buffer 35, a control write signal as well as status read signals at the control and status registers 36, a write signal at the FIR transmit filter 42, slot and clock write signals 30 at the receive time control module 39, a write signal at the send time control module 40 and control signal at the FIR send filter module 42 and the receive sample buffer 35, as well as an AM strobe signal, which causes the receive time control module 39 to reset the slot time control. Only one of the respective read or write signals on bus 48 of the internal address decoding module 34 is active at a given time.

The receive sample buffer 35 receives four samples for each receive symbol time from the A / D converter 35 via line 27a at a speed of 64 kHz; buffers a maximum of two data symbols, which is a total of eight samples; and then send these data samples to the processor chip 12 via the processor bus 25. The receive sample buffer 35 is implemented by means of a dual-page RAM. The receive sample buffer 25 receives a read activation signal on internal bus 48 of the internal address decoding module 34 and a write strobe signal on internal line 49 of the receive time control module 39.

The control and status registers 36 allow the processor chip 12 to control the internal function of the FIR chip 16, and allow the processor chip 12 to read the status of the FIR transmit filter 42 and the receive sample buffer 35, as well as other internal signals. The control signals are provided by the processor chip 12 via the processor bus 25 and the status indications are derived from various internal modules of the FIR chip 16. The status indications are provided to the processor chip 12 via the processor bus 25. 45 The status indications are received underloaded, received overloaded , transmission underloaded, transmission overloaded, start-of-frame, reception of slot start, transmission symbol clock signal, reception symbol clock signal, and capacity overrun of FIR transmission filter.

The control signals provided by the control registers 36 to the internal circuits via the internal bus 48 include the following: transmit trigger signal, modulation level, ringer trigger signal, 50 software reset signal, three-state signal, and monitoring strobe signal.

The transmit activation signal gives the start of a transmit slot based on the transmit delay determined in the transmit time control module 40.

The modulation level signal is provided to the receive timing module 39 and determines whether a slot length is 180 or 360 symbols.

The software reset signal allows the processor chip 12 to reset internal functions within the FIR chip 16.

The three-state signal allows the processor chip 12 to deactivate the outputs of the FIR chip 16.

The ringer activation signal allows the processor chip 12 to switch the ring circuit 21 on and off. This signal provides a cadence of two seconds and four seconds to the ring signal.

The monitoring strobe signal allows the processor chip 12 to reset the monitoring timing module in order to prevent the occurrence of a hardware reset.

The processor chip 12 receives a receive clock interrupt (RXCLKINT) signal from the receive timing module 39 via line 26c when data is written in the first four locations of the dual page RAM of the receive sample buffer 35. The processor chip 12 then reads the receive samples from the first four locations of the dual-page RAM via processor bus 25. At this time, samples are written in the following four locations of the dual-page RAM at a speed of 64 kHz. The 16 kHz event is a derivative of the 64 kHz event, which keeps the read and write events in synchronization. This ensures that read and write operations do not occur simultaneously at any memory location and also ensures adequate response time of the processor chip 12.

A transmit symbol buffer in the FIR transmit filter 42 receives transmit symbols from the processor chip 12 via the processor bus 25 and buffers up to two transmit symbols. The processor chip 12 receives an interrupt every other transmission symbol time for writing two more symbols into the transmission symbol buffer.

The transmit symbol buffer in the FIR transmit filter 42 receives a write signal via the internal bus 48 of the internal address decoding module 34.

After each transmit clock signal interrupt (TXCLKINT) at 8 kHz on line 26a, processor chip 12 writes out two 5-bit 20 transmission symbols. The data has a DPSK gray code format. The transmit symbol buffer produces a symbol for processing by the FIR transmit filter 42 every 16 kHz. This data is buffered twice as a result of an asynchrony between the FIR chip 16 and the processor chip 12. The last data value is repeated until new data is written. Zero data can be repeated in this way. The transmit symbol buffer is emptied during a reset.

During a training, a fixed sequence of symbols is sent to the FIR chip 16 by the processor chip 12. The FIR chip 16 performs FIR filtering on these symbols and sends 1, 4 pairs to the DIF chip 17.

The radio 20 loops the data back to the A / D converter 19. The samples are read by the processor chip 12 such as during the on-line mode and the coefficients of the processor receive filter 30 which are implemented in the processor chip 12 , be adjusted. The only timing that is critical to the training is generated by the receive and transmit timing modules 39, 40.

The receive time control module 39 generates all reference clock signals and strobe signals for processing the receive symbols. The timing is adjusted by the processor chip 12 in such a way that the processing can be synchronized with the receive samples received via line 27a of the base station. The receive timing module 39 includes a fractional receive clock signal timing circuit and a receive slot timing circuit. The purpose of these two circuits is to synchronize the receive time control of the modem within the processor chip 12 with the receive samples received on line 27a of the base station, and via the A / D converter 19, and also regulate the send time control module 40 and the code time control module 44.

40 The receive time control module 39 receives clock control at a speed of 3.2 MHz and receives the following control signals from the processor chip 12 via the processor bus 25: an AM strobe signal, a receive slot clock write signal, and a receive bit follow signal.

Various output signals are generated by the receive time control module 39. A 64 kHz write strobe is provided on line 49 to control write to the receive sample buffer. An A / DSYNC strobe signal of 64 kHz is provided on line 27b to the A / D converter 19 to synchronize its operation. An 8 kHz strobe signal is also provided to the codec timing module 44 via line 52. A 16 kHz receive clock interrupt signal (RXCLKINT) on line 26c and a start of receive clock interrupt signal (RXSOSINT) on line 26b are applied to the processor chip 12 A receive slot lead-in time control strobe is provided on line 54 to control the 50 transmit time control module 40.

The fractional timing circuit in the receive time control module 39 is set by the processor chip 12 to generate the initial receive slot interrupt signal on line 26b. The processor chip 12 determines the location of an AM hole (strobe signal) that is transmitted by the base station during acquisition. When the processor chip 12 detects the AM strobe signal, the slot 55 time control circuit in the receive time control module 39 is reset by a reset signal from the processor chip 12. This synchronizes the frame and the slot marker signals with the AM strobe signal. The frame marker is a 62.5 ps pulse that occurs every 45 milliseconds.

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The incoming receive symbols are demodulated by the processor chip 12 and the timing is further adjusted if necessary. To adjust the 16 kHz receive symbol clock, the processor chip forces the fractional timing (bit-follow) circuit to shorten or extend the 64 kHz strobe signal by up to fifty 3.2 MHz periods.

The processor chip 12 monitors the relationship of the receive symbols with the frame timing and performs adjustments of the 16 kHz receive clock signal accordingly. When the receive clock is adjusted, the slot and frame marking signals are also changed because they are derived from the receive clock signal. In order to keep the number of pulse code modulated (PCM) samples going to and from the SLIC and the codec circuit 11 synchronized with the frame time control, the receive time control module 39 controls the code time control module 44.

The transmit time control module 40 includes a transmit delay circuit and a transmit control timer circuit. These circuits generate a transmit clock interrupt signal (TXCLKINT) that is provided to the processor chip 12 via line 26a. The transmit time control module 40 is synchronized with the receive time control module 39 by the receive slot lead-time control strobe, which is provided to the transmit time control module by the receive time control module 39 on line 54 and is used to reset the transmit delay flag circuit, which in turn generates the transmit slot marking signal. The timing of the transmit clock signal is based on the internal clock signal of 3.2 MHz.

The processor chip 12 also controls the transmit delay as well as the transmit time control circuitry by providing a transmit data write control signal via the processor bus 25.

The transmit time control module 40 provides a transmit / receive control signal on line 30 to the radio 20. This signal determines whether the radio transmits or receives data.

The transmit time control module 40 also controls the transmit symbol shift, ROM addressing, accumulation time control, and I, Q product storage for supply to the DIF chip 17.

The transmit time control module 40 provides control signals on line 56 to keep the FIR transmit filter 42 synchronized with the transmit symbol and slot timing. This synchronization is achieved in accordance with the transmit slot timing marker signal. After a reset, the transmit time control module 40 actively produces control signals on line 56 as soon as a transmit slot begins.

The FIR transmit filter module 42 includes a ROM that implements an FIR filter by providing I and Q data products in response to addressing the ROM for lookup, by a combination of transmit symbols received from the processor chip 12 via the processor bus 25 as well as SINUS and COSINUS coefficient counts provided by a counter within the FIR transmit filter module 42. The FIR transmit filter 42 accumulates six sequential I and Q data products and stores results for output to the DIF chip 17 via line 24a.

The minimum frequency required for operation of the FIR transmit filter 42 is determined by the symbol rate (26 kHz) multiplied by the number of I and Q samples (2) multiplied by the number of coefficients (10) multiplied by the number taps (6) = 1.92 MHz. The main clock signal of 3.2 MHz meets this minimum frequency requirement. Waiting periods are added to provide compensation for the faster execution time.

The transmit time control module 40 is controlled with a clock speed of 3.2 MHz, which defines a cycle period 40. Because this clock speed is greater than the required minimum of 1.92 MHz, the FIR transmit filter 42 generates signals for the first six of the ten cycle periods.

Each new transmission symbol must be loaded into a circular buffer in the FIR transmission filter 42 at the speed of 16 kHz. The new transmission symbol and the previous five transmission symbols are stored in the revolving buffer. The oldest transmission symbol is deleted when a new transmission symbol is supplied. The FIR transmit filter 42 has an output speed of 320 kHz. Of each transmission symbol, ten l data values are generated and ten Q data values. Table 1 (see below) shows how I and Q as well as zero information can be derived from each 5-bit value.

TABLE 1 50 ----- BIT 1 BIT2 BIT3 BIT4 BIT5

I and Q LSB I and Q I MSB Q MSB ZERO

The data in the circulating buffer is rotated at 6 of every 10 cycles. A new transmission symbol and the five previous transmission symbols reside in the circulating buffer for twenty of these periods of 55 7 19 'ten cycles. The coefficient portion of the ROM address is also increased at six of the ten cycle periods. An accumulator in the FIR transmit filter 42 adds up the results of each 1-data product provided by the ROM for each of the six cycle periods. Therefore, the accumulator register is released for the first addition, and each successive addition is placed under clock control in a feedback register of the accumulator so that it can be added to the recently requested product. As soon as six additions have been made, the result is sent to an output shift register under clock control. The same process occurs for the same coefficients and the Q data products provided from the ROM for each transmission symbol.

The ROM address lines allow for looking up sixty COS coefficients and sixty SIN coefficients for four possible I · Q data indexes.

This requires seven address lines for coefficients and two address lines for I, Q data. The output signal from the FIR filter requires 10 bits. Two additional bits are required to maintain the accuracy of the fractional portion of the searched-up value. This results in a ROM size of 512 x 12. The MSB of the I, Q data index is passed around the ROM to a 1-complement circuit which forces the output signal of the ROM to be inverted or not to be inverted.

If the symbol addressing the ROM is a zero symbol, the zero bit controls four of the seven coefficient address lines. Because seven address lines are used to look up the coefficient, this provides 128 locations. Only 120 coefficients are required. Therefore, eight unused locations are left. Zero values are stored in these locations so that zero information can easily be output from the ROM.

A 2 complement function is implemented by using a 1 complement and passing a logical 1 to the next adder. The output signal from the adder is fed back to the input of the adder for successive additions or output via a multiplexer to an output shift register. The output is rounded off using only the ten higher bits. The outputs of the circulating buffer of the FIR transmission filter are set to zero after a reset.

This allows zero information to be processed until new transmission symbol values are loaded, 1 data is first processed followed by Q data.

The transmit clock interrupt signal only occurs during a transmit slot. The processor does not know when a transmission slot starts or ends except by responding to this interrupt. The signal has an active duration at logic zero of a 3.2 MHz clock period to ensure that the interrupt is not active once it has been processed. The transmit clock interrupt occurs every other symbol time (16 kHz / 2).

The receive clock occurs during a full frame. The processor chip 12 masks this interrupt by using the receive slot marking signal as a mask. The receive clock interrupt has an active duration at logical zero of a clock signal of 3.2 MHz.

The transmit slot start interrupt occurs every 11.25 milliseconds, and has an active duration at logic zero of a period of the 3.2 MHz clock signal.

Each interrupt signal is forced to assume an inactive state of logic "1" when resetting.

The coding timing module 44 generates timing control probes and sends the necessary clock signal via lines 29 to the SLIC and the codec circuit 11 to cause eight data bits to be transmitted between the codec and the processor at a speed of 8 kHz. The codex 11 receives and sends 8 data bits every 8 kHz. The coding time control module 44 sends a code clock signal via line 29a and a codec sync signal via line 29b. The code clock signal on line 29a is generated at a speed of 1.6 MHz by dividing the forward-shifted clock signal of 3.2 MHz by two. An 8 kHz pulse of a 3.2 MHz period is received from the receive time control circuit 39 and is clocked again so that it occurs for a period of 1.6 MHz, so that it is ensured that it occurs with respect to the rising edges of the clock signal of 1.6 MHz. With these two signals, transmission of the PCM data between codec 11 and the processor chip 12 is realized. This allows the subscriber PCM data 50 to be synchronized with the PCM data of the base station.

The bell control module 45 responds to a bell activating control signal from the processor chip 12 and is supplied from the control and status register 36 to internal bus 48 by generating a 20 Hz square wave signal on line 31 as well as two 80 kHz phase control signals , PHASEA on line 31b and PHASEB on line 31c and sending these signals to the ring 55 circuit 21. The 20 Hz square wave signal on line 31a controls the polarity of the ring voltage provided by the ring circuit 21 to the telephone interface circuit 10. The 80 kHz phase signals on lines 31b and 31c control the pulse width modulated power source in the bell circuit 21. A 194632 8 reset or an SLIC bell command signal on line 29c of the SLIC portion of the SLIC and codec circuit 11 makes these signals switching off or being ignored on lines 31a, 31b and 31c after the bell activation signal from the processor chip 12 has turned it on. This ensures that the caller is switched off if a reset occurs or the telephone's handset is lifted off the hook.

Because the bell circuit 21 generates a high voltage and dissipates a lot of power, this voltage is not generated except when the processor chip 12 requests this.

The external address decoding module 37 generates chip selection signals on the processor bus 25 which are used by the processor chip 12 to gain access to the DIF chip 17. The UART-10 hardware, and the slow memory EPROMs 14 in separate distinct address segments. The processor chip 12 provides eight MSB address lines, data space and program space signals. These are decoded to generate the appropriate chip selection signals.

The monitoring timer 38 generates a 50 millisecond hardware reset pulse on line 51, which resets all modules on FIR chip 16 and all subscriber unit modules in Figure 1. The monitoring timer 38 generates a pulse if it is not reset within a period of 512 milliseconds by the monitoring strobe signal provided on bus 48 by the control and status registers 36.

The DIF chip 17 is coupled to the processor chip 12 by the processor bus 25, to the FIR chip 16 by lines 23 and 24, to the DAC 18 by line 71 and to an oscillator in the radio 20 by line 72.

The oscillator in the radio 20 provides a main clock signal of 21.76 MHz on line 71 to the DIF chip 17.

Referring to Figure 3, the DIF chip 17 includes a clock generator 60, a processor decoder module 61, an FIR chip interface module 62, an interpolation device 63, a control register 64, tuning registers 65, a DDS phase accumulator 66, a DDS SIN and COS generating module 67, and a noise shaper 69. In combination, the DDS phase accumulator 66 and the DDS SIN, COS generator 67 form a direct digital synthesizer (DDS) for digitally generating by synthesis of a digital medium frequency signal.

The DIF chip 17 is an ASIC chip, which is arranged as processor data memory.

The DIF chip 17 operates according to one of two operating modes, a mode in which a modulated carrier is generated, and a pure carrier mode. In the modes in which a modulated carrier is generated, baseband data is input to the I, Q domain and this data is used to modulate the pure carrier that is generated by the DDS function of the DIF chip 17. In the mode where the pure carrier is generated, the baseband data inputs are ignored and a non-modulated carrier of the DDS is provided to the DAC 18.

The clock generator 60 generates all timing signals and clock signals within the DIF chip 17 and also generates the 3.2 MHz clock signal as well as the advanced 3.2 MHz clock signal which signals are applied to the FIR chip 16 on Lines 23a and 23b. The two primary timing signals used within the DIF chip 17 are a clock signal of 21.76 MHz and an interpolation port signal of 2.56 MHz. The 3.2 MHz clock signal is used internally for shifting I and Q data on line 24a from the FIR chip 16 to the FIR interface module 62.

The clock generator 60 buffers the 21.76 MHz clock signal received on line 72 of the oscillator in radio 20 and provides a buffered clock signal of 21.76 Mhz on line 71a. This buffering is performed to provide sufficient control capacity for internal functions and to minimize distortion of the clock signal. The buffered clock signal of 21.76 MHz also provides a clock signal for the DAC 18 and other external circuits.

The clock generator 60 provides the clock signal of 3.2 Mhz by dividing the clock signal of 21.76 MHz by 6 and by 8 according to the following sequence: 6-8-6-8-6, thus resulting in an average dividing factor of 6.8 (21.6: 6.8 = 3.2). The effect of this variation per period is a minimum period of 276 nanoseconds and a maximum period of 368 nanoseconds. A forward-shifted version of the 3.2 MHz clock signal is also generated as the forward-shifted 3.2 MHz clock signal 50 on line 23b. Both clock signals are identical except that the ROM deselect signal on line 23b is ahead of the 3.2 MHz clock signal on line 23a with a 21.76 MHz clock cycle.

The clock generator 60 provides the 2.56 MHz gate signal on internal line 74 by dividing the 21.76 MHz clock signal by 8 and by 9 in an equal series (8-9-8-9 -...), which therefore results in an average division factor of 8.5 (21.76: 8.5 = 2.56 MHz). This signal is used by the interpolator 63 and 55 the modulator 68.

The processor decoding module 61 allows the processor to control all internal functions of the DIF chip 17. The processor decoder module 61 decodes processor addresses and processor probe signals received from data space on the processor bus 25 to provide internal write probe signals, which are provided on internal bus 76 to the control register 64 and the tuner registers 65 to enable the processor chip 12 write control and configuration data. Only one output signal from the processor decoder module 61 is active at a given time. The processor addresses determine which output signal is generated. If a function within the address space of the DIF chip 17 is selected, a chip selection signal on line 24c of the FIR chip 16 becomes active.

The FIR interface module 62 receives the I and Q samples from the FIR chip 16 on line 24a in a serial format and converts them into a 10-bit parallel format in which they are provided to the interpolator module on line 77. The I- Q gate signal on line 24b of the FIR chip 16 is used to distinguish the 1 data from the Q data. The FIR interface module 62 also subtracts previous I and Q samples from current samples to form ΔΙ and AQ samples which are then shifted four places to the right (: 16) to form the correct incrementation for the interpolator module on line 78. Because the FIR interface module 62 provides data to the interpolator 63, a synchronization signal is sent by the FIR interface module 62 to the clock generator 60 to synchronize the 2.56 MHz gate pulse provided on line 74.

The interpolator 63 accumulates the Al, AQ at a rate of 160 kHz x 16 = 2.56 MHz and provides interpolated I and Q samples to the modulator 68 on lines 80 and 81, respectively. The interpolator 63 performs an x16 linear interpolation to reduce of the 160 kHz sampling rights that are present in the baseband data received from the FIR chip 16.

The interpolator 63 successively accumulates the Al and AQ samples to generate an output signal at a speed of 2.56 MHz. At the end of an accumulation cycle (16 repetitions), the output signal of the interpolator must be equal to the flow of I and Q samples. This is critical because the next accumulation cycle starts its cycle with the current data. In order to ensure that the data is correct, during the last accumulation cycle the current I and Q data are directly input into the output registers of the interpolator instead of the output signal of the adder (which must contain the same data).

The control registers 64 are used to control and configure the DIF chip 17 and to select the operating modes. All control registers 64 are loaded by the processor chip via the processor bus 25.

There are three control registers 64. The first control register registers a CW MODE signal, an AUTO TUNE H-L signal and an AUTO TUNE L-H signal. The second control register registers a SIGN SELECT signal, an OUTPUT CLOCK PHASE SELECT signal, an INTERPOLATOR ENABLE signal, a SERIAL PORT CLOCK SELECT signal, a SERIAL / PARAL-LEL MODE SELECT signal and a QUADRATURE ENABLE signal. The control functions associated with these signals are described later in the conclusion of the description of the other modules of the DIF chip 17.

The third control register activates and specifies the coefficients for the noise shaper 69.

There are three 8-bit tuning registers 65 for storing 24 bits of phase incrementation data for specifying the frequency of the DDS. This provides a 24-bit tuning word that allows a frequency resolution of (sampling frequency) / 224 = 21.76 MHz / 224 = 1.297 Hz. The output frequency of 40 the DDS is equal to the resolution multiplied by the 24-bit tuning word.

The tuning registers 65 are loaded by the processor chip 12 via the processor bus 25. The tuning word is double buffered by the tuning registers 65 so that the processor chip 12 can freely write data to these registers without affecting the current DDS operation.

The tuning word is loaded from buffer tuning registers to output tuning registers whenever 45 a TUNE command is issued. The TUNE command is synchronized with the 21.76 MHz clock signal to provide a synchronous transition.

The DDS phase accumulator 66 performs a phase incrementation modulo 224 accumulator provided on line 82 by the tuning registers 65. The output signal of the phase accumulator 66 represents a digital phase value provided on line 83 to the DDS SIN and COS generator 67.

50 The DDS SIN and COS generator 67 generates a sinusoidal function. A DDS works on the principle that a digitized waveform can be generated by accumulating phase changes at a higher speed.

The tuning word, which will be different with different subscriber units, represents a phase change for the phase accumulator 66. The output signal of the accumulator 66 can be 55 in a range of 0 to 224-1. This interval represents a phase change of 360 °. Although the accumulator 66 operates in the standard binary mode, this digitized phase display can be input to a waveform generator to generate a random waveform. In the DIF chip 17 194632 10, the DDS SIN and COS generators 67 produce SIN and COS functions on lines 84 and 85, respectively.

The period of the waveform function is based on the time required to perform a summation up to the higher limit of the accumulator (224-1). This means that if a large phase incrementation is provided, this limit will be reached sooner. Conversely, if a slight incrementation is given, a longer time will be required. The phase accumulator 66 performs a simple summing of the input phase incrementation and can be represented by the following equation: Φτ = ΣΦΐικ 0) l = 1 where m is the number of repetitions, and φίη (: simply represents the data supplied on line 82 10 from the reconciliation registers 65.

In the embodiment of the DIF chip 17 described, the value of φτ is limited by the length of the accumulator to a maximum of 254. Therefore, the flow phase can be described as: Φ = (ΦΜ + Φΐηο) ηιθ £ ΐυΙθ224 ( 2)

Because the accumulator clock is designated as the input main clock signal of 21.76 MHz, therefore, a complete cycle 224 / ηίηε has a repetition period of 1 / 21.76 MHz. Therefore, the entire cycle takes the following amount of time: f 224 'dds - 21.76ΜΗζ.φΙη <.

Because this period represents a 360 ° cycle, the reciprocal of this formula represents a frequency. The DDS frequency is therefore: 21.65 ΜΗζ.φΙηο

'DDS - ^ 24 W

In the DDS SIN, COS generation module 67, the SIN and COS waveforms were generated so that a complex mixing can be performed in the modulator. Each of the two is generated by two look-up tables, which represent a rough and a fine estimate of the waveforms. The two values are summed to form composite 12-bit 2-complement SIN and COS data output with sign value on lines 84 and 85. The look-up tables are implemented in ROMs that are addressed by the fourteen most significant bits of the signal on line 83 of the DDS phase accumulator 66.

It is desirable to have as much phase and amplitude resolution as is practicable. In the design of the DIF chip 17, a 14-bit phase input signal and a 12-bit amplitude data output signal are provided in the waveform generating section. If an approach based on pure processing power were chosen to generate this data, very large tables would be needed to generate all possible phase and amplitude values (for example, 16 K words x 12 bits each). In order to minimize the size of the table, the DIF chip 17 uses quadrant symmetry and trigonometric decomposition of the output data.

Because SIN and COS waveforms have square symmetry, the two most significant bits of the phase data are used to mirror the single quadrant data around the X and Y axes. For the SIN 40 function, the amplitude of the wave in the π to 2π interval has exactly the negative value of the amplitude in the 0 to π interval. For the COS function, the amplitude of the wave in the π / 2 to 3π / 2 interval is exactly the negative value of the amplitude in the 3π / 2 to π / 2 interval. Two MSBs of the phase accumulator specify the quadrant (00—> 1, 01- »2.10-> 3, 11-» 4). For the SIN function, the MSB of the phase data is used to deny the positive data generated for the first two quadrants.

45 For the COS function, an XOR of the two phase data MSBs is used to deny the positive data generated for quadrants 1 and 4.

The above-mentioned technique reduces the memory requirements by a factor of 4. This already results in a memory requirement of 4K words x 12 bits. In order to further reduce the table dimensions, a trigonometric decomposition is performed at the corners. The following trigonometric identity is used: 50 sin © = 8ϊη (φ1 + φ2) = βϊηφιοοβφ ^ εϊηφ ^ οεφ ·, (4)

By setting υ21 the complete approach becomes as follows: βΐηΘ ^ βΐηφ ^ βΐηφ ^ οβφ! (5)

It is not necessary to use all bits of φ1 when calculating the second term of the equation so that φ1 is a subset of φ ,.

55 The same approach can be used to generate the COS function because: cos © = sin (0 + -ii / 2) (6) 11 194632

This results in a modification of the φ1 and φ1 variables when calculating the COS function. The data stored in the COS ROMs will also include this angle modification so that no changes to the phase data are required.

The modulator 68 mixes the interpolated I and Q samples on lines 80 and 81 with the digital mid-frequency signal represented by the complex SIN and COS function data on lines 84 and 85 to provide a modulated digital mid-frequency signal on line 87.

The interpolated I, Q samples as well as the DDS output signal are digitally mixed by two 10 x 12 multipliers. The output signals of the mixing process are then summed by a 12-bit adder to form a modulated carrier. It is possible to change the operation of the modulator 68 by making all bits of the 1 input signal zero and making all bits of the Q input signal one. The result of this is that one multiplier will only produce zeros and the other will only produce the signal from the DDS SIN, COS generator 67. The sum of these two signals produces a non-modulated digital medium frequency signal.

The modulator 68 generates a modulated digital medium frequency signal on line 87 according to the following equation: f (t) = I.COS (<f> (t)) + Q.SIN (<|> (t)) (7)

The 12-bit output signal from the DDS SIN and COS generator 67 is multiplied by the 10-bit interpolated I and Q samples from the interpolator 63 to generate two 12-bit products. The two products are then added (combined) to generate a 12-bit modulated output 20 signal on line 87.

Because both the 1-multiplier and the Q-multiplier generate 12-bit products, it is possible that a capacity overrun could occur if their output signals are combined.

It is therefore necessary to ensure that the magnitude of the vector generated by I and Q never exceeds the value one (assuming that I1, IQI are fraction numbers <1. If this is not guaranteed, an excess capacity of the adder of the modulator is ensured. possible.

The noise shaper 69 provides a filtered modulated or non-modulated digital medium frequency signal on line 71b to the DAC 18. The noise shaper 69 is designed to achieve a reduction in the amount of noise power in the output spectrum caused by the amplitude quantization error.

The operation of the noise filter 69 is based on the fact that the quantization noise is a normal random process, and that the spectral density of the power of the process is flat over the frequency band. The desired output signal is superimposed on this quantization noise floor. The noise-shaping device is a simple multi-tap filter with finite impulse response (FIR). The filter creates a zero which reduces the power of the quantization noise in a certain portion of the frequency band. When the desired signal is superimposed on the filtered noise spectrum, the effective SQNR increases.

The transfer function of the FIR filter is given by H (z) = 1 + bz'1-z'2 (8)

A stage consisting of two adders creates a second tap value of b in the range of 40 + 1.75 to -1.75 (in binary weights of 0, 0.25, 0.50, 1.0) which is the zero of the filter will move across the output frequency band so that it can be placed as close as possible to the desired output frequency in order to achieve maximum SQNR performance.

The zero frequency can be calculated by dissolving for the roots of the above-mentioned equation in the z-plane. The roots are a complex conjugated pair that lies on the unity circle. The zero frequency 45 follows from the relationship: f ® f (Q \

zero - 360 ° "sampling" I

where Θ is the angle of the root in the upper half plane. The conjugated root will provide a zero 50 that is mirrored around the Nyquist frequency.

Table 2 provides a list of zero frequencies that are generated by the binary weighted second tap. Suppose that b3, b2 and b1 correspond to the weights 1,0, 0,5, 0,25, which means a "+" symbol that the tap is equal to its weight, which means a "" symbol. that the tap is equal to the negative value of its weight, and that "0" means that the tap has no weight. Some of the zero frequencies are the same as those of other combinations, simply because the possible combinations sometimes overlap (for example, 1.0 + 0.5 - 0.25 = 1.0 + 0.0 + 0.25).

^ sample 1Ό0.

194632 12 TABLE 2 b3 b2 b1 f (zero) f (alias) 5 0 0 0 0.250 0.750 0 0 - 0.269 0.731 0 0 + 0.230 0.770 0 + 0 0.210 0.790 0 + + 0.188 0.812 10 0 + - 0.230 0.770 0 - 0 0.290 0.710 0 - + 0.269 0.731 0 - - 0.312 0.688 + 0 0 0.167 0.833 15 + 0 - 0.128 0.812 + 0 + 0.133 0.857 + + 0 0.115 0.885 + + + 0.080 0.420 + + - 0.133 0.877 + + 0.210 0.790 + - + 0.188 0.812 + - - 0.230 0.770 OO 0.333 0.667 O - 0.357 0.643 25 - O +. 0.312 0.688 + O 0.290 0.710 + + 0.269 0.731 + - 0.312 0.688 O 0.385 0.615 30 - + 0.357 0.643 - - 0.420 0.580

All timing is derived from the 21.76 MHz clock signal on line 71a.

The functions associated with the signals in the control registers 64 are now described.

When the CW MODE signal is set, all bits are made zero from the 1 input signal applied to the respective multiplier in the modulator 68, and all bits are made one from the corresponding Q input signal. The result is that a non-modulated carrier will be generated. This function is double buffered and the loaded data will not become active until a 40 TUNE pregnancy is provided.

The INTERPOLATOR ENABLE signal activates the x16 interpolator on the I, Q samples. If the INTERPOLATOR ENABLE signal is not set, the I, Q data is supplied directly to the multiplier.

External memory required for the operation of the processor chip 12 is provided by a fast 45 memory 13 and a slow memory 14. Access to the fast memory 13 is obtained by means of an address decoder 15. The fast memory 13 is a cache memory that is implemented in a RAM that has zero wait cycles. The slow memory 14 is a bulk memory that is implemented in an EPROM, which has two waiting cycles. The slow memory 14 is coupled to the processor chip 12 for storing processing codes used by the processor chip 12 when the codes do not need to be operated with zero wait cycles; and the fast memory is coupled to the processor chip 12 for temporarily storing processing codes used by the processor chip 12 when the codes are operated with zero wait cycles. When procedures are to be performed with zero waiting cycles, the code can be transferred from the slow memory 14 to the fast memory 15 and activated there. Such procedures include the 55 interrupt service routines, symbol demodulation, RCC acquisition, BPSK demodulation as well as the processing of speech and data.

The processor chip 12 comprises a single digital signal processor of the TMS320C25 model, which performs four main tasks, a subscriber control task (SCT) 91, a channel control task (CCT) 92, a signal processing task (SPT) 93, and a mode processing task (MPT) 94, such as shown in Figure 4. These four tasks are controlled by a supervising module 95. The SCT serves the telephone interface * and high-level call processing. The CCT controls the model and RELP operation as well as timing, and performs power level and transmission timing adjustments in accordance with request from the base station. The SPT performs the RELP, the echo cancellation and tone generation functions. The supervisory body calls these four tasks sequentially and communicates with them through control words.

The SCT 91 provides the high level control function within the subscriber unit and has three basic operating modes: idle state, voice operation and termination.

The SCT enters the rest mode after switching on the supply voltage and remains in that state until an actual speech connection is made. While the SCT is in idle mode, it monitors the subscriber telephone interface for activity and responds to requests from the base station that are received through the radio control channel (RCC).

The primary function of the SCT is to guide the subscriber unit by establishing and disconnecting radio channel voice connections. However, before the unit can make a call of any kind, it must find the correct base station. The SCT determines which RCC Frequency is to be used, and sends the frequency information to the CCT. A description of the initialization of a communication channel between the subscriber unit and the base station is given in U.S. Patent Application no. 07 / 070,970, filed July 8, 1987.

Once the subscriber unit has obtained RCC synchronization, it can make a call by exchanging messages via the RCC with the base station, and by monitoring and setting hardware signals on the telephone interface. The following overview briefly describes the events that occur during the making of a call.

The normal making of a call to initiate a call begins with the subscriber taking the handset off the hook to initiate a service request. The SCT sends a CALL REQUEST message to the base station. The SCT receives a CALL CONNECT message. The SET gives a signal to the CCT to attempt synchronization on the assigned voice channel via the CALL CONNECT message. The CCT establishes synchronization on the voice channel. The subscriber receives a dial tone from the exchange. The connection has been established. The exchange provides the further support required for ending the call.

The normal structure of a call for the termination of a call takes place as follows: the SCT receives a PAGE message from the base station. The SCT responds with a CALL ACCEPT. The SCT receives a CALL CONNECT message. The SCT gives a signal to the CCT to attempt to establish synchronization on the assigned voice channel via the CALL CONNECT message. The 35 CCT establishes synchronization on the voice channel. The SCT starts the bell generator to apply a ring signal to the local loop. The subscriber picks up the receiver, the calling is stopped. The voice connection is complete.

The SCT implements the operations for building and ending the call as a finite state machine.

40 If a voice channel occupation is successfully completed, the SCT switches to the speech mode and performs a very limited set of support functions. Loading of the SCT = processor is kept to a minimum at this time in order to ensure maximum availability of processor capacity for the RELP speech compression, echo cancellation and modem processing algorithms.

45 The SCT enters the cancellation mode as a result of an unsuccessful attempt to make a call or an unexpected step sequence to end a call. During the abort mode, a repeat call is sent to the telephone receiver. The SCT monitors the subscriber telephone interface for an interruption signal (on-hook for longer periods of time) at which time the subscriber unit enters idle mode. Requests from the base station that are received via the radio control channel (RCC) are rejected until the hanging is detected.

The CCT 92 acts as a link level channel controller in the base band software. The CCT has three fundamental states: RCC operation, refinement and speech operation.

When switched on, the CCT goes to the RCC operating state to search for and then support the RCC channel. The RCC operation includes the following functions: AM hole control; monitoring the synchronization and status of the modem task; time correction of the radio channel; RCC message filtering upon receipt; RCC message formatting when sending; l / O monitoring of the PCM buffer; as well as link information processing.

194632 14

After a speech connection has been established, the CCT goes to the refinement state for the purpose of fine tuning the fractional timing of the modem. Refinement includes the following functions: interpreting and responding to refinement bursts; creating and formatting refinement bursts when sending; sending messages to the SCT as appropriate; monitoring the modem status; and 1 / O monitoring of the PCM buffer.

After the refinement has taken place, the CCT starts the speech operation, which comprises the following functions: support for code word signaling; restore dropouts; monitoring synchronization and modem status; and 1 / O monitoring of the PCM buffer.

The CCT 92 has three fundamental operating conditions: rest, refinement and speech operation. The following is an overview of the state transitions that occur during CCT operation.

After a reset, the CCT goes to the idle state and remains inactive until it receives channel assignment instructions from the SCT. The SCT provides the CCT with a frequency on which to search for the radio control channel (RCC). The CCT then instructs the MPT to synchronize the receiver on the relevant frequency and to search for an AM hole. If an AM gap is not detected within a predetermined period of time, this results in the CCT requesting a different frequency at the SCT which can be searched for. This continues indefinitely until the AM hole detection is successful.

After an AM hole has been successfully detected, the CCT starts checking whether the unique word is present in the received data. A small window around the nominal position of the unique word is scanned because the AM hole detection process may have a deviation of a few symbol times. As soon as the unique word is located and the CRC Error Detection Word is verified as being correct, the exact receive symbol timing can be determined. The TDM Frame Marks are then corrected to have the correct setting and then the normal RCC support starts. If the unique word cannot be located, the AM hole detection is considered false and the CCT requests the SCT for a new frequency assignment.

During the RCC operation, the CCT filters received RCC messages.

The majority of the base station's RCC messages are null patterns and these are ignored after link information is read from the link byte. RCC messages containing actual information are forwarded to the SCT for processing. If the RCC synchronization is lost, the CCT requests the SCT for a new frequency. The SCT will respond with the correct frequency according to the RCC frequency search algorithm.

When the SCT initiates a voice call, the CCT is assigned a voice channel as well as a time slot. The CCT makes the subscriber unit active according to this assignment and starts the refining process. During the refinement, the base station and the subscriber units transmit a BPSK signal specifically designed to assist the modem in fractional bit-time acquisition. The base station CCU sends the bit time control offset back to the subscriber unit as a two-complement correction value. The CCT maintains a time average of this feedback offset. As soon as the CCT determines that the fractional timing value is within a required tolerance, it corrects the transmission timing of the subscriber unit accordingly. The length of the time average is determined dynamically, depending on the variation of the fractional time samples. After a time correction, 40 the time average is reset and the procedure is repeated.

As soon as the base station detects that the subscriber unit is within an acceptable timing tolerance, it terminates the refining process and the voice operation starts. The length of the refinement process is determined dynamically depending on the success of the timing corrections of the subscriber unit. Power and integer symbol timing are also monitored and corrected as needed during the refining process. If, over time, the subscriber has not found the refinement bursts of the base station, or if the refinement process cannot establish an acceptable timing *, the connection is disconnected and the CCT returns to RCC operation.

After the refinement has been successfully completed, the CCT goes into voice operation at the assigned modulation-50 level. The tasks of the speech company include controlling RELP and MPT operations, establishing speech synchronization and continuously monitoring the speech code words transmitted from the base station. Local changes to the loop control, signaled via the code words, are reported to the SCT as soon as they occur. Incremental changes in power as well as fractional timing are also derived from the code words. Broadcast 55 voice code words are formulated by the CCT based on the local loop control provided by the SCT and the quality of the channel link as reported by the modem. The CCT returns to the RCC when the SCT performs a sequence of steps to end a call.

15, 194632

If the speech synchronization is lost, the CCT initiates a fading recovery operation. After the successful establishment of a good voice connection after ten seconds has not yet been successful, the CCT notifies the SCT of this condition, thereby initiating a call termination. This causes the CCT to return to the idle state.

5 During a channel test operation, a speech burst is replaced by channel test data. As soon as a salvo is received, it is analyzed for bit errors. The bit error count value is passed to the base station via bursts on the return channel.

The SPT 93 performs all digital signal processing tasks (DSP) within the subscriber unit. The various DSP functions are called as required, under the control of the supervising module 95.

The SPT comprises a RELP module which is guided from a very fast RAM memory. The RELP module performs RELP voice compression and expansion with echo cancellation. The RELP module transforms 180 bytes of blocks from 64 kbps PCM speech data to and from 42 bytes of compressed speech data using the RELP algorithm.

The SPT also includes a signal processing control module (SPC) which determines whether to generate tone generation or RELP. If RELP, the SPC determines whether the synthesis or analysis routine should be called. The synthesis routine returns a parity error count value, which is processed by the SPTCTL routine. If tone generation is required, it determines whether the output signal should be silence or a repeat call.

The SPT is controlled via the assignments of the SCT and the CCT. These commands provide invocation and control of the operation of the various functions within the SPT as required by the subscriber unit. The RELP and echo cancellation software are, for example, only executed when the subscriber unit is active in a voice call. Call progress tones are generated at a time when the handset of the subscriber unit is off the hook and RELP is not active. The tones include silence and a repeat call. With the exception of the IDLE mode, the interrupt service routine that controls the PCM codec operates continuously as a foreground process, filling the circulating PCM buffer.

The control and modem functions are performed between the processing of the analysis and the synthesis.

The MPT 94 demodulation procedure is divided into two procedures: DEMODA and DEMODB, by allowing the RELP synthesis to be performed on the receive data in buffer A immediately after the DEMODA procedure is completed. After DEMODA, all internal RAM variables should be stored in external RAM, then reloaded in the internal RAM before DEMODB is executed. The reason for this is that RELP uses the internal RAM.

When the RXCLK interrupt on line 26e is received by the processor chip 12, the MPT causes four received receive data samples to be read and then placed in a circular buffer for processing by the demodulation procedure. Duit allows other tasks to be performed while receiving samples.

The MPT receives the RXCLK interrupt signal on line 26e from the FIR chip 16 every 62.5 ps during the receive slot. The RXCLK interrupt signal is masked by the processor chip equipment during rest or transmission slots.

40 The MPT receives the TXCLK interrupt signal on line 26 of the FIR chip 16 only during the transmit slot. The TXCLK interrupt signal informs the processor chip 12 when a new receive symbol is to be sent to the FIR chip.

The MPT reads four samples from the receive sample buffer 35 into the FIR chip 16 during each RXCLK interrupt on line 26e. The MPT resets the input and output address counters for the buffer at the start of the receive slot.

The MPT sends transmission symbols to the transmission symbol buffer 36 in the FIR chip 16.

The MPT provides the data to the fractional timing circuit in the receive timing module 39 in the FIR chip 16 which is used to synchronize the RXCLK interrupt signal on line 26e with the base station transmission.

50 The MPT also synchronizes the DDS frequency with the base station's transmission frequency.

With reference to Figure 5, the MPT comprises the following modules: a supervising module 101, a training module 102, a frequency acquisition module 102, a bit synchronization module 104, a speech demodulation module 105, a symbol receiving module 106 and a transmitting module 107.

The supervising module 101 is the supervisory body of the MPT task. It reads the MPT-55 control word (CTRL0) from the RAM, and calls other routines according to the control word.

The training module 102 calculates a vector of 28 complex FIR filter coefficients and is activated in idle mode after the power supply is switched on and approximately every three hours. A training transmitter implemented by the MPT in 194632 is activated in a loop return mode to transmit a certain sequence of symbols. This sequence is sent back via a loop to a training receiver implemented by the MPT, in a normal mode, in advanced and delayed timing modes, and on higher and lower adjacent channels.

The training receiver uses the samples of the input waveform to generate a positive perfectly symmetrical matrix A of the order 28. Also, a 28-word vector V is generated from the input samples. The coefficient vector C follows from: C = A'1V (10)

The B coefficient is then calculated according to the algorithm: b = A'1 if A is given.

10 The training transmitter is activated in the loop-back mode for broadcasting five similar pairs of signal sequences, each pair consisting of the following two signal sequences: 1 series: 9 zero symbols, "i", 22 zero symbols Q series: 9 zero symbols, "j , 22 zero symbols

The "i" can be any symbol. The "j" is a symbol that differs from "i" by 90 °.

The processing tasks of the receiver are: setting the AGC so that the signal peak in the normal mode is 50 to 70 & of the maximum. The AGC is increased by 23 db for the fourth and fifth modes.

Read and save the input samples. The first 32 samples are rejected and the following 64 samples are stored in each series.

Structure of the matrix A (28, 28). The following process is performed in normal mode: A (I, J) = A (I, J) + ΣΧ (4Ν-Ι) .Χ (4Ν-ϋ) (11)

The sum applies to every N that meets: 0 (= 4N-1 (64 & 0 (= 4N-J (64 (12))

For the advanced and delayed sequences, the same process is performed with the difference that the term resulting from N = 8 is not added. In the channel series of the higher and lower adjacent adjacent channels, the following process is performed: A (I, J) = A (I, J) + 2X (2N-I) .X (2N-J) (13). .

The sum applies to every N that satisfies: • 0 (= 2N-I (64 & 0 (= 2N-J (64 (14)) Creating the vector V (1:28) from the samples of the first pair of series:

Re {V (1)} = X (32-1); wherein X are samples from the first (1) series. 1m {V (1)} = X (32l); wherein X are samples from the second Q series.

Finding the coefficient vector C by solving the equation:

AxC-V = 0 (15)

These processing steps are more fully described in U.S. Patent No. 4,644,561.

The frequency acquisition module 103 is used when the control channel is received in order to synchronize the receive frequency of the subscriber unit with the send frequency of the base 40 station. This is done by correcting the DDS CW output until the energy in each of the two sidebands of the received signal is equal. Afterwards, the DDS transmission frequencies are corrected in accordance with the calculated frequency deviation.

If the procedure fails to establish frequency synchronization, an appropriate error code is placed in the status word.

The bit synchronization module 104 is used when the RCC is received and after completing the frequency acquisition. A certain pattern is transmitted in the first 44 symbols in the RCC broadcast from the base station and this is used by the module for calculating the RXCLK deviation from the correct sampling time. This deviation is used to correct the RXCLK timing.

The speech demodulation module 105 is used to demodulate a speech slot. This is present in the slow EPROM and its functions are divided between two DEMODA and DEMODB procedures.

The DEMODA functions include initializing parameters for the symbol receiving module 106; calling the symbol receiving module to process the received symbols for buffer A; and 55 storing the variables in the external RAM before exciting.

The DEMODB functions include loading the variables from the external RAM to the internal RAM; calling the symbol receiving module to process the received symbols for buffer B; 17 194632 and determining the link quality and other information after receiving all symbols in the slot.

The symbol receiving module 106 is transferred to the RAM when the CCT enters the speech mode. This is invoked by DEMODA or DEMODB to perform the following tasks: (1) reading 1 and Q samples from the circulating buffer; (2) FIR filtering of the I and Q samples; (3) determining the transmitted symbols and placing them in a buffer; (4) establishing a phase lock loop to synchronize the DDS with the incoming signal; (5) executing the bit tracking algorithm; (6) AGC calculation; and (7) accumulating data for the purpose of the link quality calculation.

The transmit module 107 includes the interrupt service routine for the TXCLK interrupt signal received on line 26e of the FIR chip 16, which occurs once every two symbols during a transmit slot. The functions of the transmission module 107 include: (1) extracting the transmission symbol from the RELP buffer; (2) performing inverse GRAY coding on it; (3) adding it to the previous broadcast phase (due to the EPSK transmission); and (4) sending it to the transmit buffer in the FIR chip 16.

The interface of the MPT with the base band tasks is established via control and status words as well as data buffers in the shared memory. Procedures that require rapid execution are transferred to the cache memory when required. These include the interrupt service routines, symbol demodulation, RCC acquisition and BPSK demodulation.

The MPT supervisor will not wait for RXSOS to read and decode the control word, but will do so immediately when it is called.

The TMS320C25 goes to a reduced power mode when the IDLE instruction is executed. In order to save electrical power, the equipment will be in idle mode most of the time when no telephone call is in progress. Thus, after a reset, the supervisor will acquire RCC synchronization and then enter the rest mode until a predetermined interrupt causes a corresponding service routine to be performed. When operated in the reduced power mode, the TMS320C25 enters a sleep state and requires only a fraction of the power normally required to power the device. During the reduced power mode, the entire internal content of the processor is maintained to allow operation to continue unchanged when the reduced power mode is terminated. As soon as an interrupt is received, the processor chip 12 temporarily terminates the mode with reduced power and resumes normal operation for a minimum duration of a main loop cycle. The requirements of the reduced power mode are checked each time at the end of the main loop to determine whether or not the subscriber unit should return to the reduced power mode. The slot clock signaa! is based on the slot time control generated by the hardware. When a slot marker signal pulls an interrupt, the routine increments the clock signal with a tap. Each clock tick represents a duration of 11.25 milliseconds.

The receive and send functions of the UART are not interrupt controlled, but are controlled by the background software (this controls the loading of the processor and prevents uncontrolled interrupt conditions). The processing code supports the XON / XOFF protocol for directly intercepting these characters and immediately activating or deactivating the UART transmission as appropriate. The speed of the receive and transmit operation is designed to be selectable by means of an external DIP switch device. The characteristic data receiving speed is 9600 baud. A circulation buffer is used to control the transmission of the. UART. The background software periodically checks the queue and initiates the transmission if it is not empty. It does this by sending bytes to the UART with 1 byte at a time until the queue is empty.

45 The hook switch is sampled with the TMS320C25's internal timing interrupt routine. In order to simulate DC signaling, a sampling period of 1.5 milliseconds is achieved.

This interrupt is synchronized with the frame timing at the beginning of each frame; therefore, its frequency is phase-locked with the base station to prevent undershooting or exceeding of the capacity of the hook buffer. For each interrupt, a bit representing the hook detection signal 50 (from the SLIC) is input to the 60-bit hook sample buffer (SSB). The SSB is examined by the SCT, once per 45 ms in normal operation. This interrupt is always activated by the software.

Claims (9)

194632 18 A subscriber unit for a wireless digital telephone communication system, wherein the subscriber unit comprises coding / decoding means and an associated processing unit for recoding an input signal to provide digital input symbols, FIR means responsive to the processing unit for providing FIR filtered digital input symbols, a radio unit for sending a signal comprising the information contained in the FIR filtered digital input symbols, to a second unit within the system and for demodulating an output signal received from the second unit, and wherein the processing unit compose digital output signals 10 from the demodulated output signal, characterized in that the FIR means are realized as an FIR chip, which comprises: means for internal address decoding (34) to enable the processing unit (12) to gain access to internal functions of the FIR chip (16) ; control and status registers (36) that enable the processing unit (12) to read the status of the FIR chip (16) and control its internal functions; said means (42) for finite impulse response filtering of the digital input symbols; and timing control means that enable the processing unit (12) to control the FIR filtering means (42). Subscriber unit according to claim 1, characterized in that the FIR filtering means (42) comprises a read-only memory (ROM), which serves as a reference table for providing the filtered digital input symbols in response to the digital input symbols as provided by the processing unit (12). 3. Subscriber unit according to claim 1 or 2, characterized in that the FIR chip (16) comprises a receive-time control module (39) and a send-time control module (40), which are connected to the processing unit (12) for the timing of the recoding operation and the assembly operation. Subscriber unit according to one of Claims 1 to 3, characterized in that it comprises call control means (45) which are connected to the control and status registers (36) to enable the processing unit (12) to control the bell of the subscriber unit (21). Subscriber unit according to one of claims 1 to 4, characterized in that it comprises a monitoring timing circuit (38) connected to the control and status registers (36) for resetting the processing unit ( 12). Subscriber unit according to one of claims 1 to 5, characterized in that it comprises a sampling buffer (35) coupled to the processing unit (12) for the interim storage of received data samples before the data samples are output to the processing unit (12). Subscriber unit according to one of claims 5 or 6, characterized in that it comprises a branching buffer (33) for receiving and temporarily storing a main clock signal, for receiving a forwarded clock signal and for receiving a reset signal from the monitoring time control 40 (3 8). Subscriber unit according to one of claims 1 to 7, characterized in that it further comprises an external address decoding unit (37) which is connected to the processing unit (12) to enable the processing unit (12). to access selected components of the subscriber unit. Subscriber unit according to one of claims 6, 7 and 8, insofar as claims 7 and 8 refer to claim 6, characterized in that the FIR chip (16) comprises an internal address decoding module (34) which is connected to the receive-time control module (39), the send-time control module (40), the control and status registers (36), the sampling buffer (35) and the processing unit (12) via a processing bus (25) around the processing unit ( 12) enable the operation of the FIR chip (16) to be controlled. Hereby 4 sheets of drawing