RU2255351C1 - Radio-receiving device of coherent radar with optimum filtration of signal - Google Patents

Abstract

FIELD: procedure of processing of radar signals.

SUBSTANCE: the device has the first and second receiving channels. The first receiving channel includes device of quadrature phase detection A1 and preliminarily processing device A3, quadrature phase detection device A1 of the first channel has an adder, amplifier unit with a time automatic gain control, the first and second frequency mixers, the first and second operational amplifiers, the first and second voltage comparators, the first and second low-pass filters, the first and second integrators, the first, second monitory circuit and a serviceability signal formation circuit. In its turn preliminarily processing device A3 of the first channel consists of the first and second analog-to-digital converters, the first and second digital-to-analog converters, digital heterodyning device, permanent storage of the digital heterodyning device, the first and second reversible counters, the first and second N-digit counter-type adders, the first and second multiplexers, write address driver, the first and second internal storages of every-period processing, read address driver, the first and second optimum filters, reference signal conditioner, first and second microcircuits FiFo ("first entered, first left"), control device, the first and second switches. The second receiving channel has quadrature phase detection device A2 and preliminary processing device A4, which schematically-structurally are made similarly to quadrature phase detection device A1 of the first channel and preliminary processing device A3 of the first channel. The radio receiving device of the coherent radar with optimum filtration signal includes the first and second decoders, crystal oscillator, level converter, frequency divider, band-pass filter, differentiating circuit, integrating circuit, the first and second tuned amplifiers, the third and fourth multiplexers and a signal synchronizer. The device also has a connector of the first channel input signal, connector of the input reference signal, connector of the second channel input signal, contact of the pulse for formation of the strobe pulse of antenna re-tuning, contact of the trigger signal the transmitter final stage, contact of the signal determining the phase of the transmitter trigger pulse, contact of the signal determining the phase of the transmitter trigger pulse, contact of the signal of the receiver blanking pulse, contact of the pulse accompanying the main signal, contact of the pulse of transmission beginning, connector of the output signal of the imaginary component, and a parallel information line.

EFFECT: expanded functional potentialities and improved basic technical characteristics of the radar parameters.

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Description

The application relates to techniques for processing signals of radar stations (radar).

The incoherent receiver (USSR Author's Certificate No. 1525933, H 04 L 17/30, 1989) with increased noise immunity is known from the prior art, but it does not process the phase structure of the signal.

A device for recognizing moving objects is known (RF Certificate for Utility Model No. 21250, G 01 K 9/00, 2001), which determines the class of an object, but does not solve the problem of expanding the dynamic range of the receiver.

A coherent radar receiver (RF application for invention No.2000120020, bulletin "Inventions, utility models" No. 16, 2002, p. 126) does not provide digital heterodyning of the processed signal and has an error when digitally adjusting the quadrature of the received signals.

The closest in technical essence is an incoherent signal detector in noise (Application of the Russian Federation for invention No. 200102468, bulletin "Inventions, utility models" No. 8, 2002, p. 71), including incoherent local oscillator, phase-shifting circuit, analog-to-digital converter, the first and second frequency mixers, first and second intermediate frequency filters, the first inputs of the mentioned mixers are connected to the signal input, the second input of the first mixer is connected to the local oscillator output through a phase-shifting chain, the second input of the second mixer the frequency is also connected to the output of the local oscillator, the outputs of the first and second mixers are connected to the inputs of the first and second filters of the intermediate frequency, respectively, the first and second voltage comparators are introduced into the circuit, the logic circuit is "Exclusive" OR ", the counter divider is 2n, N-bit accumulating an adder, a third number comparator and an m-bit register, the output of one of the intermediate frequency filters is connected to the signal input of an analog-to-digital converter and the non-inverting input of the first voltage comparator, output the second filter is connected to the non-inverting input of the second voltage comparator, the inverting inputs of the mentioned comparators are connected to zero potential, the outputs of the first and second comparators are connected to the first and second inputs of the “Exclusive OR” logic circuit, the output of the mentioned circuit is connected to the clock input of the mentioned analog-to-digital converter and with the input of the counter-divider by n, the digital output bus of the aforementioned analog-to-digital converter without a sign discharge is connected to the N-bit input, I accumulate of its adder, m = Nn of the output high order bits of the accumulating adder are connected to the input of the third number comparator, the second input of the third number comparator is connected to the output of the m-bit register, into which the binary threshold code is written, the control input of the said number comparator is connected to the output of the said divider counter on n.

However, when using it, it does not provide optimal filtering (temporary compression of the phase-code-manipulated signal) and coherent processing of the received signal, since this is not provided for in the circuit design in the known technical solution.

The technical result of the proposed technical solution is aimed at expanding the functionality and improving the basic technical parameters of the radar.

The technical result is achieved by  that a coherent radar receiver with optimal signal filtering comprises a first analog-to-digital converter,  first and second frequency mixers,  first N-bit accumulating adder,  first and second voltage comparators,  and the first receiving channel includes a quadrature phase detection device A1 and a pretreatment device A3,  wherein the quadrature phase detection device A1 of the first channel comprises an adder,  amplifier block with temporary automatic gain control,  first and second frequency mixers,  first and second operational amplifiers,  first and second voltage comparators,  first and second low-pass filters,  first and second integrators,  the first and second control schemes,  health signal generation circuit,  in turn, the pre-processing device A3 of the first channel consists of the first and second analog-to-digital converter,  first and second digital-to-analog converters,  digital heterodyne devices,  read-only memory digital heterodyning,  first and second reversible counters,  the first and second accumulating N-bit adders,  first and second multiplexers,  shaper of the address of the record,  first and second random access memory through-period processing,  read address driver  first and second optimal filters,  reference signal driver,  the first and second FiFo chips "the first came in,  first out, "  control devices  first and second switches,  wherein the second receiving channel comprises a quadrature phase detection device A2 and a preprocessing device A4,  which are structurally similar to the quadrature phase detection device A1 of the first channel and the preliminary processing device A3 of the first channel,  as well as the first and second decoders are included in the coherent radar receiver with optimal signal filtering,  crystal oscillator  level converter  frequency divider,  bandpass filter  differentiating chain  integrating chain  first and second resonant amplifiers,  third and fourth multiplexers,  signal synchronizer  wherein the input of the receiver through the first channel is connected to the first input of the quadrature phase detection device A1 of the first channel,  the first output of the quadrature phase detection device A1 of the first channel is connected to the second input of the preliminary processing device A3 of the first channel,  the first output of the pre-processing device A3 of the first channel is connected to the first input of the third multiplexer,  the output of the third multiplexer is connected to the connector of the output signal of the real component,  the input reference signal connector is connected to the input of the frequency divider and the input of the level converter,  the output of the frequency divider is connected to the input of the bandpass filter,  the output of the bandpass filter is connected to the input of the differentiating chain and the input of the integrating chain,  the output of the differentiating circuit is connected to the input of the first resonant amplifier,  the first output of the resonant amplifier is connected to the second input of the quadrature phase detection device A1 of the first channel,  the second output of the first resonant amplifier is connected to the second input of the quadrature phase detection device A2 of the second channel,  the output of the integrating circuit is connected to the input of the second resonant amplifier,  the first output of the second resonant amplifier is connected to the third input of the quadrature phase detection device A1 of the first channel,  the second output of the second resonant amplifier is connected to the third input of the quadrature phase detection device A2 of the second channel,  the first output of the quadrature phase detection device A2 of the second channel is connected to the second input of the pre-processing device A4 of the second channel,  the first output of the pre-processing device A4 of the second channel is connected to the second input of the fourth multiplexer,  the output of the fourth multiplexer is connected to the output connector of the imaginary component,  the first output of the signal synchronizer is connected to the input of the crystal oscillator,  the first output of the crystal oscillator is connected to the fourth input of the quadrature phase detection device A1 of the first channel,  the second output of the crystal oscillator is connected to the fourth input of the quadrature phase detection device A2 of the second channel,  the second output of the signal synchronizer is connected to the input of the first decoder,  the output of the first decoder is connected to the fifth input of the quadrature phase detection device A1 of the first channel,  the third output of the signal synchronizer is connected to the input of the second decoder,  the output of the second decoder is connected to the fifth input of the quadrature phase detection device A2 of the second channel,  the output of the level converter is connected to the first input of the signal synchronizer,  the second output of the quadrature phase detection device A2 of the second channel is connected to the third input of the signal synchronizer,  the third output of the quadrature phase detection device A2 of the second channel is connected to the third input of the pre-processing device A4 of the second channel,  the second output of the quadrature phase detection device A1 of the first channel is connected to the second input of the signal synchronizer,  the third output of the quadrature phase detection device A1 of the first channel is connected to the third input of the preliminary processing device A3 of the first channel,  the fifth output of the signal synchronizer is connected to the fourth input of the pre-processing device A4 of the second channel,  the sixth output of the signal synchronizer is connected to the fifth input of the pre-processing device A4 of the second channel,  the seventh output of the signal synchronizer is connected to the sixth input of the pre-processing device A4 of the second channel,  the eighth output of the signal synchronizer is connected to the seventh input of the pre-processing device A4 of the second channel,  the ninth output of the signal synchronizer is connected to the eighth input of the pre-processing device A4 of the second channel,  the tenth output of the signal synchronizer is connected to the ninth input of the pre-processing device A4 of the second channel,  the eleventh output of the signal synchronizer is connected to the pulse contact to form the antenna tuning gate,  the twelfth output of the signal synchronizer is connected to the contact of the trigger signal of the final stage of the transmitter,  the thirteenth output of the signal synchronizer is connected to the signal contact,  determining the duration of the start pulse of the transmitter,  the fourteenth output of the signal synchronizer is connected to the signal contact,  determining the phase of the transmitter trigger pulse,  the fifteenth output of the signal synchronizer is connected to the contact signal of the pulse blanking receiver,  the sixteenth output of the signal synchronizer is connected to a pulse contact,  accompanying the main signal,  the seventeenth output of the signal synchronizer is connected to the contact of the pulse start transmission,  the eighteenth output of the signal synchronizer is connected to the tenth input of the pre-processing device A4 of the second channel,  the nineteenth output of the signal synchronizer is connected to the third input of the third multiplexer and the third input of the fourth multiplexer,  the twentieth output of the signal synchronizer is connected to the fourth input of the preliminary processing device A3 of the first channel,  the twenty-first output of the signal synchronizer is connected to the fifth input of the preliminary processing device A3 of the first channel,  the twenty-second output of the signal synchronizer is connected to the sixth input of the preliminary processing device A3 of the first channel,  the twenty-third output of the signal synchronizer is connected to the seventh input of the preliminary processing device A3 of the first channel,  the twenty-fourth output of the signal synchronizer is connected to the eighth input of the preliminary processing device A3 of the first channel,  the twenty-fifth output of the signal synchronizer is connected to the ninth input of the pre-processing device A3 of the first channel,  the twenty-sixth output of the signal synchronizer is connected to the tenth input of the preliminary processing device A3 of the first channel,  a parallel information trunk connector is connected to the first and eleventh inputs of the preprocessing apparatus A3 of the first channel,  with the first and eleventh inputs of the pre-processing device A4 of the second channel and with the fourth output of the signal synchronizer,  the second output of the pre-processing device A3 of the first channel is connected to the first input of the fourth multiplexer,  the second output of the pre-processing device A4 of the second channel is connected to the second input of the third multiplexer,  in the quadrature phase detection device A1 of the first channel, the first input is connected to the first input of the adder,  the output of the adder is connected to the first input of the amplifier block with temporary automatic gain control,  the output of the amplifier block with temporary automatic gain control is connected to the first input of the first frequency mixer and to the first input of the second frequency mixer,  the output of the first frequency mixer is connected to the first input of the first operational amplifier,  the output of the first operational amplifier is connected to the input of the first low-pass filter,  the output of the first low pass filter is connected to the first output of the quadrature phase detection device A1 of the first channel,  with the input of the first control circuit and with the input of the first integrator,  the output of the first integrator is connected to the input of the first voltage comparator,  the output of the first voltage comparator is connected to the second input of the first operational amplifier,  the output of the second frequency mixer is connected to the first input of the second operational amplifier,  the output of the second operational amplifier is connected to the input of the second low-pass filter,  the output of the low-pass filter is connected to the third output of the quadrature phase detection device A1 of the first channel,  with the input of the second control circuit and with the input of the second integrator,  the output of the second integrator is connected to the input of the second voltage comparator,  the output of the second voltage comparator is connected to the second input of the second operational amplifier,  the output of the first control circuit is connected to the first input of the health signal generating circuit,  the output of the second control circuit is connected to the second input of the health signal generating circuit,  the output of the health signal generating circuit is connected to the second output of the quadrature phase detection device A1 of the first channel,  the fourth input of the quadrature phase detection device A1 of the first channel is connected to the second input of the adder,  the second input of the quadrature phase detection device A1 of the first channel is connected to the second input of the first frequency mixer,  the third input of the quadrature phase detection device A1 of the first channel is connected to the second input of the second frequency mixer,  the fifth input of the quadrature phase detection device A1 of the first channel is connected to the second input of the amplifier block with temporary automatic gain control,  the input signal of the second channel is connected to the first input of the phase detection device A2 of the second channel,  the first input of the pre-processing device A3 of the first channel is connected to the third input of the first multiplexer,  the second input of the pre-processing device A3 of the first channel is connected to the second input of the first analog-to-digital converter,  the output of the first analog-to-digital converter is connected to the fifth input of the digital heterodyning device,  the first output of the digital heterodyning device is connected to the first input of the first N-bit accumulating adder,  the first output of the first N-bit accumulating adder is connected to the first input of the first multiplexer,  the output of the first multiplexer is connected to the first input of random access memory and to the second input of the first switch,  the output of the first random-access memory is connected to the first input of the optimal filter,  the output of the first optimal filter is connected to the first input of the first FiFo chip,  the output of the first FiFo chip is connected to the first input of the first voltage switch,  the output of the first voltage switch is connected to the first output of the preliminary processing device A3 of the first channel,  the third input of the pre-processing device A3 of the first channel is connected to the first input of the second analog-to-digital converter,  the output of the second analog-to-digital converter is connected to the second input of the digital heterodyning device,  the second output of the digital heterodyning device is connected to the first input of the second N-bit accumulating adder,  the first output of the second N-bit accumulating adder is connected to the first input of the second multiplexer,  the output of the second multiplexer is connected to the first input of the second random-access memory and to the second input of the second switch,  the output of the second random-access memory is connected to the first input of the second optimal filter,  the output of the second optimal filter is connected to the first input of the second FiFo chip,  the output of the second FiFo chip is connected to the first input of the second switch,  the output of the second switch is connected to the second output of the pre-processing device A3 of the first channel,  the second output of the first N-bit accumulating adder is connected to the first input of the first reversible counter,  the output of the first reversible counter is connected to the input of the first digital-to-analog converter,  the output of the first digital-to-analog converter is connected to the first input of the first analog-to-digital converter,  the second output of the second N-bit accumulating adder is connected to the first input of the second reversible counter,  the output of the second reversible counter is connected to the input of the second digital-to-analog converter,  the output of the second digital-to-analog converter is connected to the second input of the analog-to-digital converter,  the fourth input of the pre-processing device A3 of the first channel is connected to the third input of the second analog-to-digital converter,  with the third input of the first analog-to-digital converter,  with the first input of the digital heterodyning device,  the fifth input of the first channel processing apparatus A3 of the first channel is connected to the input of the read-only memory of the digital heterodyning device,  the first output of the read-only memory of the digital heterodyning device is connected to the third input of the digital heterodyning device,  the second output of the digital memorization device is connected to the fourth input of the digital heterodyning device,  the sixth input of the pre-processing device A3 of the first channel is connected to the second input of the second N-bit accumulating adder and to the second input of the first N-bit accumulating adder,  the seventh input of the pre-processing device A3 of the first channel is connected to the third input of the second N-bit accumulating adder and to the third input of the first N-bit accumulating adder,  the eighth input of the pre-processing device A3 of the first channel is connected to the second input of the second reversible counter,  with the second input of the second multiplexer,  with the input of the address generator of the record,  with the second input of the first multiplexer and with the second input of the first reversible counter,  the ninth input of the preprocessing device A3 of the first channel is connected to the input of the read address generator,  with the input of the driver of the reference signals,  with the second input of the second FiFo chip,  with the input of the control device and with the second input of the first FiFo chip,  the tenth input of the pre-processing device A3 of the first channel is connected to the third input of the first switch and the third input of the second switch,  the first output of the control device is connected to the third input of the first FiFo chip,  the second output of the control device is connected to the fourth input of the first FiFo chip,  the third output of the control device is connected to the third input of the second FiFo chip,  the fourth output of the control device is connected to the fourth input of the second FiFo chip,  the first output of the driver of the reference signals is connected to the second input of the first optimal filter,  the second output of the driver of the reference signals is connected to the second input of the second optimal filter,  the output of the recording address generator is connected to the second input of the first random access memory of the inter-period processing and the second input of the second random access memory of the inter-period processing,  the output of the read address generator is connected to the third input of the first random access memory of the inter-period processing and to the third input of the second random access memory of the inter-period processing,  the eleventh input of the pre-processing device A3 of the first channel is connected to the third input of the second multiplexer,  interstage communications in the quadrature phase detection device A2 of the second channel are similar to interstage communications in the quadrature phase detection device A1 of the first channel,  interstage communications of the pre-processing device A4 of the second channel are similar to interstage communications in the pre-processing device A3 of the first channel.

Distinctive features of the prototype is that the first receiving channel includes a quadrature phase detection device A1 and a pretreatment device A3, while the quadrature phase detection device A1 of the first channel includes an adder, an amplifier unit with automatic time gain control, first and second frequency mixers, first and second operational amplifiers, first and second voltage comparators, first and second low-pass filters, first and second integrators, first and second with control circuits and a working signal generation circuit, in turn, the first channel A3 preprocessing device consists of the first and second analog-to-digital converters, the first and second digital-to-analog converters, the digital heterodyning device, the permanent storage device of the digital heterodyning device, the first and second reversible counters , the first and second accumulating adders, the first and second multiplexers, the shaper of the write address, the first and second operative memory devices of inter-period processing, a shaper of a read address, a first and second optimal filters, a shaper of reference signals, the first and second FiFo microcircuits “first entered, first left”, a control device, first and second switches, while the second reception channel contains a quadrature phase device A2 detection and A4 pre-processing device, which are structurally made similar to the quadrature phase detection device A1 of the first channel and the pre-device The first and second decoders, a crystal oscillator, a level converter, a frequency divider, a band-pass filter, a differentiating circuit, an integrating circuit, the first and second resonant amplifiers, the third and fourth ones, are included in the A3 channel of the first channel, as well as in a coherent radar receiver with optimal signal filtering multiplexers, a signal synchronizer and new interstage communications between them.

The proposed technical solution provides controlled amplification, frequency conversion, decomposition into quadrature components, analog-to-digital signal conversion, digital heterodyning, accumulation, optimal filtering of phase-code-manipulated signals from a high-frequency radar receiver.

Figure 1 shows the functional electrical diagram of the proposed device, figure 2 is the same, a continuation of figure 1.

A coherent radar radio receiver with optimal signal filtering comprises first and second reception channels.

The first receiving channel includes a quadrature phase detection device A1 and a pretreatment device A3, while the quadrature phase detection device A1 of the first channel includes an adder 9, an amplifier unit with temporarily automatic gain control 12, the first 13 and second 14 frequency mixers, the first 15 and second 17 operational amplifiers, the first 16 and second 18 voltage comparators, the first 19 and second 21 low-pass filters, the first 20 and second 22 integrators, the first 23, the second 24 control circuits and the formation circuit health indicator 25. In turn, the first channel A3 pre-processor consists of the first 26 and second 27 analog-to-digital converters, the first 28 and second 35 digital-to-analog converters, the digital heterodyning device 29, the read-only memory of the digital heterodyning device 30, the first 31 and the second 34 reverse counters, the first 32 and second 33 N-bit accumulators, the first 36 and second 38 multiplexers, the shaper of the write address 37, the first 39 and second 40 op of memory devices for inter-period processing, a shaper of a read address 41, a first 42 and a second 44 optimal filters, a shaper of the reference signals 43, the first 45 and the second 47 of the FiFo microcircuits ("the first entered, the first left"), the control device 46, the first 48 and the second 49 switches.

The second receiving channel comprises a quadrature phase detection device A2 and a pre-processing device A4, which are structurally similar to the quadrature phase detection device A1 of the first channel and the preliminary processing device A3 of the first channel.

The coherent radar receiver with optimal signal filtering includes the first 5 and second 4 decoders, a crystal oscillator 3, a level 1 converter, a frequency divider 2, a bandpass filter 6, a differentiating circuit 7, an integrating circuit 8, the first 10 and second 11 resonant amplifiers, the third 51 and fourth 52 multiplexers and signal synchronizer 50.

The device also contains a connector of the input signal 53 of the first channel, a connector of the input reference signal 54, a connector of the input signal of the second channel 55, a pulse contact for forming the tuning gate of the antenna 56, a contact of the trigger signal of the final stage of the transmitter 57, a signal contact that determines the duration of the trigger pulse of the transmitter 58, the contact of the signal determining the phase of the start pulse of the transmitter 59, the contact of the signal of the blanking pulse of the receiver 60, the contact of the pulse accompanying the main signal 61, the contact of the start pulse la transmission 62, the output signal connector of the real component 63, the output signal connector of the imaginary component 64 and the parallel information highway 65.

The input signal connector of the first channel 53 is connected to the first input of the quadrature phase detection device A1 of the first channel. The first output of the quadrature phase detection device A1 of the first channel is connected to the second input of the preliminary processing device A3 of the first channel. The first output of the pre-processing apparatus A3 of the first channel is connected to the first input of the third multiplexer 51.

The output of the third multiplexer 51 is connected to the connector of the output signal of the real component 63. The connector of the input reference signal 54 is connected to the input of the frequency divider 2 and the input of the level converter 1. The output of the frequency divider 2 is connected to the input of the bandpass filter 6. The output of the bandpass filter 6 is connected to the input of the differentiating circuit 7 and the input of the integrating chain 8. The output of the differentiating chain 7 is connected to the input of the first resonant amplifier 10. The first output of the resonant amplifier 10 is connected to the second input of the quadrature device A1 of the phase detection of the first channel.

The second output of the first resonant amplifier 10 is connected to the second input of the quadrature phase detection device A2 of the second channel. The output of the integrating circuit 8 is connected to the input of the second resonant amplifier 11. The first output of the second resonant amplifier 11 is connected to the third input of the quadrature phase detection device A1 of the first channel. The second output of the second resonant amplifier 11 is connected to the third input of the quadrature phase detection device A2 of the second channel.

The input signal connector of the second channel 55 is connected to the first input of the quadrature phase detection device A2 of the second channel. The first output of the quadrature phase detection device A2 of the second channel is connected to the second input of the pre-processing device A4 of the second channel.

The first output of the pre-processing device A4 of the second channel is connected to the second input of the fourth multiplexer 52. The output of the fourth multiplexer 52 is connected to the output signal connector of the imaginary component 64.

The first output of the signal synchronizer 50 is connected to the input of the crystal oscillator 3. The first output of the crystal oscillator 3 is connected to the fourth input of the quadrature phase detection device A1 of the first channel. The second output of the crystal oscillator 3 is connected to the fourth input of the quadrature phase detection device A2 of the second channel.

The second output of the signal synchronizer 50 is connected to the input of the first decoder 5. The output of the first decoder 5 is connected to the fifth input of the quadrature phase detection device A1 of the first channel.

The third output of the signal synchronizer 50 is connected to the input of the second decoder 4. The output of the second decoder 4 is connected to the fifth input of the quadrature phase detection device A2 of the second channel. The output of the level 1 converter is connected to the first input of the signal synchronizer 50. The second output of the second channel quadrature phase detection device A2 is connected to the third input of the signal synchronizer 50. The third output of the second channel quadrature phase detection device A2 is connected to the third input of the second channel pre-processing device A4.

The second output of the quadrature phase detection device A1 of the first channel is connected to the second input of the signal synchronizer 50.

The third output of the quadrature phase detection device A1 of the first channel is connected to the third input of the preliminary processing device A3 of the first channel.

The fifth output of the signal synchronizer 50 is connected to the fourth input of the pre-processing device A4 of the second channel.

The sixth output of the signal synchronizer 50 is connected to the fifth input of the pre-processing device A4 of the second channel.

The seventh output of the signal synchronizer 50 is connected to the sixth input of the pre-processing device A4 of the second channel.

The eighth output of the signal synchronizer 50 is connected to the seventh input of the pre-processing device A4 of the second channel.

The ninth output of the signal synchronizer 50 is connected to the eighth input of the pre-processing device A4 of the second channel.

The tenth output of the signal synchronizer 50 is connected to the ninth input of the pre-processing device A4 of the second channel.

The eleventh output of the signal synchronizer 50 is connected to a pulse contact to form a tuning gate of the antenna 56.

The twelfth output of the signal synchronizer 50 is connected to the contact of the trigger signal of the final stage of the transmitter 57.

The thirteenth output of the signal synchronizer 50 is connected to a signal contact that determines the duration of the start pulse of the transmitter 58.

The fourteenth output of the signal synchronizer 50 is connected to a signal contact that defines the phase of the start pulse of the transmitter 59.

The fifteenth output of the signal synchronizer 50 is connected to the contact of the signal of the pulse blanking receiver 60.

The sixteenth output of the signal synchronizer 50 is connected to a pulse contact accompanying the main signal 61.

The seventeenth output of the signal synchronizer 50 is connected to the contact of the transmission start pulse 62.

The eighteenth output of the signal synchronizer 50 is connected to the tenth input of the pre-processing device A4 of the second channel.

The nineteenth output of the signal synchronizer 50 is connected to the third input of the third multiplexer 51 and the third input of the fourth multiplexer 52.

The twentieth output of the signal synchronizer is connected to the fourth input of the pre-processing device A3 of the first channel.

The twenty-first output of the signal synchronizer 50 is connected to the fifth input of the pre-processing device A3 of the first channel.

The twenty-second output of the signal synchronizer 50 is connected to the sixth input of the pre-processing device A3 of the first channel.

The twenty-third output of the signal synchronizer 50 is connected to the seventh input of the preliminary processing device A3 of the first channel.

The twenty-fourth output of the signal synchronizer 50 is connected to the eighth input of the first channel processing apparatus A3.

The twenty-fifth output of the signal synchronizer 50 is connected to the ninth input of the first channel processing apparatus A3.

The twenty-sixth output of the signal synchronizer 50 is connected to the tenth input of the pre-processing device A3 of the first channel.

The connector of the parallel information highway 65 is connected to the first and eleventh inputs of the preliminary processing device A3 of the first channel, with the first and eleventh inputs of the preliminary processing device A4 of the second channel and the fourth output of the signal synchronizer 50.

The second output of the pre-processing apparatus A3 of the first channel is connected to the first input of the fourth multiplexer 52.

The second output of the pre-processing device A4 of the second channel is connected to the second input of the third multiplexer 51.

In the quadrature phase detection device A1 of the first channel, the first input is connected to the first input of the adder 9. The output of the adder 9 is connected to the first input of the amplifier block with temporary automatic gain control 12. The output of the amplifier block with temporary automatic gain control is connected to the first input of the first frequency mixer 13 and with the first input of the second frequency mixer 14.

The output of the first frequency mixer 13 is connected to the first input of the first operational amplifier 15. The output of the first operational amplifier 15 is connected to the input of the first low-pass filter 19. The output of the first low-pass filter 19 is connected to the first output of the quadrature phase detection device A1 of the first channel, with the input of the first circuit control 23 and with the input of the first integrator 20.

The output of the first integrator 20 is connected to the input of the first voltage comparator 16. The output of the first voltage comparator 16 is connected to the second input of the first operational amplifier 15. The output of the second frequency mixer 14 is connected to the first input of the second operational amplifier 17. The output of the second operational amplifier 17 is connected to the input of the second filter low pass 21. The output of the low pass filter 21 is connected to the third output of the quadrature phase detection device A1 of the first channel, with the input of the second control circuit 24, with the input of the second and Integrator 22.

The output of the second integrator 22 is connected to the input of the second voltage comparator 18. The output of the second voltage comparator 18 is connected to the second input of the second operational amplifier 17. The output of the first control circuit 23 is connected to the first input of the health signal generating circuit 25.

The output of the second monitoring circuit 24 is connected to the second input of the health signal generating circuit 25. The output of the health signal generating circuit 25 is connected to the second output of the quadrature phase detection device A1 of the first channel.

The fourth input of the quadrature phase detection device A1 of the first channel is connected to the second input of the adder 9.

The second input of the quadrature phase detection device A1 of the first channel is connected to the second input of the first frequency mixer 13.

The third input of the quadrature phase detection device A1 of the first channel is connected to the second input of the second frequency mixer 14.

The fifth input of the quadrature phase detection device A1 of the first channel is connected to the second input of the amplifier unit with a temporary automatic gain control 12.

The first input of the pre-processing apparatus A3 of the first channel is connected to the third input of the first multiplexer 36.

The second input of the pre-processing device A3 of the first channel is connected to the second input of the first analog-to-digital converter 26.

The output of the first analog-to-digital Converter 26 is connected to the fifth input of the digital heterodyning device 29.

The first output of the digital heterorating device 29 is connected to the first input of the first N-bit accumulating adder 32. The first output of the first N-bit accumulating adder 32 is connected to the first input of the first multiplexer 36. The output of the first multiplexer 36 is connected to the first input of the inter-period processing random access memory 39 and with the second input of the first switch 48. The output of the first random access memory 39 is connected to the first input of the optimal filter 42. The output is not The first optimal filter 42 is connected to the first input of the first FiFo 45 chip. The output of the first FiFo 45 chip is connected to the first input of the first voltage switch 48.

The output of the first voltage switch 48 is connected to the first output of the preliminary processing device A3 of the first channel.

The third input of the pre-processing device A3 of the first channel is connected to the first input of the second analog-to-digital converter 27. The output of the second analog-to-digital converter 27 is connected to the second input of the digital heterodyning device 29. The second output of the digital heterodyning device 29 is connected to the first input of the second N-bit accumulating the adder 33. The first output of the second N-bit accumulating adder 33 is connected to the first input of the second multiplexer 38. The output of the second multiplexer 38 is connected to the first input of the second random-access memory 40 and with the second input of the second switch 49. The output of the second random-access memory 40 is connected to the first input of the second optimal filter 44. The output of the second optimal filter 44 is connected to the first input of the second FiFo 47 chip. The second output the FiFo 47 is connected to the first input of the second switch 49. The output of the second switch 49 is connected to the second output of the preprocessor A3 of the first channel. The second output of the first N-bit accumulating adder 32 is connected to the first input of the first reverse counter 31. The output of the first reverse counter 31 is connected to the input of the first digital-to-analog converter 28. The output of the first digital-to-analog converter 28 is connected to the first input of the first analog-to-digital converter 26. The second output of the second N-bit accumulating adder 33 is connected to the first input of the second reversible counter 34. The output of the second reversible counter 34 is connected to the input of the second digital-analog converter 35. The output of the second digital to analog converter 35 is connected to a second input of the analog-digital converter 27.

The fourth input of the pre-processing device A3 of the first channel is connected to the third input of the second analog-to-digital converter 27, with the third input of the first analog-to-digital converter 26, with the first input of the digital heterodyning device 29.

The fifth input of the pre-processing device A3 of the first channel is connected to the input of the read-only memory of the digital heterodyning device 30. The first output of the read-only memory of the device of digital heterodyning 30 is connected to the third input of the digital heterodyning device 29. The second output of the read-only memory digital heterodyning device 30 is connected to the fourth input of the device digital heterodyning 29.

The sixth input of the pre-processing device A3 of the first channel is connected to the second input of the second N-bit accumulating adder 33, with the second input of the first N-bit accumulating adder 32.

The seventh input of the pre-processing device A3 of the first channel is connected to the third input of the second N-bit accumulating adder 33, with the third input of the first N-bit accumulating adder 3.

The eighth input of the pre-processing device A3 of the first channel is connected to the second input of the second reverse counter 34, with the second input of the second multiplexer 38, with the input of the write address generator 37, with the second input of the first multiplexer 36, with the second input of the first reverse counter 31.

The ninth input of the pre-processing device A3 of the first channel is connected to the input of the read address generator 41, with the input of the reference signal generator 43, with the second input of the second FiFo chip 47, with the input of the control device 46, with the second input of the first FiFo 45 chip.

The tenth input of the first channel pre-processor A3 is connected to the third input of the first switch 48 and the third input of the second switch 49. The first output of the control device 46 is connected to the third input of the first FiFo 45 chip. The second output of the control device 46 is connected to the fourth input of the first FiFo 45 chip. The third output of the control device 46 is connected to the third input of the second chip FiFo 47. The fourth output of the control device 46 is connected to the fourth input of the second chip FiFo 47. The first output of the driver signal 43 is connected to the second input of the first optimal filter 42. The second output of the reference signal generator 43 is connected to the second input of the second optimal filter 44. The output of the write address generator 37 is connected to the second input of the first random access memory 39 and to the second input of the second random access memory inter-period processing devices 40. The output of the read address generator 41 is connected to the third input of the first random-access memory of the inter-period processing 39 and with the third input of the second random access memory inter-period processing 40.

The eleventh input of the pre-processing apparatus A3 of the first channel is connected to the third input of the second multiplexer 38.

Interstage communications in the quadrature phase detection device A2 of the second channel are similar to interstage communications in the quadrature phase detection device A1 of the first channel, interstage communications of the A4 preprocessing device of the second channel are similar to interstage communications in the preliminary processing apparatus A3 of the first channel.

The device for quadrature phase detection A1 of the first channel provides discrete controlled amplification of the signals, their decomposition into quadrature components (cos and sin), post-filter low-pass filtering, linking the DC component of the output signals to the midpoint of the analog-to-digital converter and monitoring the health of the device.

The device operates as follows.

The input signal from the first channel of the radar at an intermediate frequency (fpch) containing the Doppler frequency offset from the input signal of the first channel 53 is fed to the first input of the adder 9, then to the amplifier block with a temporary automatic gain control 12, which amplify the received signal. The gain of the amplifiers changes discretely according to the instructions received from the first decoder 5. The control commands to the first decoder 5 come from the signal synchronizer 50, which is controlled via the parallel information line 65. The gain of the amplifiers block is provided by a discrete change in the value of the sequential negative feedback keys on field effect transistors.

After amplifying the signal in the quadrature phase detection device, the signal frequency is converted, it is decomposed into quadrature components (cos-I quadrature and sin-II quadrature), the DC component of the output voltage is stabilized by quadrature, and the quadrature phase detection device is checked for health. The signal from the output of the amplifier block with temporary automatic gain control 12 is fed to the first input of the first frequency mixer 13 and to the first input of the second frequency mixer 14.

The formation of reference signals (local oscillators) for frequency mixers is provided by dividing the input reference signal in frequency divider 2 by two frequencies, subsequent filtering of harmonics with a bandpass filter 6, a phase shift in the differentiating and integrating circuits, and a signal amplifier in the amplifiers 10 and 11 of the local oscillator frequency.

Due to the phase shift of the signals in the differentiating and integrating circuits in opposite directions by 45 °, the phase shift of the local oscillator signals at the second inputs of the frequency mixers 13 and 14 is approximately 90 °. The amplifiers 10 and 11 of the local oscillator frequency are made resonant and the exact installation of the phase shift of the local oscillator signals equal to 90 ° is provided by tuning the resonant circuits.

From the output of the first frequency mixer 13, low-frequency signals with a frequency corresponding to the Doppler frequency shift of the input signal are summed in the first operational amplifier 15 with the voltage of the stabilization circuit of the DC component of the output signal, pass through the low-pass filter 19 and enter the real component of the first channel (ReIk ( cos)) to the second input of the first analog-to-digital converter 26 of the preliminary processing apparatus A3 of the first channel. The output signal from the second mixer 14 is processed similarly in the second operational amplifier 17, in the second low-pass filter 21 and along the imaginary component of the first channel (ImIk (sin)) to the first input of the second analog-to-digital converter 27 of the preliminary processing apparatus A3 of the first channel.

The first 19 and second 21 low-pass filters are made in the form of a fifth-order T-shaped passive filter with Butterworth approximation on LC elements with a cut-off frequency of the amplitude-frequency characteristic equal to 3 MHz.

To stabilize the DC component of the voltage of the output signal at the first output of the quadrature phase detection device (output of the I-th quadrature), the output signal passes through the first integrator 20, which has a large integration time constant, and is fed to the input of the first comparator 16, where it is compared with a potential whose value close to zero. The output signal of the first comparator is fed to the second input of the first operational amplifier and provides stabilization of the DC component of the voltage at the output of the first quadrature.

The stabilization of the DC component of the voltage of the output signal at the third output of the quadrature phase detection device (output of the 2nd quadrature) is performed similarly to the stabilization of the DC component of the voltage of the output signal of the 1st quadrature through the second integrator 22, the second comparator 18.

The transmission coefficients of the signals at the quadrature outputs in the quadrature phase detection device A1 of the first channel are the same, and the signal phases are shifted by 90 °. The first control circuit 23, the second control circuit 24 and the signal conditioning circuit 25 form a signal ″ Serviceability of the quadrature phase detection device A1 of the first channel ″.

The first monitoring circuit 23 monitors the health of the quadrature phase detection device A1 of the first channel of the real component of the signal, and the second monitoring circuit monitors the health of the imaginary component of the signal. The control is provided by a bipolar threshold check of the signal level at the output of each quadrature. In the control circuit, the signal levels at the comparators are compared with threshold voltage levels. If the signal levels exceed the threshold voltage levels, a signal is outputted to the health signal generation circuit 25. The second monitoring circuit 24 works similarly to the imaginary signal component of the first channel. If there are signals from both control circuits 23 and 24, the health signal generation circuit 25 provides a “health” signal, which is fed to the signal synchronizer 50 and fed to the output of the coherent radar receiver with optimal signal filtering via the parallel information line 65 (“Signal generation and measurement in pulsed technology ", G. M. Gontarenko, N. G. Kryzhanovskaya, publishing house of standards, 1992, p. 89).

The input signal of the second channel of the radar from the input connector of the second channel 55 is supplied to the first input of the quadrature phase detection device A2 of the second channel.

The quadrature phase detection device A2 of the second channel provides a similar signal processing of the second receiving channel and is structurally similar to the device A1.

The second decoder 4 performs functions similarly to the first decoder only for the second reception channel. From the output of the quadrature phase detection device A2 of the second channel, the real and imaginary components of the low-frequency signal are fed to the second and third inputs of the pre-processing device A4 of the second channel.

The preprocessing device A3 of the first channel performs the following operations:

- conversion of four analog input signals (Re 1k, Im 1k, Re 2k, Im 2k) into a twelve-digit code;

- produces digital heterodyning;

- provides optimal filtering of signals;

- produces channel multiplexing;

- generates correction factors for digital heterodyning;

- compensates for the constant component that occurs at the inputs of analog-to-digital converters.

Works device pre-processing A3 of the first channel as follows.

The first analog-to-digital Converter 26 converts the analog signal of the real component into digital form. The second analog-to-digital Converter 27 converts the analog signal of the imaginary component into digital form. After the analog-to-digital converters 26 and 27, the digital heterodyning device 29 performs digital heterodyning, the local oscillator frequency is set along the parallel information line with an accuracy of 0.8 Hz. The digital heterodyning device 29 performs the operation of multiplying two complex numbers:

- поступающие из аналого-цифрового преобразователя коды выборок квадратурных составляющих сигнала,Where

- the codes of samples of the quadrature components of the signal coming from the analog-to-digital converter,

K ’[i] = cos φ [i] -j sin φ [i] - correction factors coming from a digital local oscillator,

φ [i] = φ [i-1] + Δφ; Δφ is the phase incursion.

The read-only memory 30 of the digital heterodyning device is based on two read-only memory devices AT29C1024-70JI. The address for reading information from read-only memory 30 of the digital heterodyning device is continuously generated in accordance with the code Δφ. Reading the values of the correction factors occurs with the sampling frequency of the analog-to-digital Converter.

After heterodyning, the signal samples are summed over the interval of one range element

where n is the number of the range element,

the real component in the first N-bit accumulating adder 32, the imaginary component in the second N-bit accumulating adder 33.

The number of summing samples is determined by the code N _k and can take values from one to sixty three.

The first analog-to-digital converter 26 is covered by a feedback circuit consisting of a reversible counter 31 and a digital-to-analog converter 28 for balancing the DC component. The second analog-to-digital converter 27 is likewise covered by a feedback circuit consisting of a second counter counter 34 and a second digital-to-analog converter 35 for balancing the DC component. To prevent overflow of the discharge grid of drives, there are first 36 and second 38 multiplexers, the first 39 and second 40 random access memory devices are designed for information processing in the first 42 and second 44 optimal filters. The first 48 and second 49 switches supply information to the outputs of the third 51 and fourth 52 multiplexers either directly from the first 36 and second 38 multiplexers or from the first 42 and second 44 outputs of the optimal filters.

The signal synchronizer 50 generates control signals for the transmitting channel, the high-frequency receiver, which are supplied to the contacts: a pulse for generating the tuning gate of the antenna 56, a trigger signal for the finished stage of the transmitter 57, a signal that determines the duration of the trigger pulse of the transmitter 58, a signal that determines the phase of the trigger pulse of the transmitter 59 , a blanking pulse signal of the receiver 60, a pulse accompanying the main signal 61, a transmission start pulse 62, and for synchronizing the pre-processing device weave.

For temporary compression of the phase-code-manipulated signal, inter-period processing of information from the drive is used. For storing signal data of the previous measure and recording data of the current measure, two-port random access memory devices are used. The formation of write and read addresses for dual-port random access memory devices is carried out in a shaper of write addresses 37 and a shaper of read addresses 41. Shaper of reference signals 43 generates arrays of reference functions for various types of phase-code-manipulated signals. The control device 46 generates control signals of the first 45 and second 47 of the FiFo chips, depending on the operating mode of the radar.

When compressing the phase-code-manipulated signal for each element of the range, the convolution value is calculated:

N _k-1

where B [k] is the element of the array of the support function.

In order to reduce the processing time of information in the pre-processing device A1 of the first channel, sixty-four parallel-working devices for compressing phase-code-manipulated signals are used, thus information is simultaneously processed for sixty-four range elements.

The processing time of sixty-four range elements is determined by the length of the phase-code-manipulated sequence N _fkms

where F _T is the clock frequency of the compression devices, determined by the speed of the chip. In this case, F _T = 7 MHz.

причем необходимое число циклов может быть дробным числом. Данные из оптимальных фильтров 42 и 44 записываются оперативно-запоминающим устройством типа FiFo в конце каждого цикла. После обработки всех элементов дальности производится передача всего массива данных FiFo во внешнее устройство в соответствии с заданным протоколом обмена. Частота передачи определяется параметрами внешнего устройства и в данном случае после мультиплексирования составляет 14 МГц.Since the required number of range elements in the general case is more than sixty-four, phase-code-manipulated signals are compressed in several cycles

moreover, the required number of cycles can be a fractional number. Data from the optimal filters 42 and 44 are recorded by a FiFo-type random access memory at the end of each cycle. After processing all range elements, the entire FiFo data array is transferred to an external device in accordance with the specified exchange protocol. The transmission frequency is determined by the parameters of the external device and in this case, after multiplexing, is 14 MHz.

The control device controls the processes of recording information from the optimal filter in FiFo and reading information from FiFo in accordance with the specified number of range elements and the timing diagram of the optimal filter.

From the outputs of the first 42 and second 44 optimal filters, the data is recorded in the first 45 and second 47 of the FiFo chip, respectively, after the processing of all range elements is completed, the data from the first 45 and second 47 FiFo chip are fed to the output third 51 and fourth 52 multiplexers, respectively.

The pre-processing device A4 of the second channel provides similar processing of the output signal of the quadrature phase detection device A2 of the second channel, as in the pre-processing device A3 of the first channel, and is structurally similar to the pre-processing device A3 of the first channel.

The accuracy of digital correction of the quadrature of the received signals is ensured by the formation of a control signal on a crystal oscillator 3.

The dynamic range of the receiving device is expanded due to the high linearity of the amplitude characteristics of the amplifier block with temporary automatic gain control and mixers. The first 13 and second 14 mixers are made according to the key balanced circuit with the control of the local oscillator signal by the value of the sequential negative feedback in the mixer amplifiers.

The reference frequency signal for the signal synchronizer 50 is generated in the level 1 converter from the reference frequency signal coming from the input connector of the input reference signal 54.

From the third multiplexer 51, the output signal is supplied to the output signal connector of the real component 63, and from the fourth multiplexer 52, the output signal is supplied to the output signal connector of the imaginary component 64.

The application of the proposed device expands the functionality by additionally performing the following functions:

- provides control signals for the transmitting channel, the high-frequency receiver and the synchronization of the preprocessing device;

- compensates for the DC component at the inputs of the analog-to-digital converter;

- generates correction factors for digital heterodyning;

- provides optimal filtering of signals;

- produces channel multiplexing;

- produces digital heterodyning.

Improvement of the main technical parameters is carried out by increasing the dynamic range of the device and increasing accuracy with digital adjustment of the quadrature of the received signals.

According to the proposed technical solution, prototypes were made. Technical parameters are confirmed by the positive results of preliminary and flight tests.

Claims (1)

Coherent radar receiver with optimal signal filtering,  containing the first receiving channel,  which includes a quadrature phase detection device A1 and a pretreatment device A3,  wherein the quadrature phase detection device A1 of the first channel comprises an adder,  amplifier block with temporary automatic gain control,  first and second frequency mixers,  first and second operational amplifiers,    first and second voltage comparators,  first and second low-pass filters,  first and second integrators,  the first and second control schemes,  health signal generation circuit,  in turn,  the pre-processing device A3 of the first channel consists of the first and second analog-to-digital converters,  first and second digital-to-analog converters,  digital heterodyne devices,  read only memory device digital heterodyne,  first and second reversible counters,  the first and second accumulating N-bit adders,  first and second multiplexers,  shaper of the address of the record,  first and second random-access memory  read address driver  first and second optimal filters,  reference signal driver,  the first and second FiFo chips “the first came in,  first out ”  control devices  first and second switches,  wherein the second receiving channel comprises a quadrature phase detection device A2 and a preprocessing device A4,  which are structurally similar to the quadrature phase detection device A1 of the first channel and the preliminary processing device A3 of the first channel,  and it also includes the first and second decoders,  crystal oscillator  level converter  frequency divider,  bandpass filter  differentiating chain  integrating chain  first and second resonant amplifiers,  third and fourth multiplexers and signal synchronizer,  wherein the input of the receiver through the first channel is connected to the first input of the quadrature phase detection device A1 of the first channel,  the first output of the quadrature phase detection device A1 of the first channel is connected to the second input of the preliminary processing device A3 of the first channel,  the first output of the pre-processing device A3 of the first channel is connected to the first input of the third multiplexer,  the output of the third multiplexer is connected to the connector of the output signal of the real component,  the input reference signal connector is connected to the input of the frequency divider and the input of the level converter,  the output of the frequency divider is connected to the input of the bandpass filter,  the output of the bandpass filter is connected to the input of the differentiating chain and the input of the integrating chain,  the output of the differentiating circuit is connected to the input of the first resonant amplifier,  the first output of the first resonant amplifier is connected to the second input of the quadrature phase detection device A1 of the first channel,  the second output of the first resonant amplifier is connected to the second input of the quadrature phase detection device A2 of the second channel,  the output of the integrating circuit is connected to the input of the second resonant amplifier,  the first output of the second resonant amplifier is connected to the third input of the quadrature phase detection device A1 of the first channel,  the second output of the second resonant amplifier is connected to the third input of the quadrature phase detection device A2 of the second channel,  the first output of the quadrature phase detection device A2 of the second channel is connected to the second input of the pre-processing device A4 of the second channel,  the first output of the pre-processing device A4 of the second channel is connected to the second input of the fourth multiplexer,  the output of the fourth multiplexer is connected to the output connector of the imaginary component,  the first output of the signal synchronizer is connected to the input of the crystal oscillator,  the first output of the crystal oscillator is connected to the fourth input of the quadrature phase detection device A1 of the first channel,  the second output of the crystal oscillator is connected to the fourth input of the quadrature phase detection device A2 of the second channel,  the second output of the signal synchronizer is connected to the input of the first decoder,  the output of the first decoder is connected to the fifth input of the quadrature phase detection device A1 of the first channel,  the third output of the signal synchronizer is connected to the input of the second decoder,  the output of the second decoder is connected to the fifth input of the quadrature phase detection device A2 of the second channel,  the output of the level converter is connected to the first input of the signal synchronizer,  the second output of the quadrature phase detection device A2 of the second channel is connected to the third input of the signal synchronizer,  the third output of the quadrature phase detection device A2 of the second channel is connected to the third input of the pre-processing device A4 of the second channel,  the second output of the quadrature phase detection device A1 of the first channel is connected to the second input of the signal synchronizer,  the third output of the quadrature phase detection device A1 of the first channel is connected to the third input of the preliminary processing device A3 of the first channel,  the fifth output of the signal synchronizer is connected to the fourth input of the pre-processing device A4 of the second channel,  the sixth output of the signal synchronizer is connected to the fifth input of the pre-processing device A4 of the second channel,  the seventh output of the signal synchronizer is connected to the sixth input of the pre-processing device A4 of the second channel,  the eighth output of the signal synchronizer is connected to the seventh input of the pre-processing device A4 of the second channel,  the ninth output of the signal synchronizer is connected to the eighth input of the pre-processing device A4 of the second channel,  the tenth output of the signal synchronizer is connected to the ninth input of the pre-processing device A4 of the second channel,  the eleventh output of the signal synchronizer is connected to the pulse contact to form the antenna tuning gate,  the twelfth output of the signal synchronizer is connected to the contact of the trigger signal of the final stage of the transmitter,  the thirteenth output of the signal synchronizer is connected to a signal contact determining the duration of the transmitter start pulse,  the fourteenth output of the signal synchronizer is connected to the signal contact determining the phase of the trigger pulse of the transmitter,  the fifteenth output of the signal synchronizer is connected to the contact signal of the pulse blanking receiver,  the sixteenth output of the signal synchronizer is connected to the pulse contact accompanying the main signal,  the seventeenth output of the signal synchronizer is connected to the contact of the pulse start transmission,  the eighteenth output of the signal synchronizer is connected to the tenth input of the pre-processing device A4 of the second channel,  the nineteenth output of the signal synchronizer is connected to the third input of the third multiplexer and the third input of the fourth multiplexer,  the twentieth output of the signal synchronizer is connected to the fourth input of the preliminary processing device A3 of the first channel,  the twenty-first output of the signal synchronizer is connected to the fifth input of the preliminary processing device A3 of the first channel,  the twenty-second output of the signal synchronizer is connected to the sixth input of the preliminary processing device A3 of the first channel,  the twenty-third output of the signal synchronizer is connected to the seventh input of the preliminary processing device A3 of the first channel,  the twenty-fourth output of the signal synchronizer is connected to the eighth input of the preliminary processing device A3 of the first channel,  the twenty-fifth output of the signal synchronizer is connected to the ninth input of the pre-processing device A3 of the first channel,  the twenty-sixth output of the signal synchronizer is connected to the tenth input of the preliminary processing device A3 of the first channel,  a parallel information trunk connector is connected to the first and eleventh inputs of the preprocessing apparatus A3 of the first channel,  with the first and eleventh inputs of the pre-processing device A4 of the second channel,  and with the fourth output of the signal synchronizer,  the second output of the pre-processing device A3 of the first channel is connected to the first input of the fourth multiplexer,  the second output of the pre-processing device A4 of the second channel is connected to the second input of the third multiplexer,  in the quadrature phase detection device A1 of the first channel, the first input is connected to the first input of the adder,  the output of the adder is connected to the first input of the amplifier block with temporary automatic gain control,  the output of the amplifier block with temporary automatic gain control is connected to the first input of the first frequency mixer and to the first input of the second frequency mixer,  the output of the first frequency mixer is connected to the first input of the first operational amplifier,  the output of the first operational amplifier is connected to the input of the first low-pass filter,  the output of the first low pass filter is connected to the first output of the quadrature phase detection device A1 of the first channel,  with the input of the first control circuit and with the input of the first integrator,  the output of the first integrator is connected to the input of the first voltage comparator,  the output of the first voltage comparator is connected to the second input of the first operational amplifier,  the output of the second frequency mixer is connected to the first input of the second operational amplifier,  the output of the second operational amplifier is connected to the input of the second low-pass filter,  the output of the low-pass filter is connected to the third output of the quadrature phase detection device A1 of the first channel,  with the input of the second control circuit and with the input of the second integrator,  the output of the second integrator is connected to the input of the second voltage comparator,  the output of the second voltage comparator is connected to the second input of the second operational amplifier,  the output of the first control circuit is connected to the first input of the health signal generating circuit,  the output of the second control circuit is connected to the second input of the health signal generating circuit,  the output of the health signal generating circuit is connected to the second output of the quadrature phase detection device A1 of the first channel,  the fourth input of the quadrature phase detection device A1 of the first channel is connected to the second input of the adder,  the second input of the quadrature phase detection device A1 of the first channel is connected to the second input of the first frequency mixer,  the third input of the quadrature phase detection device A1 of the first channel is connected to the second input of the second frequency mixer,  the fifth input of the quadrature phase detection device A1 of the first channel is connected to the second input of the amplifier block with temporary automatic gain control,  the input channel of the second channel is connected to the first input of the quadrature phase detection device A2 of the second channel,  the first input of the pre-processing device A3 of the first channel is connected to the third input of the first multiplexer,  the second input of the pre-processing device A3 of the first channel is connected to the second input of the first analog-to-digital converter,  the output of the first analog-to-digital converter is connected to the fifth input of the digital heterodyning device,  the first output of the digital heterodyning device is connected to the first input of the first N-bit accumulating adder,  the first output of the first N-bit accumulating adder is connected to the first input of the first multiplexer,  the output of the first multiplexer is connected to the first input of random access memory and to the second input of the first switch,  the output of the first random-access memory is connected to the first input of the optimal filter,  the output of the first optimal filter is connected to the first input of the first FiFo chip,  the output of the first FiFo chip is connected to the first input of the first voltage switch,  the output of the first voltage switch is connected to the first output of the preliminary processing device A3 of the first channel,  the third input of the pre-processing device A3 of the first channel is connected to the first input of the second analog-to-digital converter,  the output of the second analog-to-digital converter is connected to the second input of the digital heterodyning device,  the second output of the digital heterodyning device is connected to the first input of the second N-bit accumulating adder,  the first output of the second N-bit accumulating adder is connected to the first input of the second multiplexer,  the output of the second multiplexer is connected to the first input of the second random-access memory and to the second input of the second switch,  the output of the second random-access memory is connected to the first input of the second optimal filter,  the output of the second optimal filter is connected to the first input of the second FiFo chip,  the output of the second FiFo chip is connected to the first input of the second switch,  the output of the second switch is connected to the second output of the pre-processing device A3 of the first channel,  the second output of the first N-bit accumulating adder is connected to the first input of the first reversible counter,  the output of the first reversible counter is connected to the input of the first digital-to-analog converter,  the output of the first digital-to-analog converter is connected to the first input of the first analog-to-digital converter,  the second output of the second N-bit accumulating adder is connected to the first input of the second reversible counter,  the output of the second reversible counter is connected to the input of the second digital-to-analog converter,  the output of the second digital-to-analog converter is connected to the second input of the second analog-to-digital converter,  the fourth input of the pre-processing device A3 of the first channel is connected to the third input of the second analog-to-digital converter,  with the third input of the first analog-to-digital converter,  with the first input of the digital heterodyning device,  the fifth input of the first channel processing apparatus A3 of the first channel is connected to the input of the read-only memory of the digital heterodyning device,  the first output of the read-only memory of the digital heterodyning device is connected to the third input of the digital heterodyning device,  the second output of read-only memory of the digital heterodyning device is connected to the fourth input of the digital heterodyning device,  the sixth input of the pre-processing device A3 of the first channel is connected to the second input of the second N-bit accumulating adder and to the second input of the first N-bit accumulating adder,  the seventh input of the pre-processing device A3 of the first channel is connected to the third input of the second N-bit accumulating adder and to the third input of the first N-bit accumulating adder,  the eighth input of the pre-processing device A3 of the first channel is connected to the second input of the second reversible counter,  with the second input of the second multiplexer,  with the input of the address generator of the record,  with the second input of the first multiplexer and with the second input of the first reversible counter,  the ninth input of the preprocessing device A3 of the first channel is connected to the input of the read address generator,  with the input of the driver of the reference signals,  with the second input of the second FiFo chip,  with the input of the control device and with the second input of the first FiFo chip,  the tenth input of the pre-processing device A3 of the first channel is connected to the third input of the first switch and the third input of the second switch,  the first output of the control device is connected to the third input of the first FiFo chip,  the second output of the control device is connected to the fourth input of the first FiFo chip,  the third output of the control device is connected to the third input of the second FiFo chip,  the fourth output of the control device is connected to the fourth input of the second FiFo chip,  the first output of the driver of the reference signals is connected to the second input of the first optimal filter,  the second output of the driver of the reference signals is connected to the second input of the second optimal filter,  the output of the recording address generator is connected to the second input of the first random access memory of the inter-period processing and the second input of the second random access memory of the inter-period processing,  the output of the read address generator is connected to the third input of the first random access memory of the inter-period processing and to the third input of the second random access memory of the inter-period processing,  the eleventh input of the pre-processing device A3 of the first channel is connected to the third input of the second multiplexer,  interstage communications in the quadrature phase detection device A2 of the second channel are similar to interstage communications in the quadrature phase detection device A1 of the first channel,  interstage communications of the pre-processing device A4 of the second channel are similar to interstage communications in the pre-processing device A3 of the first channel.

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