RU2273860C2 - Coherent receiver of a radiolocation station with a digital arrangement for amplitude and phase adjusting of quadrature component of a receiving signal - Google Patents

Abstract

FIELD: the invention refers to the technique of processing signals of radiolocation stations.

SUBSTANCE: the essence of the invention is in providing controlled intensification, frequency transformation, disintegration on quadrature components, analog-digital conversion of signals, providing identity of amplitude and phase characteristics of an imaginary and a real component of a signal, digital oscillating, storing, optimal filtration (compression of phase-code-manipulated signals) entering from a high frequency receiver.

EFFECT: expansion of functional possibilities and improving main technical parameters of a radiolocation station.

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Description

The invention relates to techniques for processing signals of radar stations (radar).

The incoherent receiver (USSR Author's Certificate No. 1525933, H 04 L 17/30, 1989) with increased noise immunity is known from the prior art, but it does not process the phase structure of the signal.

A device for recognizing moving objects is known (RF Certificate for Utility Model No. 21250, G 01 K 9/00, 2001), which determines the class of an object, but does not solve the problem of expanding the dynamic range of the receiver.

A coherent radar receiver (RF application for invention No.2000120020, bulletin "Inventions, utility models" No. 16, 2002, p. 126) does not provide digital heterodyning of the processed signal and has an error when digitally adjusting the quadrature of the received signals.

The closest in technical essence is an incoherent signal detector in noise (RF Application for invention No.200102468, bulletin "Inventions, utility models" No. 8, 2002, p. 71), including an incoherent local oscillator, phase-shifting circuit, analog-to-digital converter, the first and second frequency mixers, first and second intermediate frequency filters, the first inputs of the mentioned mixers are connected to the signal input, the second input of the first mixer is connected to the local oscillator output through a phase-shifting chain, the second input of the second mixer the frequency is also connected to the output of the local oscillator, the outputs of the first and second mixers are connected to the inputs of the first and second filters of the intermediate frequency, respectively, the first and second voltage comparators are introduced into the circuit, an exclusive OR logic circuit, a 2n counter-divider, an N-bit accumulating adder , the third comparator of numbers and the m-bit register, the output of one of the intermediate frequency filters is connected to the signal input of an analog-to-digital converter and the non-inverting input of the first voltage comparator, the output to The second filter is connected to the non-inverting input of the second voltage comparator, the inverting inputs of the said comparators are connected to zero potential, the outputs of the first and second comparators are connected to the first and second inputs of the exclusive OR circuit, the output of the mentioned circuit is connected to the clock input of the analog-to-digital converter and with the input of the counter-divider by n, the digital output bus of the aforementioned analog-to-digital converter without sign discharge is connected to the input of the N-bit accumulating the adder, m = Nn of the output high-order bits of the accumulating adder are connected to the input of the third number comparator, the second input of the third number comparator is connected to the output of the m-bit register, into which the binary threshold code is written, the control input of the said number comparator is connected to the output of the said divider counter by n

However, when using it, it does not ensure the identity of the amplitude, phase characteristics of the signal by quadratures, which will lead to a high level of the mirror component of the signal during digital heterodyning in the receiver and coherent processing of the received signal, since this is not provided for in the circuit design in the known technical solution.

The technical result of the proposed technical solution is aimed at expanding the functionality and improving the basic technical parameters of the radar.

The technical result is achieved by  that the coherent radar receiver with a digital device for amplitude and phase adjustment of the quadrature components of the received signal contains a first analog-to-digital converter,  first and second frequency mixers,  first N-bit accumulating adder,  first and second voltage comparators,  and the first receiving channel includes a quadrature phase detection device of the first channel and a preliminary processing device of the first channel,  wherein the device quadrature phase detection of the first channel contains an adder,  amplifier block with temporary automatic gain control,  first and second frequency mixers,  first and second operational amplifiers,  first and second voltage comparators,  first and second low-pass filters,  first and second integrators,  the first and second control schemes,  health signal generation circuit,  in turn, the first channel pre-processing device consists of the first and second analog-to-digital converter,  first and second digital-to-analog converters,  the first and second device for adjusting the coefficients,  digital heterodyne devices,  read only memory device digital heterodyne,  first and second reversible counters,  the first and second accumulating N-bit adders,  first and second multiplexers,  shaper of the address of the record,  first and second random access memory devices,  read address driver  first and second optimal filters,  reference signal driver,  the first and second FiFo chips "the first came in,  first out, "  control devices  first and second switches,  wherein the second receiving channel comprises a quadrature phase detection device for the second channel and a preliminary processing device for the second channel,  which are structurally similar to the quadrature phase detection device of the first channel and the preliminary processing device of the first channel,  as well as in the coherent radar receiver with a digital device for amplitude and phase correction of the quadrature components of the received signal, the first and second decoders are included,  crystal oscillator  level converter  frequency divider,  bandpass filter  differentiating chain  integrating chain  first and second resonant amplifiers,  third and fourth multiplexers,  signal synchronizer  wherein the input of the receiver through the first channel is connected to the first input of the quadrature phase detection device of the first channel,  the first output of the quadrature phase detection device of the first channel is connected to the second input of the first channel preprocessing device,  the first output of the pre-processing device of the first channel is connected to the first input of the third multiplexer,  the output of the third multiplexer is connected to the connector of the output signal of the real component,  the input reference signal connector is connected to the input of the frequency divider and the input of the level converter,  the output of the frequency divider is connected to the input of the bandpass filter,  the output of the bandpass filter is connected to the input of the differentiating chain and the input of the integrating chain,  the output of the differentiating circuit is connected to the input of the first resonant amplifier,  the first output of the resonant amplifier is connected to the second input of the quadrature phase detection device of the first channel,  the second output of the first resonant amplifier is connected to the second input of the quadrature phase detection device of the second channel,  the output of the integrating circuit is connected to the input of the second resonant amplifier,  the first output of the second resonant amplifier is connected to the third input of the quadrature phase detection device of the first channel,  the second output of the second resonant amplifier is connected to the third input of the quadrature phase detection device of the second channel,  the first output of the quadrature phase detection device of the second channel is connected to the second input of the second channel preprocessing device,  the first output of the pre-processing device of the second channel is connected to the second input of the fourth multiplexer,  the output of the fourth multiplexer is connected to the output connector of the imaginary component,  the first output of the signal synchronizer is connected to the input of the crystal oscillator,  the first output of the crystal oscillator is connected to the fourth input of the quadrature phase detection device of the first channel,  the second output of the crystal oscillator is connected to the fourth input of the quadrature phase detection device of the second channel,  the second output of the signal synchronizer is connected to the input of the first decoder,  the output of the first decoder is connected to the fifth input of the quadrature phase detection device of the first channel,  the third output of the signal synchronizer is connected to the input of the second decoder,  the output of the second decoder is connected to the fifth input of the quadrature phase detection device of the second channel,  the output of the level converter is connected to the first input of the signal synchronizer,  the second output of the quadrature phase detection device of the second channel is connected to the third input of the signal synchronizer,  the third output of the quadrature phase detection device of the second channel is connected to the third input of the preliminary processing device of the second channel,  the second output of the quadrature phase detection device of the first channel is connected to the second input of the signal synchronizer,  the third output of the quadrature phase detection device of the first channel is connected to the third input of the preliminary processing device of the first channel,  the fifth output of the signal synchronizer is connected to the fourth input of the preliminary processing device of the second channel,  the sixth output of the signal synchronizer is connected to the fifth input of the pre-processing device of the second channel,  the seventh output of the signal synchronizer is connected to the sixth input of the pre-processing device of the second channel,  the eighth output of the signal synchronizer is connected to the seventh input of the preliminary processing device of the second channel,  the ninth output of the signal synchronizer is connected to the eighth input of the pre-processing device of the second channel,  the tenth output of the signal synchronizer is connected to the ninth input of the pre-processing device of the second channel,  the eleventh output of the signal synchronizer is a pulse output for forming the antenna tuning gate,  the twelfth output of the signal synchronizer is the output of the trigger signal of the final stage of the transmitter,  the thirteenth output of the signal synchronizer is a signal output,  determining the duration of the start pulse of the transmitter,  the fourteenth output of the signal synchronizer is a signal output,  determining the phase of the transmitter trigger pulse,  the fifteenth output of the signal synchronizer is the output signal of the pulse blanking receiver,  the sixteenth output of the signal synchronizer is a pulse output,  accompanying the main signal,  the seventeenth output of the signal synchronizer is the output of the transmission start pulse,  the eighteenth output of the signal synchronizer is connected to the tenth input of the preliminary processing device of the second channel,  the nineteenth output of the signal synchronizer is connected to the third input of the third multiplexer and the third input of the fourth multiplexer,  the twentieth output of the signal synchronizer is connected to the fourth input of the first channel preprocessing device,  the twenty-first output of the signal synchronizer is connected to the fifth input of the pre-processing device of the first channel,  the twenty-second output of the signal synchronizer is connected to the sixth input of the preliminary processing device of the first channel,  the twenty-third output of the signal synchronizer is connected to the seventh input of the pre-processing device of the first channel,  the twenty-fourth output of the signal synchronizer is connected to the eighth input of the first channel preprocessing device,  the twenty-fifth output of the signal synchronizer is connected to the ninth input of the first channel preprocessing device,  the twenty-sixth output of the signal synchronizer is connected to the tenth input of the first channel preprocessing device,  the parallel information trunk connector is connected in parallel with the first,  eleventh  the twelfth  the thirteenth inputs of the pre-processing device of the first channel and with the first,  eleventh  the twelfth  the thirteenth inputs of the pre-processing device of the second channel and with the fourth output of the signal synchronizer,  the second output of the first channel pre-processing device is connected to the first input of the fourth multiplexer,  the second output of the pre-processing device of the second channel is connected to the second input of the third multiplexer,  in the quadrature phase detection device of the first channel, the first input is connected to the first input of the adder,  the output of the adder is connected to the first input of the amplifier block with temporary automatic gain control,  the output of the amplifier block with temporary automatic gain control is connected to the first input of the first frequency mixer and to the first input of the second frequency mixer,  the output of the first frequency mixer is connected to the first input of the first operational amplifier,  the output of the first operational amplifier is connected to the input of the first low-pass filter,  the output of the first low pass filter is connected to the first output of the quadrature phase detection device of the first channel,  with the input of the first control circuit and with the input of the first integrator,  the output of the first integrator is connected to the input of the first voltage comparator,  the output of the first voltage comparator is connected to the second input of the first operational amplifier,  the output of the second frequency mixer is connected to the first input of the second operational amplifier,  the output of the second operational amplifier is connected to the input of the second low-pass filter,  the output of the second low-pass filter is connected to the third output of the quadrature phase detection device of the first channel,  with the input of the second control circuit and with the input of the second integrator,  the output of the second integrator is connected to the input of the second voltage comparator,  the output of the second voltage comparator is connected to the second input of the second operational amplifier,  the output of the first control circuit is connected to the first input of the health signal generating circuit,  the output of the second control circuit is connected to the second input of the health signal generating circuit,  the output of the health signal generating circuit is connected to the second output of the quadrature phase detection device of the first channel,  the fourth input of the quadrature phase detection device of the first channel is connected to the second input of the adder,  the second input of the quadrature phase detection device of the first channel is connected to the second input of the first frequency mixer,  the third input of the quadrature phase detection device of the first channel is connected to the second input of the second frequency mixer,  the fifth input of the quadrature phase detection device of the first channel is connected to the second input of the amplifier block with temporary automatic gain control,  the input signal of the second channel is connected to the first input of the phase detection device of the second channel,  the first input of the first channel preprocessing device is connected to the third input of the first multiplexer,  the second input of the pre-processing device of the first channel is connected to the second input of the first analog-to-digital converter,  the output of the first analog-to-digital converter is connected to the first input of the first coefficient correction device,  the output of the first coefficient correction device is connected to the fifth input of the digital heterodyning device,  the first output of the digital heterodyning device is connected to the first input of the first N-bit accumulating adder,  the first output of the first N-bit accumulating adder is connected to the first input of the first multiplexer,  the output of the first multiplexer is connected to the first input of random access memory and to the second input of the first switch,  the output of the first random-access memory is connected to the first input of the optimal filter,  the output of the first optimal filter is connected to the first input of the first FiFo chip,  the output of the first FiFo chip is connected to the first input of the first voltage switch,  the output of the first voltage switch is connected to the first output of the pre-processing device of the first channel,  the third input of the pre-processing device of the first channel is connected to the first input of the second analog-to-digital converter,  the output of the second analog-to-digital converter is connected to the first input of the second coefficient correction device,  the output of the second coefficient correction device is connected to the second input of the digital heterodyning device,  the second output of the digital heterodyning device is connected to the first input of the second N-bit accumulating adder,  the first output of the second N-bit accumulating adder is connected to the first input of the second multiplexer,  the output of the second multiplexer is connected to the first input of the second random-access memory and to the second input of the second switch,  the output of the second random-access memory is connected to the first input of the second optimal filter,  the output of the second optimal filter is connected to the first input of the second FiFo chip,  the output of the second FiFo chip is connected to the first input of the second switch,  the output of the second switch is connected to the second output of the pre-processing device of the first channel,  the second output of the first N-bit accumulating adder is connected to the first input of the first reversible counter,  the output of the first reversible counter is connected to the input of the first digital-to-analog converter,  the output of the first digital-to-analog converter is connected to the first input of the first analog-to-digital converter,  the second output of the second N-bit accumulating adder is connected to the first input of the second reversible counter,  the output of the second reversible counter is connected to the input of the second digital-to-analog converter,  the output of the second digital-to-analog converter is connected to the second input of the analog-to-digital converter,  the fourth input of the first channel pre-processing device is connected in parallel with the third input of the second analog-to-digital converter,  with the third input of the first analog-to-digital converter,  with the first input of the digital heterodyning device,  with the third input of the second coefficient correction device,  with the third input of the first coefficient correction device,  the fifth input of the first channel pre-processing device is connected to the input of the read-only memory of the digital heterodyning device,  the first output of the read-only memory of the digital heterodyning device is connected to the third input of the digital heterodyning device,  the second output of the digital memorization device is connected to the fourth input of the digital heterodyning device,  the sixth input of the pre-processing device of the first channel is connected to the second input of the second N-bit accumulating adder and to the second input of the first N-bit accumulating adder,  the seventh input of the pre-processing device of the first channel is connected to the third input of the second N-bit accumulating adder and to the third input of the first N-bit accumulating adder,  the eighth input of the pre-processing device of the first channel is connected to the second input of the second reverse counter,  with the second input of the second multiplexer,  with the input of the address generator of the record,  with the second input of the first multiplexer and with the second input of the first reversible counter,  the ninth input of the preprocessing device of the first channel is connected to the input of the read address generator,  with the input of the driver of the reference signals,  with the second input of the second FiFo chip,  with the input of the control device and with the second input of the first FiFo chip,  the tenth input of the first channel pre-processing device is connected to the third input of the first switch and the third input of the second switch,  the first output of the control device is connected to the third input of the first FiFo chip,  the second output of the control device is connected to the fourth input of the first FiFo chip,  the third output of the control device is connected to the third input of the second FiFo chip,  the fourth output of the control device is connected to the fourth input of the second FiFo chip,  the first output of the driver of the reference signals is connected to the second input of the first optimal filter,  the second output of the driver of the reference signals is connected to the second input of the second optimal filter,  the output of the recording address generator is connected to the second input of the first random access memory of the inter-period processing and the second input of the second random access memory of the inter-period processing,  the output of the read address generator is connected to the third input of the first random-access memory and the third input of the second random-access memory,  the eleventh input of the first channel pre-processing device is connected to the third input of the second multiplexer,  interstage communications in the quadrature phase detection device of the second channel are similar to interstage communications in the quadrature phase detection device of the first channel,  interstage communications of the pre-processing device of the second channel are similar to interstage communications in the pre-processing device of the first channel.

Distinctive features of the prototype is that the first receiving channel includes a quadrature phase detection device and a preprocessing device, while the quadrature phase detection device of the first channel includes an adder, an amplifier unit with automatic time gain control, first and second frequency mixers, first and second operational amplifiers, the first and second voltage comparators, the first and second low-pass filters, the first and second integrators, the first and second circuits to The monitoring circuit and the health signal generation circuit, in turn, the first channel pre-processing device consists of the first and second analog-to-digital converters, the first and second coefficient correction devices, the first and second digital-to-analog converters, the digital heterodyning device, read-only memory of the digital heterodyning device, the first and the second reversible counters, the first and second accumulating adders, the first and second multiplexers, form of a write address switcher, first and second random access memory devices, a read address shaper, first and second optimal filters, a reference signal shaper, first and second FiFo microcircuits “first entered, first left”, control devices, first and second switches, while the second receiving channel comprises a quadrature phase detection device for the second channel and a second channel preprocessing device, which are structurally similar to the device The first and second decoders, a crystal oscillator, a level converter, a frequency divider, a band-pass filter, a differentiating circuit, an integrating circuit, the first and second ones, are included in the phase-shift phase detection of the first channel and the first channel pre-processor, with a coherent radar receiver with optimal signal filtering resonant amplifiers, third and fourth multiplexers, a signal synchronizer and new interstage communications between them.

The proposed technical solution provides controlled amplification, frequency conversion, decomposition into quadrature components, analog-to-digital signal conversion, identity of the amplitude and phase characteristics of the imaginary and real components of the signal, digital heterodyning, accumulation, optimal filtering (compression of phase-coded signals) coming from a high-frequency radar receiver .

Figure 1 shows the functional electrical diagram of the proposed device, figure 2 is the same, continued figure 1, figure 3 shows the timing diagrams of the operation of the device in the presence of the command "On. frequency adjustment strobe. "

A coherent radar receiver with a digital device for amplitude and phase correction of the quadrature components of the received signal contains the first and second reception channels.

The first receiving channel includes a quadrature phase detection device for the first channel and a first channel preprocessing device, while the quadrature phase detection device for the first channel includes an adder 9, an amplifier unit with temporarily automatic gain control 12, the first 13 and second 14 frequency mixers, the first 15 and second 17 operational amplifiers, first 16 and second 18 voltage comparators, first 19 and second 21 low-pass filters, first 20 and second 22 integrators, first 23, second 24 control circuits For the operational signal generation circuit 25. In turn, the first channel pre-processing device consists of the first 26 and second 27 analog-to-digital converters, the first 66 and second 67 of the coefficient correction device, the first 28 and second 35 digital-to-analog converters, the digital heterodyning device 29, permanent storage device digital heterodyne 30, the first 31 and second 34 reverse counters, the first 32 and second 33 N-bit accumulative adders, the first 36 and There are 38 multiplexers, a write address generator 37, the first 39 and 40 second random-access memory, a read address generator 41, the first 42 and a second 44 optimal filters, reference signal conditioner 43, the first 45 and second 47 FiFo chips ("the first one entered, first came out "), control devices 46, first 48 and second 49 switches.

The second receiving channel comprises a quadrature phase detection device for the second channel and a second channel pre-processing device, which are structurally similar to the first channel quadrature phase detection device and the first channel pre-processing device.

The coherent radar receiver with a digital device for amplitude and phase correction of the quadrature components of the received signal includes the first 5 and second 4 decoders, a crystal oscillator 3, a level converter 1, a frequency divider 2, a bandpass filter 6, a differentiating circuit 7, an integrating circuit 8, the first 10 and the second 11 resonant amplifiers, the third 51 and fourth 52 multiplexers and a signal synchronizer 50.

The coherent receiver also contains a first channel input signal connector 53, an input reference signal connector 54, a second channel input signal connector 55, a pulse contact for generating an antenna tuning gate 56, a terminal signal for triggering the terminal stage of the transmitter 57, a signal contact for determining the duration of the transmitter start pulse 58 , the contact of the signal that determines the phase of the start pulse of the transmitter 59, the contact of the signal of the pulse blanking receiver 60, the contact of the pulse accompanying the main signal 61, the contact imp bca start transmission 62, the output connector real component 63, output connector 64 and the imaginary component of the parallel data highway 65.

The input signal connector of the first channel 53 is connected to the first input of the quadrature phase detection device of the first channel. The first output of the quadrature phase detection device of the first channel is connected to the second input of the first channel preprocessing device. The first output of the pre-processing device of the first channel is connected to the first input of the third multiplexer 51.

The output of the third multiplexer 51 is connected to the output signal connector of the real component 63. The input reference signal connector 54 is connected to the input of the frequency divider 2 and the input of the level converter 1. The output of the frequency divider 2 is connected to the input of the bandpass filter 6. The output of the bandpass filter 6 is connected to the input of the differentiating circuit 7 and the input of the integrating chain 8. The output of the differentiating chain 7 is connected to the input of the first resonant amplifier 10. The first output of the resonant amplifier 10 is connected to the second input of the quadrature device first phase detection of the first channel.

The second output of the first resonant gain 10 is connected to the second input of the quadrature phase detection device of the second channel. The output of the integrating circuit 8 is connected to the input of the second resonant amplifier 11. The first output of the second resonant amplifier 11 is connected to the third input of the quadrature phase detection device of the first channel. The second output of the second resonant amplifier 11 is connected to the third input of the quadrature phase detection device of the second channel.

The input connector of the second channel 55 is connected to the first input of the quadrature phase detection device of the second channel. The first output of the quadrature phase detection device of the second channel is connected to the second input of the second channel preprocessing device.

The first output of the second channel pre-processing device is connected to the second input of the fourth multiplexer 52. The output of the fourth multiplexer 52 is connected to the output signal connector of the imaginary component 64.

The first output of the signal synchronizer 50 is connected to the input of the crystal oscillator 3. The first output of the crystal oscillator 3 is connected to the fourth input of the quadrature phase detection device of the first channel. The second output of the crystal oscillator 3 is connected to the fourth input of the quadrature phase detection device of the second channel.

The second output of the signal synchronizer 50 is connected to the input of the first decoder 5. The output of the first decoder 5 is connected to the fifth input of the quadrature phase detection device of the first channel.

The third output of the signal synchronizer 50 is connected to the input of the second decoder 4. The output of the second decoder 4 is connected to the fifth input of the quadrature phase detection device of the second channel. The output of the level 1 converter is connected to the first input of the signal synchronizer 50. The second output of the quadrature phase detection device of the second channel is connected to the third input of the signal synchronizer 50. The third output of the quadrature phase detection device of the second channel is connected to the third input of the second channel preprocessing device.

The second output of the quadrature phase detection device of the first channel is connected to the second input of the signal synchronizer 50.

The third output of the quadrature phase detection device of the first channel is connected to the third input of the first channel preprocessing device.

The fifth output of the signal synchronizer 50 is connected to the fourth input of the second channel preprocessing device.

The sixth output of the signal synchronizer 50 is connected to the fifth input of the pre-processing device of the second channel.

The seventh output of the signal synchronizer 50 is connected to the sixth input of the pre-processing device of the second channel.

The eighth output of the signal synchronizer 50 is connected to the seventh input of the pre-processing device of the second channel.

The ninth output of the signal synchronizer 50 is connected to the eighth input of the second channel preprocessing device.

The tenth output of the signal synchronizer 50 is connected to the ninth input of the pre-processing device of the second channel.

The eleventh output of the signal synchronizer 50 is connected to a pulse contact to form a tuning gate of the antenna 56.

The twelfth output of the signal synchronizer 50 is connected to the contact of the trigger signal of the final stage of the transmitter 57.

The thirteenth output of the signal synchronizer 50 is connected to a signal contact that determines the duration of the start pulse of the transmitter 58.

The fourteenth output of the signal synchronizer 50 is connected to a signal contact that defines the phase of the start pulse of the transmitter 59.

The fifteenth output of the signal synchronizer 50 is connected to the contact of the signal of the pulse blanking receiver 60.

The sixteenth output of the signal synchronizer 50 is connected to a pulse contact accompanying the main signal 61.

The seventeenth output of the signal synchronizer 50 is connected to the contact of the transmission start pulse 62.

The eighteenth output of the signal synchronizer 50 is connected to the tenth input of the second channel preprocessing device.

The nineteenth output of the signal synchronizer 50 is connected to the third input of the third multiplexer 51 and the third input of the fourth multiplexer 52.

The twentieth output of the signal synchronizer 50 is connected to the fourth input of the first channel preprocessing device.

The twenty-first output of the signal synchronizer 50 is connected to the fifth input of the first channel preprocessing device.

The twenty-second output of the signal synchronizer 50 is connected to the sixth input of the first channel preprocessing device.

The twenty-third output of the signal synchronizer 50 is connected to the seventh input of the first channel preprocessing device.

The twenty-fourth output of the signal synchronizer 50 is connected to the eighth input of the first channel preprocessing device.

The twenty-fifth output of the signal synchronizer 50 is connected to the ninth input of the first channel preprocessing device.

The twenty-sixth output of the signal synchronizer 50 is connected to the tenth input of the first channel preprocessing device.

The parallel information highway connector 65 is connected in parallel with the first, eleventh, twelfth, thirteenth inputs of the first channel preprocessing device and with the first, eleventh, twelfth, thirteenth inputs of the second channel preprocessing device and the fourth output of the signal synchronizer 50.

The second output of the first channel pre-processing device is connected to the first input of the fourth multiplexer 52.

The second output of the second channel pre-processing device is connected to the second input of the third multiplexer 51.

In the quadrature phase detection device of the first channel, the first input is connected to the first input of the adder 9. The output of the adder 9 is connected to the first input of the amplifier block with temporary automatic gain control 12. The output of the amplifier block with temporary automatic gain control is connected to the first input of the first frequency mixer 13 and the first input of the second frequency mixer 14.

The output of the first frequency mixer 13 is connected to the first input of the first operational amplifier 15. The output of the first operational amplifier 15 is connected to the input of the first low-pass filter 19. The output of the first low-pass filter 19 is connected to the first output of the quadrature phase detection device of the first channel, with the input of the first control circuit 23 and with the input of the first integrator 20.

The output of the first integrator 20 is connected to the input of the first voltage comparator 16. The output of the first voltage comparator 16 is connected to the second input of the first operational amplifier 15. The output of the second frequency mixer 14 is connected to the first input of the second operational amplifier 17. The output of the second operational amplifier 17 is connected to the input of the second filter low frequencies 21. The output of the second low-pass filter 21 is connected to the third output of the quadrature phase detection device of the first channel, with the input of the second control circuit 24, with the input of the second horn integrator 22.

The output of the second integrator 22 is connected to the input of the second voltage comparator 18. The output of the second voltage comparator 18 is connected to the second input of the second operational amplifier 17. The output of the first control circuit 23 is connected to the first input of the health signal generating circuit 25.

The output of the second monitoring circuit 24 is connected to the second input of the health signal generating circuit 25. The output of the health signal generating circuit 25 is connected to the second output of the quadrature phase detection device of the first channel.

The fourth input of the quadrature phase detection device of the first channel is connected to the second input of the adder 9.

The second input of the quadrature phase detection device of the first channel is connected to the second input of the first frequency mixer 13.

The third input of the quadrature phase detection device of the first channel is connected to the second input of the second frequency mixer 14.

The fifth input of the quadrature phase detection device of the first channel is connected to the second input of the amplifier block with a temporary automatic gain control 12.

The first input of the first channel preprocessor is connected to the third input of the first multiplexer 36.

The second input of the pre-processing device of the first channel is connected to the second input of the first analog-to-digital converter 26.

The output of the first analog-to-digital converter 26 is connected to the first input of the first coefficient correction device 66, the output of the first coefficient correction device 66 is connected to the fifth input of the digital heterodyning device 29.

The first output of the digital heterodyning device 29 is connected to the first input of the first N-bit accumulating adder 32. The first output of the first N-bit accumulating adder 32 is connected to the first input of the first multiplexer 36. The output of the first multiplexer 36 is connected to the first input of random access memory 39 and with the second input of the first switch 48. The output of the first random access memory 39 is connected to the first input of the optimal filter 42. The output the first optimal filter 42 is connected to the first input of the first FiFo 45 chip. The output of the first FiFo 45 chip is connected to the first input of the first voltage switch 48.

The output of the first voltage switch 48 is connected to the first output of the pre-processing device of the first channel.

The third input of the first channel pre-processing device is connected to the first input of the second analog-to-digital converter 27. The output of the second analog-to-digital converter 27 is connected to the first input of the second coefficient correction device 67, the output of the second coefficient correction device 67 is connected to the second input of the digital heterodyning device 29. The second output of the digital heterodyning device 29 is connected to the first input of the second N-bit accumulating adder 33. The first output of the second N-ra the row accumulating adder 33 is connected to the first input of the second multiplexer 38. The output of the second multiplexer 38 is connected to the first input of the second random access memory 40 and to the second input of the second switch 49. The output of the second random memory 40 is connected to the first input of the second optimal filter 44. The output of the second optimal filter 44 is connected to the first input of the second chip FiFo 47. The output of the second chip FiFo 47 is connected to the first input of the second nth switch 49. The output of the second switch 49 is connected to the second output of the pre-processing device of the first channel. The second output of the first N-bit accumulating adder 32 is connected to the first input of the first reverse counter 31. The output of the first reverse counter 31 is connected to the input of the first digital-to-analog converter 28. The output of the first digital-to-analog converter 28 is connected to the first input of the first analog-to-digital converter 26. The second output of the second An N-bit accumulating adder 33 is connected to the first input of the second reverse counter 34. The output of the second reverse counter 34 is connected to the input of the second digital-analog converter 35. The output of the second digital to analog converter 35 is connected to a second input of the analog-digital converter 27.

The fourth input of the first channel pre-processing device is connected in parallel with the third input of the second analog-to-digital converter 27, with the third input of the first analog-to-digital converter 26, with the first input of the digital heterodyning device 29, with the third input of the first coefficient correction device 66, with the third input of the second coefficient correction devices 67.

The fifth input of the first channel pre-processing device is connected to the input of the permanent storage device of the digital heterodyning device 30. The first output of the permanent storage device of the digital heterodyning device 30 is connected to the third input of the digital heterodyning device 29. The second output of the permanent storage device of digital heterodyning 30 is connected to the fourth input of the digital heterodyning device 30 heterodyning 29.

The sixth input of the pre-processing device of the first channel is connected to the second input of the second N-bit accumulating adder 33, with the second input of the first N-bit accumulating adder 32.

The seventh input of the pre-processing device of the first channel is connected to the third input of the second N-bit accumulating adder 33, with the third input of the first N-bit accumulating adder 3.

The eighth input of the first channel pre-processing device is connected to the second input of the second reverse counter 34, with the second input of the second multiplexer 38, with the input of the write address generator 37, with the second input of the first multiplexer 36, with the second input of the first reverse counter 31.

The ninth input of the first channel pre-processing device is connected to the input of the read address generator 41, with the input of the reference signal generator 43, with the second input of the second FiFo chip 47, with the input of the control device 46, with the second input of the first FiFo 45 chip.

The tenth input of the first channel pre-processor is connected to the third input of the first switch 48 and the third input of the second switch 49. The first output of the control device 46 is connected to the third input of the first FiFo 45 chip. The second output of the control device 46 is connected to the fourth input of the first FiFo 45 chip. Third the output of the control device 46 is connected to the third input of the second FiFo 47 chip. The fourth output of the control device 46 is connected to the fourth input of the second FiFo 47 chip. The first output of the reference driver signal 43 is connected to the second input of the first optimal filter 42. The second output of the reference signal generator 43 is connected to the second input of the second optimal filter 44. The output of the write address generator 37 is connected to the second input of the first random access memory 39 and to the second input of the second random access memory inter-period processing devices 40. The output of the read address generator 41 is connected to the third input of the first random-access memory of the inter-period processing and 39 and to a third input of the second operational cheresperiodnoy processing memory 40.

The eleventh input of the first channel preprocessor is connected to the third input of the second multiplexer 38.

The interstage communications in the quadrature phase detection device of the second channel are similar to the interstage communications in the quadrature phase detection device of the first channel, the interstage communications of the second channel preprocessing device are similar to the interstage communications in the first channel preprocessing device.

Coherent receiver operates as follows

The device for quadrature phase detection of the first channel provides a discrete controlled amplification of the input signal, transfer of the spectrum of the input signal to the low frequency region and its decomposition into quadrature components (cos - Re is the real component of the signal and sin - Im is the imaginary component of the signal), low-pass filtering, constant binding component of the output signals to the midpoint of the analog-to-digital Converter and monitoring the health of the device.

The input signal from the first channel of the radar at an intermediate frequency (fpch), containing the Doppler frequency offset, from the input signal of the first channel 53 is fed to the first input of the adder 9, then to the amplifier block with temporary automatic gain control 12, which amplifies the received signal and produces a frequency his selection. The gain of the amplifiers changes discretely according to the instructions received from the first decoder 5. The control commands to the first decoder 5 come from the signal synchronizer 50, which is controlled via the parallel information line 65. The gain of the amplifiers block is provided by a discrete change in the value of the sequential negative feedback keys on field effect transistors.

The signal from the output of the amplifier block with temporary automatic gain control 12 is fed to the first input of the first frequency mixer 13 and to the first input of the second frequency mixer 14. The heterodyne signals phase-shifted 90 ° from each other are fed to the second inputs of the mixers 12 and 13.

The generation of heterodyne signals for frequency mixers is provided from the reference signal coming from the input reference signal connector 54 by dividing the input reference signal in frequency divider 2 by two frequencies, then filtering the harmonics with a bandpass filter 6 and phase shifting in the differentiating and integrating circuits and the signal amplifier in amplifiers 10 and 11.

Due to the phase shift of the signals in the differentiating and integrating circuits in opposite directions by 45 °, the phase shift of the heterodyne signals at the second inputs of the frequency mixers 13 and 14 is approximately 90 °. Amplifiers 10 and 11 are made resonant and the exact installation of the phase shift of the heterodyne signals, equal to 90 °, is provided by tuning the resonant circuits.

From the output of the first frequency mixer 13, the low-frequency signals are amplified in the first operational amplifier 15, pass through the first low-pass filter 19, and are fed through the circuit of the real component of the first channel (ReIk (cos)) to the second input of the first analog-to-digital converter 26 of the preliminary processing device of the first channel . The output signal from the second mixer 14 is processed similarly in the second operational amplifier 17, in the second low-pass filter 21 and along the imaginary component of the first channel (ImIk (sin)) to the first input of the second analog-to-digital converter 27 of the preliminary channel processing device.

The first 19 and second 21 low-pass filters are made in the form of a fifth-order T-shaped passive filter with Butterworth approximation on LC elements with a cutoff frequency of the amplitude-frequency characteristic equal to 3 MHz.

The stabilization of the DC component of the voltage of the output signal at the first output of the quadrature phase detection device (output of the I-th quadrature) is provided by a tracking system consisting of a first integrator 20, a first comparator 16, a first operational amplifier 15 and a first low-pass filter 19. The output signal from the first filter low frequencies 19 is supplied to the first integrator 20 having a large integration time constant. After integration, the signal is fed to the input of the first comparator 16, where it is compared with a threshold voltage. The output signal of the first comparator is fed to the second input of the first operational amplifier, changing its mode so as to ensure stabilization of the DC component of the voltage at the output of the first quadrature.

The stabilization of the DC component of the voltage of the output signal at the third output of the quadrature phase detection device of the first channel (output of the second quadrature) is carried out by a tracking system consisting of a second integrator 22, a second comparator 18, a second operational amplifier 17 and a second low-pass filter 21. The work of the constant stabilization circuit component of the voltage of the output signal at the third output of the quadrature phase detection device of the first channel is similar to stabilization oyannoy component of the output signal voltage I-th quadrature.

The transmission coefficients of the signals at the quadrature outputs in the quadrature phase detection device of the first channel are the same, and the signal phases are shifted by 90 °.

The first control circuit 23, the second control circuit 24, and the health signal generation circuit 25 form a “health” signal.

The first control circuit 23 monitors the health of the quadrature phase detection device of the first channel of the real component of the signal, and the second control circuit 24 monitors the health of the imaginary component of the signal.

Serviceability control by the real component is provided by a bipolar threshold check of the signal level. The signal from the output of the first low-pass filter 19 is fed to the first control circuit. In the first control circuit 23, the signal levels on the comparators are compared with threshold voltage levels. If the signal levels exceed the threshold voltage levels in the comparators, a signal is outputted to the health signal generation circuit 25. The second monitoring circuit 24 works similarly to the imaginary signal component of the first channel. If there are signals from both control circuits 23 and 24, the health signal generation circuit 25 provides a “good” signal, which is fed to the signal synchronizer 50 and fed to the output of the coherent radar receiver with a digital device 65 for the amplitude and phase correction of the received quadrature components signal.

The input signal of the second channel of the radar from the input connector of the second channel 55 is fed to the first input of the quadrature phase detection device of the second channel.

The quadrature phase detection device of the second channel provides a similar signal processing of the second receiving channel and is structurally similar to the first channel device.

The second decoder 4 performs functions similarly to the first decoder only for the second reception channel. From the output of the quadrature phase detection device of the second channel, the real and imaginary components of the low-frequency signal are fed to the second and third inputs of the pre-processing device of the second channel.

The preprocessing device of the first channel performs the following operations:

- conversion of four analog input signals (Re 1k, Im 1k, Re 2k, Im 2k) into a twelve-digit code;

- produces digital heterodyning;

- provides optimal filtering of signals;

- produces channel multiplexing;

- generates correction factors for digital heterodyning;

- compensates for the constant component that occurs at the inputs of analog-to-digital converters;

- provides signal accumulation;

corrects the identity of the amplitude and phase characteristics of quadratures;

provides control signals for the transmitting channel, the high-frequency receiver and the synchronization of the preprocessing device.

The device for pre-processing the first channel as follows.

The first analog-to-digital Converter 26 translates the analog signal of the real component of the first channel into digital form. The second analog-to-digital Converter 27 converts the analog signal of the imaginary component of the first channel into digital form. After analog-to-digital converters, the first 66 and second 67 coefficient correction devices correct the distortions that occur during the quadrature conversion of the real and imaginary components of the signal according to the algorithm:

Re _out = Re _in

Im _out = Im _in C1 + Re _in C2

C1 = Kcos (Δφ)

C2 = tg (Δφ),

where K is the initial excess of the gain in the channel Re relative to the channel Im;

Δφ is the deviation of the true position of the axes from π / 2.

The values of the coefficients C1, C2 are received through the parallel information line 65 from the on-board digital computer system.

The digital heterodyning device 29 performs digital heterodyning, the local oscillator frequency is set along the parallel information line with an accuracy of 0.8 Hz. The digital heterodyning device 29 performs the operation of multiplying two complex numbers:

Á1 [i] = Á0 [i] · K '[i],

where Á0 [i] = Re0 [i] + jIm0 [i] are the sample codes of the quadrature components of the signal coming from the analog-to-digital converter,

K '[i] = cosφ [i] -jsinφ [i] - correction factors coming from a digital local oscillator,

φ [i] = φ [i-1] + Δφ; Δφ is the phase incursion.

The read-only memory 30 of the digital heterodyning device is based on two read-only memory devices AT29C1024-70JI. The address for reading information from read-only memory 30 of the digital heterodyning device is continuously generated in accordance with the code Δφ. Reading the values of the correction factors occurs with the sampling frequency of the analog-to-digital Converter.

After heterodyning, the signal samples are summed over the interval of one range element

where n is the number of the range element of the real component in the first N-bit accumulating adder 32, the imaginary component in the second N-bit accumulating adder 33.

The number of summing samples is determined by the code N _k and can take values from one to sixty three.

The first analog-to-digital converter 26 is covered by a feedback circuit consisting of a reversible counter 31 and a digital-to-analog converter 28 for balancing the DC component. The second analog-to-digital converter 27 is likewise covered by a feedback circuit consisting of a second reversible counter 34 and a second digital-to-analog converter 35 for balancing the DC component. To prevent overflow of the discharge grid of drives, the first 36 and second 38 multiplexers are available, the first 39 and second 40 random access memory devices are designed for information processing in the first 42 and second 44 optimal filters. The first 48 and second 49 switches supply information to the outputs of the third 51 and fourth 52 multiplexers either directly from the first 36 and second 38 multiplexers or from the first 42 and second 44 outputs of the optimal filters via FiFo microcircuits.

The signal synchronizer 50 is an electronic logic circuit in which logical operations are performed under the control of external signals and, therefore, synchronously with the radar clock pulses generated outside the circuit (Explanatory Dictionary of Computing Systems / Edited by V. Illingworth et al. Translated from English A.Kbelotsky et al .; Edited by E.K. Maslovsky. - M.: Mechanical Engineering, 1990, p. 471).

The operation of the signal synchronizer 50 is performed on the parallel information line (MPI).

To ensure synchronous operation of the signal synchronizer 50 of the claimed device with the clock signals of the radar, a reference signal with a frequency of 56 MHz with a high frequency stability of 54 is used, which comes from the master radar generator. This reference signal through the level 1 converter is fed to the first input of the signal synchronizer 50. All output signals of the signal synchronizer 50 are generated on logical digital devices (triggers, counters, decoders, registers, signal distributors, buffer stages, AND, AND-NOT circuits "). The operation of these digital devices is described in (Bukreev I.N. et al. Microelectronic circuits of digital devices. 2 nd, revised., From the add. M .: Sov.radio 1975). These digital devices are located in the microcircuit (FPGA) of ALTERA EPM 9560ARI208-10, on the basis of which a signal synchronizer 50 is made.

The connection diagram of logical digital devices in the FPGA is carried out according to the MAX + Plus II program, the construction of which is described in (Komolov D.A., Myalk R.A., Zobenko A.A., Filippov A.S. Computer-aided design systems by ALTERA MAX + Plus II and Quartus II. Brief Description and Tutorial. - M .: IP RadioSoft, 2002, p. 256-281).

Signal synchronizer 50 provides control signals for a transmitting channel, a high-frequency receiver:

- from the eleventh output, a pulse to form the antenna tuning gate (SPA) 56;

- from the twelfth output, the start signal of the finished transmitter stage (IZP) 57;

- from the thirteenth output, a signal defining the duration of the transmitter start pulse (D _Σ ) 58;

- from the fourteenth output, a signal defining the phase of the transmitter start pulse (Дπ) 59;

- from the fifteenth output, the signal of the pulse blanking receiver (UPS) 60;

- from the sixteenth output, the pulse accompanying the main signal (SI) 61;

- from the seventeenth output, the pulse of the beginning of the transfer (IPP) 62.

There are two main modes of operation of the signal synchronizer 50: the LF mode (low repetition rate) and the HFP / CID mode (high or medium repetition rate). The change of mode is made by the command “On Low Frequency”, coming from the MPI. With this command, the discrete setting of the IPP period and the delay in the start of the reception zone relative to the leading edge of the “Dπ” signal is 1/14 μs, in the absence of it, it is 1/56 μs.

To control the repetition period of the IPP, two words are provided in the MPI: the upper five digits are transmitted in a word with one address, the lower sixteen digits in a word with a different address.

The formation of the “Dπ” signal is controlled by the “Smooth” command coming from the MPI. In the presence of this command, the signal “Dπ” is a video pulse with a duration of 1/7 · Nkv, where Nkv is the number of samples in the range element, it is determined by the code coming from the MPI. The range of variation of Nkv is [1 ... 63].

In the absence of the “Smooth” command, the “Dπ” signal is one of the code sequences: a thirteen-element Barker code or a minimax code of seventy-one, one hundred twenty-seven, two hundred and fifty-one elements in length. The type of sequence is determined by the two-digit code "N code [1 ... 0]".

The SPA signal is generated when the “On SPA” command is present. The duration of the SPA corresponds to the duration of the strobe tuning the radar frequency (HFC) and is 4.48 ms. During the SPA, the issuance of signals of IZP, D _Σ and Dπ is blocked. Timing diagrams of the operation of the device in the presence of the command “On. SPA "are shown in figure 3.

The temporary position of the edges of the signals D _Σ , Dπ and the leading edge of the UPS signal relative to the edges of the UPS is selected based on the statistics on the development of the radar. The trailing edge of the UPS signal is tied to the beginning of the reception area. The signal D _Σ lags behind the SPD by 11/14 μs. The signal Dπ lags the signal D _Σ by 1/14 μs.

To synchronize the pre-processing device of the first channel, the output signals from the signal synchronizer 50 are used:

output twenty - a sampling signal - a meander with a frequency of 7 MHz, designed to synchronize the ADC and organize pipelining of the signal in the first analog-to-digital converter 26, in the first device for adjusting the coefficients 66, in the second analog-to-digital converter 27, in the second device for adjusting the coefficients 67 , in a digital heterodyning device 29;

output twenty one - the address of the ROM 30 of the digital heterodyning device, is calculated in the signal synchronizer 50 at a given value of the frequency of the digital heterodyning, is changed synchronously by the signal from the output twenty;

output twenty two is the momentum of the beginning of summation. Defines the beginning of the range element (zeroing the first 32 and second 33 N-bit accumulative adders);

output twenty-three is the momentum of the end of the summation. Defines the end of the range element (recording data from the first 32 and second 33 N-bit accumulative adders in the output buffer register);

output twenty-four - inverted pulses of the summing channel. Designed for organizing conveyor processing in the first 36 and second 38 multiplexers, for synchronizing counters and controlling data recording in the first 39 and second 40 random access memory devices with inter-period processing using the write address generator 37;

output twenty-five — synchronization signal of the optimal filter — meander with a frequency of 14 MHz. Designed to organize the data processing process in the optimal filter for recording results in the first 45 and second 47 FiFo microcircuits;

output twenty six - switch switching signal - logic level. It is set by the command “Enabling the optimal filter”, coming from the parallel information line.

The control signal of the output multiplexers (channel switches) is nineteen - a meander with a frequency of 7 MHz, if there is a command "Turn on the optimal filter" or a meander with a frequency of 22 MHz - if there is no command "Turn on the optimal filter".

The signals from the fifth, sixth, seventh, eighth, ninth, tenth and eighteenth outputs of the signal synchronizer 50 are used to synchronize the device 50 for the preliminary processing of the second channel. These signals are similar to signals from the twentieth, twenty-first, twenty-second, twenty-third, twenty-fourth, twenty-fifth and twenty-sixth outputs, respectively.

The health signal of the quadrature phase detection device of the first channel is fed to the second input of the signal synchronizer 50. The health signal of the quadrature phase detection device of the second channel is fed to the third input of the signal synchronizer 50. These health signals are generated in the quadrature phase detection devices of the first and second channels in the presence of the “Turn on” command control signal ”, coming from the first output of the signal synchronizer. The signal synchronizer 50 issues the command "Turn on the control signal" to the first output, if there is a command "Turn on the control signal" from the parallel line of information 65, which is fed to the fourth input of the signal synchronizer 50.

The control commands of the temporary automatic gain control for the first and second quadrature phase detection devices, coming through the parallel information line 65 to the fourth input of the signal synchronizer 50, are transmitted by the signal synchronizer 50 to the second output for supplying them to the first decoder 5 and to the third output of the signal synchronizer 50 for feeding them to a second decoder 4, respectively.

For temporary compression of the phase-coded signal, inter-period processing of information from the drive is used. Two port random access memory devices are used to store the signal data of the previous clock and record data of the current clock. The writing and reading addresses for two port random access memory devices are generated in the write address generator 37 and the read address generator 41. The reference signal generator 43 generates arrays of reference functions for various types of phase-shifted signals. The control device 46 generates control signals of the first 45 and second 47 of the FiFo chips, depending on the operating mode of the radar.

When compressing the phase-coded signal for each element of the range, the convolution value is calculated:

where B [k] is the element of the array of the support function.

In order to reduce the information processing time, the first channel pre-processing device uses sixty-four parallel-working compression devices for phase-coded signals, thus simultaneously processing information for sixty-four range elements.

The processing time of sixty-four range elements is determined by the length of the phase-coded sequence N _fcc

where F _T is the clock frequency of the compression devices, determined by the speed of the chip. In this case, F _T = 7 MHz.

. Данные из первого 42 и второго 44 оптимальных фильтров записываются оперативно-запоминающим устройством типа FiFo в конце каждого цикла. После обработки всех элементов дальности производится передача всего массива данных FiFo во внешнее устройство в соответствии с заданным протоколом обмена. Частота передачи определяется параметрами внешнего устройства и в данном случае после мультиплексирования составляет 14 МГц.Since the required number of range elements in the general case is more than sixty-four, the compression of phase-coded signals is performed in several cycles

. Data from the first 42 and second 44 optimal filters are recorded by a random access memory device of the FiFo type at the end of each cycle. After processing all range elements, the entire FiFo data array is transferred to an external device in accordance with the specified exchange protocol. The transmission frequency is determined by the parameters of the external device and in this case, after multiplexing, is 14 MHz.

The control device controls the processes of recording information from the optimal filter in FiFo and reading information from FiFo in accordance with the specified number of range elements and the timing diagram of the optimal filter.

From the outputs of the first 42 and second 44 optimal filters, the data is recorded in the first 45 and second 47 of the FiFo chip, respectively, after the processing of all range elements is completed, the data from the first 45 and second 47 of the FiFo chip are fed to the output of the third 51 and fourth 52 multiplexers, respectively.

The pre-processing device of the second channel provides similar processing of the output signal of the quadrature phase detection device of the second channel, as in the pre-processing device of the first channel and is structurally similar to the pre-processing device of the first channel.

Signal processing in the pre-processing devices of the second channel and the first channel is carried out according to the program on programmable logic integrated circuits PLIS type EPF10K200EB 1600-2.

In order to check the accuracy during digital correction of the quadrature of the received signals, a control signal is generated on the crystal oscillator 3. The synchronizer 50, on the control signal from the highway 65, issues a command to the first output of the synchronizer, which is transmitted to the crystal oscillator 3 and allows the control signal to be generated. The control signal from the first output of the crystal oscillator is fed to the second input of the adder 9 of the quadrature phase detection device of the first channel, and from the second output of the crystal generator the control signal is fed to the fourth input of the quadrature phase detection device of the second channel to a similar adder, thereby entering the main signal processing paths both channels.

The dynamic range of the receiving device is expanded due to the high linearity of the amplitude characteristics of the amplifier block with temporary automatic gain control and mixers. The first 13 and second 14 mixers are made according to a key balanced circuit with the control of the local oscillator signal by the amount of sequential negative feedback in the amplifier of the mixer, which also ensures the linearity of the mixers.

The reference frequency signal for the signal synchronizer 50 is generated in the level 1 converter from the reference frequency signal coming from the input connector of the input reference signal 54.

From the third multiplexer 51, the output signal is supplied to the output signal connector of the real component 63, and from the fourth multiplexer 52, the output signal is supplied to the output signal connector of the imaginary component 64.

The application of the proposed coherent receiver expands the functionality by additionally performing the following functions:

- provides control signals for the transmitting channel, the high-frequency receiver and the synchronization of the preprocessing device;

- provides controlled gain,

- compensates for the DC component at the inputs of the analog-to-digital converter;

- generates correction factors for digital heterodyning;

- provides optimal filtering of signals;

- produces channel multiplexing;

- produces digital heterodyning ;.

- provides accumulation;

- Corrects the identity of the amplitude and phase characteristics of the quadrature.

Improvement of the main technical parameters is carried out by increasing the dynamic range of the device and increasing accuracy with digital adjustment of the quadrature of the received signals.

According to the proposed technical solution, prototypes were made. Technical parameters are confirmed by the positive results of preliminary and flight tests.

Claims (1)

Coherent radar receiver with a digital device for amplitude and phase correction of the quadrature components of the received signal,  comprising a first analog-to-digital converter,  first and second frequency mixers,  first N-bit accumulating adder,  first and second voltage comparators  that the first receiving channel includes a quadrature phase detection device of the first channel and a preliminary processing device of the first channel,  wherein the device quadrature phase detection of the first channel contains an adder,  amplifier block with temporary automatic gain control,  first and second frequency mixers,  first and second operational amplifiers,  first and second voltage comparators,  first and second low-pass filters,  first and second integrators,  the first and second control schemes,  health signal generation circuit,  the first channel pre-processing device consists of the first and second analog-to-digital converters,  first and second digital-to-analog converters,  the first and second devices for adjusting coefficients,  digital heterodyne devices,  read only memory device digital heterodyne,  first and second reversible counters,  the first and second accumulating N-bit adders,  first and second multiplexers,  shaper of the address of the record,  first and second random access memory devices,  read address driver  first and second optimal filters,  reference signal driver,  the first and second FiFo chips "the first came in,  first out, "  control devices  first and second switches,  wherein the second receiving channel comprises a quadrature phase detection device for the second channel and a preliminary processing device for the second channel,  which are structurally similar to the quadrature phase detection device of the first channel and the preliminary processing device of the first channel,  as well as in the coherent radar receiver with a digital device for amplitude and phase correction of the quadrature components of the received signal, the first and second decoders are included,  crystal oscillator  level converter  frequency divider,  bandpass filter  differentiating chain  integrating chain  first and second resonant amplifiers,  third and fourth multiplexers,  signal synchronizer  wherein the input of the receiver through the first channel is connected to the first input of the quadrature phase detection device of the first channel,  the first output of the quadrature phase detection device of the first channel is connected to the second input of the first channel preprocessing device,  the first output of the pre-processing device of the first channel is connected to the first input of the third multiplexer,  the output of the third multiplexer is connected to the connector of the output signal of the real component,  the input reference signal connector is connected to the input of the frequency divider and the input of the level converter,  the output of the frequency divider is connected to the input of the bandpass filter,  the output of the bandpass filter is connected to the input of the differentiating chain and the input of the integrating chain,  the output of the differentiating circuit is connected to the input of the first resonant amplifier,  the first output of the resonant amplifier is connected to the second input of the quadrature phase detection device of the first channel,  the second output of the first resonant amplifier is connected to the second input of the quadrature phase detection device of the second channel,  the output of the integrating circuit is connected to the input of the second resonant amplifier,  the first output of the second resonant amplifier is connected to the third input of the quadrature phase detection device of the first channel,  the second output of the second resonant amplifier is connected to the third input of the quadrature phase detection device of the second channel,  the first output of the quadrature phase detection device of the second channel is connected to the second input of the second channel preprocessing device,  the first output of the pre-processing device of the second channel is connected to the second input of the fourth multiplexer,  the output of the fourth multiplexer is connected to the output connector of the imaginary component,  the first output of the signal synchronizer is connected to the input of the crystal oscillator,  the first output of the crystal oscillator is connected to the fourth input of the quadrature phase detection device of the first channel,  the second output of the crystal oscillator is connected to the fourth input of the quadrature phase detection device of the second channel,  the second output of the signal synchronizer is connected to the input of the first decoder,  the output of the first decoder is connected to the fifth input of the quadrature phase detection device of the first channel,  the third output of the signal synchronizer is connected to the input of the second decoder,  the output of the second decoder is connected to the fifth input of the quadrature phase detection device of the second channel,  the output of the level converter is connected to the first input of the signal synchronizer,  the second output of the quadrature phase detection device of the second channel is connected to the third input of the signal synchronizer,  the third output of the quadrature phase detection device of the second channel is connected to the third input of the preliminary processing device of the second channel,  the second output of the quadrature phase detection device of the first channel is connected to the second input of the signal synchronizer,  the third output of the quadrature phase detection device of the first channel is connected to the third input of the preliminary processing device of the first channel,  the fifth output of the signal synchronizer is connected to the fourth input of the preliminary processing device of the second channel,  the sixth output of the signal synchronizer is connected to the fifth input of the pre-processing device of the second channel,  the seventh output of the signal synchronizer is connected to the sixth input of the pre-processing device of the second channel,  the eighth output of the signal synchronizer is connected to the seventh input of the preliminary processing device of the second channel,  the ninth output of the signal synchronizer is connected to the eighth input of the pre-processing device of the second channel,  the tenth output of the signal synchronizer is connected to the ninth input of the pre-processing device of the second channel,  the eleventh output of the signal synchronizer is a pulse output for forming the antenna tuning gate,  the twelfth output of the signal synchronizer is the output of the trigger signal of the final stage of the transmitter,  the thirteenth output of the signal synchronizer is a signal output,  determining the duration of the start pulse of the transmitter,  the fourteenth output of the signal synchronizer is a signal output,  determining the phase of the transmitter trigger pulse,  the fifteenth output of the signal synchronizer is the output signal of the pulse blanking receiver,  the sixteenth output of the signal synchronizer is a pulse output,  accompanying the main signal,  the seventeenth output of the signal synchronizer is the output of the transmission start pulse,  the eighteenth output of the signal synchronizer is connected to the tenth input of the preliminary processing device of the second channel,  the nineteenth output of the signal synchronizer is connected to the third input of the third multiplexer and the third input of the fourth multiplexer,  the twentieth output of the signal synchronizer is connected to the fourth input of the first channel preprocessing device,  the twenty-first output of the signal synchronizer is connected to the fifth input of the pre-processing device of the first channel,  the twenty-second output of the signal synchronizer is connected to the sixth input of the preliminary processing device of the first channel,  the twenty-third output of the signal synchronizer is connected to the seventh input of the pre-processing device of the first channel,  the twenty-fourth output of the signal synchronizer is connected to the eighth input of the first channel preprocessing device,  the twenty-fifth output of the signal synchronizer is connected to the ninth input of the first channel preprocessing device,  the twenty-sixth output of the signal synchronizer is connected to the tenth input of the first channel preprocessing device,  the parallel information trunk connector is connected in parallel with the first,  eleventh  the twelfth  the thirteenth inputs of the pre-processing device of the first channel and with the first,  eleventh  the twelfth  the thirteenth inputs of the pre-processing device of the second channel and with the fourth output of the signal synchronizer,  the second output of the first channel pre-processing device is connected to the first input of the fourth multiplexer,  the second output of the pre-processing device of the second channel is connected to the second input of the third multiplexer,  in the quadrature phase detection device of the first channel, the first input is connected to the first input of the adder,  the output of the adder is connected to the first input of the amplifier block with temporary automatic gain control,  the output of the amplifier block with temporary automatic gain control is connected to the first input of the first frequency mixer and to the first input of the second frequency mixer,  the output of the first frequency mixer is connected to the first input of the first operational amplifier,  the output of the first operational amplifier is connected to the input of the first low-pass filter,  the output of the first low pass filter is connected to the first output of the quadrature phase detection device of the first channel,  with the input of the first control circuit and with the input of the first integrator,  the output of the first integrator is connected to the input of the first voltage comparator,  the output of the first voltage comparator is connected to the second input of the first operational amplifier,  the output of the second frequency mixer is connected to the first input of the second operational amplifier,  the output of the second operational amplifier is connected to the input of the second low-pass filter,  the output of the second low-pass filter is connected to the third output of the quadrature phase detection device of the first channel,  with the input of the second control circuit and with the input of the second integrator,  the output of the second integrator is connected to the input of the second voltage comparator,  the output of the second voltage comparator is connected to the second input of the second operational amplifier,  the output of the first control circuit is connected to the first input of the health signal generating circuit,  the output of the second control circuit is connected to the second input of the health signal generating circuit,  the output of the health signal generating circuit is connected to the second output of the quadrature phase detection device of the first channel,  the fourth input of the quadrature phase detection device of the first channel is connected to the second input of the adder,  the second input of the quadrature phase detection device of the first channel is connected to the second input of the first frequency mixer,  the third input of the quadrature phase detection device of the first channel is connected to the second input of the second frequency mixer,  the fifth input of the quadrature phase detection device of the first channel is connected to the second input of the amplifier block with temporary automatic gain control,  the input signal of the second channel is connected to the first input of the phase detection device of the second channel,  the first input of the first channel preprocessing device is connected to the third input of the first multiplexer,  the second input of the pre-processing device of the first channel is connected to the second input of the first analog-to-digital converter,  the output of the first analog-to-digital converter is connected to the first input of the first coefficient correction device,  the output of the first coefficient correction device is connected to the fifth input of the digital heterodyning device,  the first output of the digital heterodyning device is connected to the first input of the first N-bit accumulating adder,  the first output of the first N-bit accumulating adder is connected to the first input of the first multiplexer,  the output of the first multiplexer is connected to the first input of random access memory and to the second input of the first switch,  the output of the first random-access memory is connected to the first input of the optimal filter,  the output of the first optimal filter is connected to the first input of the first FiFo chip,  the output of the first FiFo chip is connected to the first input of the first voltage switch,  the output of the first voltage switch is connected to the first output of the pre-processing device of the first channel,  the third input of the pre-processing device of the first channel is connected to the first input of the second analog-to-digital converter,  the output of the second analog-to-digital converter is connected to the first input of the second coefficient correction device,  the output of the second coefficient correction device is connected to the second input of the digital heterodyning device,  the second output of the digital heterodyning device is connected to the first input of the second N-bit accumulating adder,  the first output of the second N-bit accumulating adder is connected to the first input of the second multiplexer,  the output of the second multiplexer is connected to the first input of the second random-access memory and to the second input of the second switch,  the output of the second random-access memory is connected to the first input of the second optimal filter,  the output of the second optimal filter is connected to the first input of the second FiFo chip,  the output of the second FiFo chip is connected to the first input of the second switch,  the output of the second switch is connected to the second output of the pre-processing device of the first channel,  the second output of the first N-bit accumulating adder is connected to the first input of the first reversible counter,  the output of the first reversible counter is connected to the input of the first digital-to-analog converter,  the output of the first digital-to-analog converter is connected to the first input of the first analog-to-digital converter,  the second output of the second N-bit accumulating adder is connected to the first input of the second reversible counter,  the output of the second reversible counter is connected to the input of the second digital-to-analog converter,  the output of the second digital-to-analog converter is connected to the second input of the analog-to-digital converter,  the fourth input of the first channel pre-processing device is connected in parallel with the third input of the second analog-to-digital converter,  with the third input of the first analog-to-digital converter,  with the first input of the digital heterodyning device,  with the third input of the second coefficient correction device,  with the third input of the first coefficient correction device,  the fifth input of the first channel pre-processing device is connected to the input of the read-only memory of the digital heterodyning device,  the first output of the read-only memory of the digital heterodyning device is connected to the third input of the digital heterodyning device,  the second output of the digital memorization device is connected to the fourth input of the digital heterodyning device,  the sixth input of the pre-processing device of the first channel is connected to the second input of the second N-bit accumulating adder and to the second input of the first N-bit accumulating adder,  the seventh input of the pre-processing device of the first channel is connected to the third input of the second N-bit accumulating adder and to the third input of the first N-bit accumulating adder,  the eighth input of the pre-processing device of the first channel is connected to the second input of the second reverse counter,  with the second input of the second multiplexer,  with the input of the address generator of the record,  with the second input of the first multiplexer and with the second input of the first reversible counter,  the ninth input of the preprocessing device of the first channel is connected to the input of the read address generator,  with the input of the driver of the reference signals,  with the second input of the second FiFo chip,  with the input of the control device and with the second input of the first FiFo chip,  the tenth input of the first channel pre-processing device is connected to the third input of the first switch and the third input of the second switch,  the first output of the control device is connected to the third input of the first FiFo chip,  the second output of the control device is connected to the fourth input of the first FiFo chip,  the third output of the control device is connected to the third input of the second FiFo chip,  the fourth output of the control device is connected to the fourth input of the second FiFo chip,  the first output of the driver of the reference signals is connected to the second input of the first optimal filter,  the second output of the driver of the reference signals is connected to the second input of the second optimal filter,  the output of the recording address generator is connected to the second input of the first random access memory of the inter-period processing and the second input of the second random access memory of the inter-period processing,  the output of the read address generator is connected to the third input of the first random-access memory and the third input of the second random-access memory,  the eleventh input of the first channel pre-processing device is connected to the third input of the second multiplexer,  interstage communications in the quadrature phase detection device of the second channel are similar to interstage communications in the quadrature phase detection device of the first channel,  interstage communications of the pre-processing device of the second channel are similar to interstage communications in the pre-processing device of the first channel.

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