CN212905422U - Broadband digital frequency measurement module - Google Patents
Broadband digital frequency measurement module Download PDFInfo
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- CN212905422U CN212905422U CN202020939317.2U CN202020939317U CN212905422U CN 212905422 U CN212905422 U CN 212905422U CN 202020939317 U CN202020939317 U CN 202020939317U CN 212905422 U CN212905422 U CN 212905422U
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Abstract
The utility model discloses a broadband digital frequency measurement module, its structure includes radio frequency processing circuit, intermediate frequency processing circuit, detection circuit and supply circuit. The utility model has the advantages that: the structure design is reasonable, the conventional analog frequency measurement technology is improved into the digital frequency measurement technology, the phase delay is improved into the digital domain delay technology from the analog delay line technology, and the Verilog language is matched and used in the practical engineering application to realize the instantaneous frequency measurement algorithm in the FPGA according to the frequency measurement algorithm principle and matlab simulation. The method realizes rapid frequency measurement of the monitored and received radar signals in the frequency range of 3 GHz-5 GHz, outputs frequency, width-preserving pulse and other related information, and meets the requirement of rapidly guiding interference equipment to perform interference.
Description
Technical Field
The utility model relates to a broadband digital frequency measurement module, concretely relates to applies to the broadband digital frequency measurement module of frequency measurement receiver of electronic countermeasure equipment.
Background
Electronic countermeasure techniques are mainly divided into electronic reconnaissance and electronic interference. The electronic reconnaissance mainly aims to measure the signal parameters of the enemy radar and the position of the enemy radar, and further obtain the function and performance of the radar. In modern complex electromagnetic environments, signals must be sorted and threat identified first for effective interference, and signal frequency is one of the main factors for signal sorting and threat identification. The signal frequency measurement is therefore one of the main properties of electronic countermeasure equipment. The frequency measuring module is also a core component of the electronic countermeasure equipment.
In the prior art, a frequency measurement module is a simulated instantaneous frequency measurement module, and has the advantages of simple composition, mature technology, high modularization degree, small volume, low cost, low working sensitivity, poor adaptability of an arrival signal, and easy influence of temperature change on delay line precision, thereby causing channel error or frequency measurement precision reduction (the frequency measurement range is determined by a shortest delay line channel, and the frequency measurement precision is determined by a longest delay line channel).
SUMMERY OF THE UTILITY MODEL
The utility model provides a broadband digital frequency measurement module, its purpose aims at overcoming the above-mentioned not enough that prior art exists, adopts the instantaneous frequency measurement technique of digit, realizes carrying out quick frequency measurement to the radar signal of listening receipts in 3GHz ~ 5GHz frequency range to relevant information such as output frequency, guarantor's width pulse satisfy the demand that quick guide interference device carried out the interference.
The technical solution of the utility model is as follows: the broadband digital frequency measurement module structurally comprises a radio frequency processing circuit, an intermediate frequency processing circuit, a detection circuit and a power supply circuit,
the radio frequency processing circuit is used for receiving a 3 GHz-5 GHz radio frequency signal, outputting the signal to the intermediate frequency processing circuit for processing after amplification, 32 frequency division amplification and filtering,
the intermediate frequency processing circuit is used for receiving intermediate frequency signals output by the radio frequency processing circuit, carrying out AD sampling, carrying out digital down conversion, parallel differential complex multiplication and multipoint average filtering processing on the intermediate frequency sampling signals in the FPGA, outputting CMOS level frequency codes, converting the CMOS level frequency codes into 5VTTL levels through a driver, parallelly outputting 11bit frequency codes, finally converting the 11bit frequency codes into differential TTL levels through a second differential conversion chip,
the detection circuit is used for detecting the received 3-5 GHz radio frequency signals, outputting detection pulses and judging whether the input signal power of the frequency measurement module is lower than the receiving sensitivity,
the power supply circuit is used for accessing DC24V direct current voltage input from the outside, and provides a low-ripple low-voltage direct current power supply for the radio frequency processing circuit, the intermediate frequency processing circuit and the detection circuit through the DC/DC conversion circuit and the low dropout regulator LDO.
Preferably, the radio frequency processing circuit comprises an amplitude limiting low noise amplifier, a 3 GHz-5 GHz band pass filter, a power divider, a gain amplifier, a 5GHz low pass filter, a quartering device, a 1.2GHz low pass filter, an octave frequency divider and a 160MHz low pass filter which are connected in sequence, the amplitude limiting low noise amplifier is connected with a radio frequency signal input, the power divider is further connected with the detection circuit, and the 160MHz low pass filter is connected with the intermediate frequency processing circuit.
Preferably, the detection circuit comprises a detector, a high-speed comparator and a first differential conversion chip which are connected in sequence, the detector is connected with the power divider, and the first differential conversion chip outputs a detection signal.
Preferably, the intermediate frequency processing circuit comprises an ADC chip, an FPGA, a level conversion circuit and a second differential conversion chip which are connected in sequence, the FPGA and the ADC chip are further connected to a clock generator, the ADC chip is connected to the 160MHz low-pass filter, and the second differential conversion chip outputs a frequency measurement signal.
Preferably, the first differential conversion chip and the second differential conversion chip are AM26C31 differential conversion chips.
The utility model has the advantages that: the structure design is reasonable, the conventional analog frequency measurement technology is improved into the digital frequency measurement technology, the phase delay is improved into the digital domain delay technology from the analog delay line technology, and the Verilog language is matched and used in the practical engineering application to realize the instantaneous frequency measurement algorithm in the FPGA according to the frequency measurement algorithm principle and matlab simulation. The method realizes rapid frequency measurement of the monitored and received radar signals in the frequency range of 3 GHz-5 GHz, outputs frequency, width-preserving pulse and other related information, and meets the requirement of rapidly guiding interference equipment to perform interference.
Drawings
Fig. 1 is a block diagram of the wideband digital frequency measurement module of the present invention.
Fig. 2 is a working principle block diagram of the wideband digital frequency measurement module of the present invention.
Fig. 3 is a schematic diagram of an embodiment of the rf processing circuit of fig. 2.
Fig. 4 is a schematic diagram of an embodiment of the if processing circuit of fig. 2.
FIG. 5 is a block diagram of one embodiment of the FPGA of FIG. 2.
Fig. 6 is a schematic block diagram of an embodiment of the if processing circuit of fig. 2.
Detailed Description
The present invention will be described in further detail with reference to examples and embodiments.
As shown in fig. 1 and 2, the wideband digital frequency measurement module structurally comprises a radio frequency processing circuit, an intermediate frequency processing circuit, a detection circuit and a power supply circuit,
the radio frequency processing circuit is used for receiving a 3 GHz-5 GHz radio frequency signal, outputting the signal to the intermediate frequency processing circuit for processing after amplification, 32 frequency division amplification and filtering,
the intermediate frequency processing circuit is used for receiving intermediate frequency signals output by the radio frequency processing circuit, carrying out AD sampling, carrying out digital down conversion, parallel differential complex multiplication and multipoint average filtering processing on the intermediate frequency sampling signals in the FPGA, outputting CMOS level frequency codes, converting the CMOS level frequency codes into 5VTTL levels through a driver, parallelly outputting 11bit frequency codes, finally converting the 11bit frequency codes into differential TTL levels through a second differential conversion chip,
the detection circuit is used for detecting the received 3-5 GHz radio frequency signals, outputting detection pulses and judging whether the input signal power of the frequency measurement module is lower than the receiving sensitivity,
the power supply circuit is used for accessing DC24V direct current voltage input from the outside, and provides a low-ripple low-voltage direct current power supply for the radio frequency processing circuit, the intermediate frequency processing circuit and the detection circuit through the DC/DC conversion circuit and the low dropout regulator LDO.
The radio frequency processing circuit comprises an amplitude limiting low-noise amplifier, a 3 GHz-5 GHz band-pass filter, a power divider, a gain amplifier, a 5GHz low-pass filter, a four-frequency divider, a 1.2GHz low-pass filter, an eight-frequency divider and a 160MHz low-pass filter which are sequentially connected, wherein the amplitude limiting low-noise amplifier is connected with a radio frequency signal input, the power divider is also connected with a detection circuit, and the 160MHz low-pass filter is connected with an intermediate frequency processing circuit. Considering the factors of the best performance of the device, the signal quality and the like, the 32-division circuit is realized by an eight-division and four-division twice-division circuit.
The amplitude limiting low-noise amplifier comprises an amplitude limiter and a low-noise amplifier.
The detector circuit comprises a detector, a high-speed comparator and a first differential conversion chip which are sequentially connected, the detector is connected with the power divider, and the first differential conversion chip outputs a detection signal.
The intermediate frequency processing circuit comprises an ADC chip, an FPGA, a level conversion circuit and a second differential conversion chip which are sequentially connected, the FPGA and the ADC chip are further connected with a clock generator, the ADC chip is connected with a 160MHz low-pass filter, and the second differential conversion chip outputs a frequency measurement signal.
The first differential conversion chip and the second differential conversion chip are AM26C31 differential conversion chips.
According to the structure, when the broadband digital frequency measurement module works, the broadband digital frequency measurement module receives a measured radio frequency signal of 3 GHz-5 GHz, and after the signal is amplified and filtered by the amplitude limiting low-noise amplifier, the signal is divided into two paths of signals through the power divider: one path of radio frequency signal is detected by a detector and then outputs detection pulse, and is converted into a differential signal by a matching differential conversion chip AM26C31 to be directly output by a control connector;
the other path of radio frequency signal adjusts the circuit power to the power suitable for the normal work of the programmable frequency divider through devices such as a gain amplifier, a low-pass filter, a gain adjusting network and the like; the frequency divider divides the frequency of the radio frequency signal by 32 to generate an intermediate frequency signal of 93.75 MHz-156.25 MHz; the intermediate frequency signal is processed by an intermediate frequency processing circuit directly after low-pass filtering and high-frequency noise filtering.
The intermediate frequency processing circuit receives an intermediate frequency signal of 93.75 MHz-156.25 MHz output by the radio frequency processing circuit, and carries out AD sampling on the intermediate frequency signal, wherein a sampling clock signal is 500 MHz; after the intermediate frequency sampling signal is subjected to digital down conversion, digital low-pass filtering, parallel differential complex multiplication and multipoint average filtering in the FPGA, a CMOS level frequency code is output, after the intermediate frequency sampling signal is converted into a 5VTTL level through a driver, a 11bit frequency code is parallelly output, a differential TTL level is converted through a second differential conversion chip AM26C31, and finally the differential TTL level is externally output through a control connector.
Example 1
As shown in fig. 3, the rf processing circuit mainly includes a limiter, a low noise amplifier, a band pass filter, a power divider, a gain amplifier, an eight frequency divider, an attenuator, a four frequency divider, and a low pass filter, and meets the following requirements:
1) receiving and carrying out low-noise amplification and filtering on an externally input radio frequency signal to meet the requirements of the power and the quality of an input signal of the frequency divider;
2) frequency division filtering processing is carried out on the radio frequency signals to obtain intermediate frequency signal frequency required by an intermediate frequency processing circuit;
3) the input radio frequency signal dynamic control is realized, and the input requirement of a detection circuit is met;
4) the requirements of receiving dynamic state and sensitivity of the frequency measuring module are met.
Example 2
As shown in fig. 4, the intermediate frequency processing circuit mainly comprises an FPGA, a DC/DC power chip, an LDO power chip, an active temperature compensation crystal oscillator, an ADC chip, a FLASH, a driver chip, a clock distributor, and a connector, and meets the following requirements:
1) completing the conversion of an external power supply and providing a power supply for the intermediate frequency processing circuit;
2) providing a sampling clock and a reference clock for the ADC and the FPGA;
3) completing AD sampling of the input signal;
4) completing the level conversion of the FPGA output frequency code;
5) and finishing peripheral circuit design and Flash loading configuration of the FPGA.
The ADC chip mainly completes sampling of intermediate frequency signals, and then transmits sampling data to the FPGA through the high-speed parallel IO port for subsequent processing. The FPGA is a core chip of the module and completes functions of ADC sampling data receiving, frequency measurement algorithm realization and the like. The power supply module adopts a mode of a DC/DC power supply chip and an LDO power supply chip to provide stable voltage for the intermediate frequency processing module and the radio frequency processing module. And the driving chip completes the level conversion of the FPGA output frequency code. The active temperature compensation crystal oscillator provides high-precision and high-stability sampling frequency for the ADC and reference frequency of the FPGA.
The following key technologies are involved:
1. multipoint averaging technique:
the phase difference method theoretically only needs two sampling points to estimate the frequency of the signal, and the function of instantaneous frequency measurement is easy to realize. And calculating two adjacent sampling points for frequency measurement of the input complex signal, wherein the frequency measurement range is the sampling bandwidth. In practice, a signal to be measured is easily affected by different degrees of noise interference and IQ amplitude inconsistency to generate large interference on time domain phase difference method frequency measurement, and when the signal-to-noise ratio is low and the IQ amplitude inconsistency is large, the frequency measurement performance becomes poor. According to the irrelevance of noise at different moments, a multipoint averaging method can be utilized, namely N frequency measurement values are averaged in a short time, and the effect is equivalent to that the variance of frequency measurement precision is reduced by N times. The frequency measurement precision can be simply and effectively improved by utilizing a multipoint averaging method, the speed of realizing the accumulation summation operation by hardware is faster and faster along with the development of a programmable logic device, and the frequency measurement time can be ensured. The influence of IQ amplitude inconsistency on phase difference is considered, a digital down-conversion method can be adopted, orthogonal conversion is carried out after ADC sampling, and the influence of IQ amplitude inconsistency on frequency measurement errors caused by analog down-conversion can be avoided.
2. Complex multiplication and inverse tangent technique:
according to the frequency measurement algorithm principle and the matlab simulation result, the instantaneous frequency measurement algorithm is realized in the FPGA by using a Verilog language in practical engineering application. The detailed hardware implementation inside one embodiment of the FPGA is shown in fig. 5.
The FPGA completes the frequency measurement algorithm realization part of the transient measurement module of the system. The method has the main functions of receiving an intermediate frequency 500MHz sampling input signal, converting the intermediate frequency 500MHz sampling input signal into a 2-path 250MHz parallel structure after serial-parallel conversion, respectively performing digital down-conversion and digital low-pass filtering to form an IQ baseband signal, forming parallel 4-path 250M signal streams after time delay, performing complex multiplication and arc tangent operation to complete calculation of a differential phase, and realizing accurate frequency measurement after multi-point average filtering.
The complex multiplication and inverse tangent part is the core of the algorithm, and with the wide application of the integrated hardware multiplier in FPGA and the CORDIC algorithm in signal processing, the complex multiplication and inverse tangent part can be realized by directly calling an IP core.
Analyzing key technical indexes:
frequency measurement precision (less than or equal to 3MHz (r.m.s))
The frequency measurement accuracy mainly depends on several factors, generally speaking, the frequency measurement accuracy is composed of the sampling bit number of the intermediate frequency AD, the frequency stability of the reference clock, the system thermal noise, the device nonlinearity, the power supply and other factors.
The following two main factors are now analyzed:
1. AD sampling bit number calculation
The system requires that the frequency measurement precision reaches 3MHz (RMS), and the differential phase of two adjacent sampling points is calculated according to a frequency measurement formula
Wherein f isdTo be measured at intermediate frequency, fSThe sampling frequency is 500 MHz.
Therefore, it is
While inputting the radio frequency
In MHz. Assuming minimum error of frf_min_errAt 3MHz, the normalized minimum error of the differential phase is
Tangent after conversion to radianThe LSB of the required ADC is tan (3 pi/8000) 0.001178, so that the number of sampling bits for obtaining the ADC cannot be less than 10 bits, and the accuracy requirement of the system can be met. In the design, AD9434 of ADI company is used, the sampling digit is 12 bits, and the actual effective sampling digit ENOB is 10.5, so that the requirement of system precision is met.
2. Reference clock frequency stability calculation
The stability of the reference clock affects the amplitude error between two adjacent sampling points according to the formula
It can be seen that the error of the sampling clock causes the error of the final frequency measurement result to be amplified by 16 times, so that the frequency stability needs to be ensuredrf_min_errThe frequency stability of 500MHz can not be less than 0.000375MHz because of 3MHz/16 MHz 0.1875MHz, the design adopts 500MHz temperature compensation crystal oscillator, the frequency stability is 10-6, and the requirement of the system is met.
Pulse Signal Width (0.1 us-continuous wave)
The frequency measuring machine samples and measures the frequency of the signal near the front edge of the pulse signal, and can adapt to radio frequency signals ranging from 0.1us to continuous waves. Thus meeting the system pulse signal width requirement.
Measuring frequency time (less than or equal to 250ns)
As shown in fig. 6, the intermediate frequency part is divided into 4 parts: serial-parallel conversion, digital down-conversion and differential multiplication, inverse tangent and multipoint average filtering.
A simulation tool is utilized to realize a frequency measurement algorithm in a system generator based on MATLAB, wherein a certain time is consumed when data flow passes through each module, and the time when the data in each step are normally output can be accurately reached through simulation. When a 4GHz signal is input in a simulation mode, the time when the sampled data passes through each step is respectively recorded as t1, t2, t3 and t4, t1 is 1933, t2 is 1960, t3 is 1981 and t4 is 1993, and thus the time consumed by each module is respectively calculated. The clock period consumed for converting the intermediate frequency part from serial-parallel connection to stable intermediate frequency measurement value output is t4-t1 which is 60 clock periods, each clock period consumes 4ns, and the total time is 240 ns. Therefore, the technical index requirements are met.
All the above components are prior art, and those skilled in the art can use any model and existing design that can implement their corresponding functions.
The foregoing is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, many modifications and improvements can be made without departing from the inventive concept, and all of them belong to the protection scope of the present invention.
Claims (5)
1. The broadband digital frequency measurement module is characterized by comprising a radio frequency processing circuit, an intermediate frequency processing circuit, a detection circuit and a power supply circuit,
the radio frequency processing circuit is used for receiving a 3 GHz-5 GHz radio frequency signal, outputting the signal to the intermediate frequency processing circuit for processing after amplification, 32 frequency division amplification and filtering,
the intermediate frequency processing circuit is used for receiving intermediate frequency signals output by the radio frequency processing circuit, carrying out AD sampling, carrying out digital down conversion, parallel differential complex multiplication and multipoint average filtering processing on the intermediate frequency sampling signals in the FPGA, outputting CMOS level frequency codes, converting the CMOS level frequency codes into 5VTTL levels through a driver, parallelly outputting 11bit frequency codes, finally converting the 11bit frequency codes into differential TTL levels through a second differential conversion chip,
the detection circuit is used for detecting the received 3-5 GHz radio frequency signals, outputting detection pulses and judging whether the input signal power of the frequency measurement module is lower than the receiving sensitivity,
the power supply circuit is used for accessing DC24V direct current voltage input from the outside, and provides a low-ripple low-voltage direct current power supply for the radio frequency processing circuit, the intermediate frequency processing circuit and the detection circuit through the DC/DC conversion circuit and the low dropout regulator LDO.
2. The wideband digital frequency measuring module according to claim 1, wherein the rf processing circuit comprises a limiting low noise amplifier, a 3 GHz-5 GHz band pass filter, a power divider, a gain amplifier, a 5GHz low pass filter, a quartering device, a 1.2GHz low pass filter, an eight frequency divider, and a 160MHz low pass filter, which are connected in sequence, the limiting low noise amplifier is connected to the rf signal input, the power divider is further connected to the detection circuit, and the 160MHz low pass filter is connected to the if processing circuit.
3. The wideband digital frequency measuring module as claimed in claim 2, wherein the detector circuit comprises a detector, a high speed comparator and a first differential conversion chip connected in sequence, the detector is connected to the power divider, and the first differential conversion chip outputs the detection signal.
4. The wideband digital frequency measurement module according to claim 3, wherein the intermediate frequency processing circuit includes an ADC chip, an FPGA, a level conversion circuit and a second differential conversion chip connected in sequence, the FPGA and the ADC chip are further connected to a clock generator, the ADC chip is connected to a 160MHz low-pass filter, and the second differential conversion chip outputs a frequency measurement signal.
5. The wideband digital frequency measuring module as claimed in claim 4, wherein the first differential conversion chip and the second differential conversion chip are AM26C31 differential conversion chips.
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| CN113721203A (en) * | 2021-09-01 | 2021-11-30 | 扬州宇安电子科技有限公司 | Simple radar radio frequency signal detection display method |
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