CN112666392A - Carrier frequency measuring circuit and method of high-speed pulse modulation signal - Google Patents
Carrier frequency measuring circuit and method of high-speed pulse modulation signal Download PDFInfo
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Abstract
The invention discloses a carrier frequency measuring circuit and a method of a high-speed pulse modulation signal, belonging to the technical field of frequency measurement, the invention realizes frequency conversion compression of the signal through a variable frequency divider, filters harmonic components of more than 3 times of the frequency divider through a filter, reserves phase information of the signal, and has simple frequency conversion scheme; the phase extraction of the pulse modulation signal is realized through the control signal generating unit and the digital IQ demodulation unit, the noise interference during the off period of the pulse modulation is avoided, the rapid extraction and calculation of the phase of the pulse modulation signal are realized, and finally the carrier frequency measurement of the high-speed pulse modulation signal is realized; the invention can realize the carrier frequency measurement of the pulse repetition frequency 10MHz high-speed pulse modulation signal, the measurement time is 8ns (rate 125MHz) fastest, the measurement scheme is simple, and the cost is low; the carrier frequency of the high-speed pulse modulation signal can be quickly measured, and the change of the carrier frequency of the pulse modulation signal can be tracked and measured.
Description
Technical Field
The invention belongs to the technical field of frequency measurement, and particularly relates to a carrier frequency measurement circuit and method of a high-speed pulse modulation signal.
Background
The pulse modulation signal is an important signal in radar and digital communication systems, and with the development of electronic technology, the Pulse Repetition Frequency (PRF) of the pulse modulation signal is continuously improved, the pulse width is smaller and smaller, the pulse modulation carrier is complex and changeable, and the measurement is more difficult.
Two methods are mainly used for measuring the carrier frequency of the pulse modulation signal, one method is a frequency spectrograph measuring method, the measured signal is subjected to frequency mixing and frequency conversion for multiple times to obtain an intermediate frequency signal, the intermediate frequency signal is subjected to FFT (fast Fourier transform) to obtain frequency spectrum information, and the carrier signal frequency is obtained according to the frequency spectrum information.
The second method is a counter frequency measurement method, as shown in FIG. 1, a gate is first set by measuring the gate time T and the number of signal times N in the gate0Using f ═ N0and/T calculating the frequency of the measured signal. In the measurement, the measured signal and the measurement gate are synchronized, so that the number of the measured signal can be accurately measured without error, but an error exists in the gate time measurement, as shown in the figure, T1 and T2 are measurement errors. The maximum measurement error is the measurement clock period. The error in the short-time measurement is very influential. To reduce the measurement error, interpolation is usually used to measure T1 and T2.
The defects of the prior art are as follows:
(1) the scheme for measuring the pulse carrier frequency by adopting the frequency spectrograph is complex and high in cost. The frequency spectrograph adopts a frequency sweeping scheme, and when the carrier frequency of the pulse modulation signal changes, the frequency spectrum is limited by the frequency sweeping speed of the frequency spectrograph, so that the signal with the rapidly changed frequency cannot be tracked and measured.
(2) By adopting a counter method, if interpolation is not needed, the frequency measurement precision is low; the interpolation method is adopted, the measuring speed is slow, such as 53200 series frequency meter of German company in the United states, the shortest measuring time is 1us (rate is 1MHz),
disclosure of Invention
Aiming at the technical problems in the prior art, the invention provides the carrier frequency measuring circuit and the carrier frequency measuring method of the high-speed pulse modulation signal, which are reasonable in design, overcome the defects of the prior art and have good effects.
In order to achieve the purpose, the invention adopts the following technical scheme:
a carrier frequency measuring circuit of a high-speed pulse modulation signal comprises a power divider, a controllable frequency divider, a filter, an AD converter, an FPGA, a comparator and a detector; the power divider, the controllable frequency divider, the filter, the AD converter, the FPGA, the comparator and the detector are sequentially connected through a circuit;
the power divider is configured to divide the measured signal into two paths;
a controllable frequency divider configured to implement frequency translation compression of a signal;
a filter configured to filter out 3 rd order and above harmonic components after frequency division;
an AD converter configured to convert an analog signal into a digital signal;
a detector configured to detect a detected signal envelope waveform and output a detected signal;
a comparator configured to change the detected signal into a digital signal;
an FPGA configured to perform digital IQ demodulation and output a carrier frequency of a pulse modulated signal;
the measured signal is divided into two paths by a power divider, one path enters a controllable frequency divider, the controllable frequency divider outputs an intermediate frequency signal to a filter through frequency dividing ratio setting, the filter filters 3 times or more harmonic components after frequency division, the filter outputs the signal to an AD converter, and the AD converter samples the signal and then sends the signal to an FPGA;
and the second path of signal enters a detector, the detector detects the envelope waveform of the detected signal and outputs a detection signal to a comparator, the comparator converts the detection signal into a digital signal and sends the digital signal to the FPGA, an external digital local oscillation signal and an output signal of the AD converter carry out digital IQ demodulation in the FPGA, and the digital local oscillation frequency is a middle value of an intermediate frequency range.
Preferably, the FPGA includes a control signal generation unit, a digital IQ demodulation unit, a phase calculation unit, and a frequency calculation unit; the control signal generating unit, the digital IQ demodulating unit, the phase calculating unit and the frequency calculating unit are sequentially connected through a line;
a control signal generating unit configured to compare arrival times of the AD converter output signal and the comparator output signal, delay and intercept the comparator output signal, and output a control gate signal shorter than the comparator output signal, for controlling an operation period of the digital IQ demodulating unit, so that the digital IQ demodulating unit operates during a pulse-on period and does not operate during a pulse-off period, thereby obtaining effective pulse modulation carrier frequency information;
the digital IQ demodulation unit carries out IQ frequency mixing on an external digital local oscillation signal and an output signal of the AD converter to demodulate an I path signal and a Q path signal;
the phase calculation unit is configured to operate the I-path signal and the Q-path signal to obtain the phase of the pulse modulation signal;
and the frequency calculation unit is configured to obtain the carrier frequency of the pulse modulation signal according to the phase change.
In addition, the invention also provides a carrier frequency measuring method of the high-speed pulse modulation signal, which adopts the carrier frequency measuring circuit of the high-speed pulse modulation signal, and specifically comprises the following steps:
step 1: dividing a detected signal into two paths through a power divider, wherein one path of the detected signal enters a controllable frequency divider, and the other path of the detected signal enters a detector;
step 2: the frequency conversion compression of the signal is realized through a controllable frequency divider, and the controllable frequency divider outputs an intermediate frequency signal to a filter through frequency dividing ratio setting;
and step 3: filtering 3-order and above harmonic components after frequency division by a filter, and outputting a signal to an AD converter by the filter;
and 4, step 4: the AD converter performs analog-to-digital conversion on the signal and then sends the signal to the FPGA;
and 5: through the control signal generating unit, the arrival time of the output signal of the AD converter and the output signal of the comparator is compared, the output signal of the comparator is delayed and cut off, and a control gate signal which is shorter than the output signal of the comparator is output and is used for controlling the working time period of the digital IQ demodulation unit, so that the digital IQ demodulation unit works in the pulse on period and does not work in the pulse off period, and the effective pulse modulation carrier frequency information is obtained;
step 6: carrying out IQ frequency mixing on an external digital local oscillator signal and an output signal of the AD converter through a digital IQ demodulation unit, and demodulating an I path signal and a Q path signal;
and 7: calculating the I path signal and the Q path signal through a phase calculation unit to obtain the phase of the pulse modulation signal;
and 8: and obtaining the carrier frequency of the pulse modulation signal according to the phase change by a frequency calculation unit.
The invention has the following beneficial technical effects:
the invention realizes the frequency conversion compression of the signal through the variable frequency divider, filters the harmonic component of more than 3 times of the frequency divider through the filter, reserves the phase information of the signal, and has simple frequency conversion scheme; the phase extraction of the pulse modulation signal is realized through the control signal generating unit and the digital IQ demodulation unit, the noise interference during the off period of the pulse modulation is avoided, the rapid extraction and calculation of the phase of the pulse modulation signal are realized, and finally the carrier frequency measurement of the high-speed pulse modulation signal is realized;
the invention can realize the carrier frequency measurement of the pulse repetition frequency 10MHz high-speed pulse modulation signal, the measurement time is 8ns (rate 125MHz) fastest, the measurement scheme is simple, and the cost is low; the carrier frequency of the high-speed pulse modulation signal can be quickly measured, and the change of the carrier frequency of the pulse modulation signal can be tracked and measured.
Drawings
Fig. 1 is a schematic diagram of frequency measurement of a counter.
Fig. 2 is a schematic block diagram of a circuit for measuring carrier frequency of a high-speed pulse modulated signal according to the present invention.
FIG. 3 is a diagram of two paths of signal timing and control signals entering the FPGA.
Detailed Description
The invention is described in further detail below with reference to the following figures and detailed description:
as shown in fig. 2, a signal to be measured is divided into two paths by a power divider, one path enters a variable frequency divider, and the variable frequency divider changes the signal to be measured into a fixed intermediate frequency range, such as (20 MHz-50 MHz), by setting a frequency dividing ratio; the frequency divider outputs an intermediate frequency signal to enter a filter, the filter is used for filtering 3 or more harmonic components after frequency division, and the filter can be set as a 50MHz low-pass filter; the output signal of the filter enters an AD converter, the AD converter samples the signal at a high speed and sends the signal to the FPGA, and the sampling frequency is 250 MHz;
the second path of signal passes through a detector to detect the envelope waveform of the detected signal; the detection signal is converted into a digital signal through a comparator, the digital signal is sent to the FPGA, an external digital local oscillation signal is sent to the FPGA for digital IQ demodulation, and the digital local oscillation frequency is a middle value (35MHz) of an intermediate frequency range.
The FPGA is divided into four units: the device comprises a control signal generating unit, a digital IQ demodulating unit, a phase calculating unit and a frequency calculating unit.
Because the paths and device delays passed by the two signals are different, the time of the two signals reaching the FPGA is different, as shown in FIG. 3. A control signal generating unit in the FPGA delays and cuts an output signal of a comparator by comparing the arrival time of the output signal of the AD converter with the arrival time of the output signal of the comparator, outputs a control gate signal (the difference between the front edge and the rear edge is 5ns) which is shorter than the output signal of the comparator, and is used for controlling the working time period of a digital IQ demodulating unit, so that the digital IQ demodulating unit works during the pulse on period and does not work during the pulse off period, thereby obtaining effective pulse modulation carrier frequency information and avoiding clutter interference during the pulse off period.
The digital IQ demodulation unit carries out IQ frequency mixing on an output signal of the AD converter and an external digital local oscillation signal to output an I path signal and a Q path signal, the I path signal and the Q path signal are operated in the phase calculation unit to obtain the phase of the signal, each sampling point output by the AD converter can calculate a phase, the frequency calculation unit obtains the frequency of a carrier signal according to the phase change, the sampling rate of the AD converter is 250MHz, 4ns can obtain one sampling point, 8ns can obtain two sampling points, and the phases of the two sampling points are assumed to be respectively
The intermediate frequency f1 is calculated as
Assuming that the digital local oscillation frequency is f2, the frequency division ratio of the frequency divider is N, and the frequency f of the signal to be measured is (f1+ f2) × N. Because the AD converter can continuously sample, the frequency calculation unit can continuously calculate the signal frequency and perform tracking measurement on the change of the carrier frequency of the pulse modulation signal.
It is to be understood that the above description is not intended to limit the present invention, and the present invention is not limited to the above examples, and those skilled in the art may make modifications, alterations, additions or substitutions within the spirit and scope of the present invention.
Claims (3)
1. A carrier frequency measuring circuit of a high-speed pulse modulation signal is characterized in that: the frequency divider comprises a power divider, a controllable frequency divider, a filter, an AD converter, an FPGA, a comparator and a detector; the power divider, the controllable frequency divider, the filter, the AD converter, the FPGA, the comparator and the detector are sequentially connected through a circuit;
the power divider is configured to divide the measured signal into two paths;
a controllable frequency divider configured to implement frequency translation compression of a signal;
a filter configured to filter out 3 rd order and above harmonic components after frequency division;
an AD converter configured to convert an analog signal into a digital signal;
a detector configured to detect a detected signal envelope waveform and output a detected signal;
a comparator configured to change the detected signal into a digital signal;
an FPGA configured to perform digital IQ demodulation and output a carrier frequency of a pulse modulated signal;
the measured signal is divided into two paths by a power divider, one path enters a controllable frequency divider, the controllable frequency divider outputs an intermediate frequency signal to a filter through frequency dividing ratio setting, the filter filters 3 times or more harmonic components after frequency division, the filter outputs the signal to an AD converter, and the AD converter samples the signal and then sends the signal to an FPGA;
the second path of signal enters a detector, the detector detects the envelope waveform of the detected signal and outputs a detection signal to a comparator, the comparator converts the detection signal into a digital signal and sends the digital signal to the FPGA, and the external digital local oscillation signal and the output signal of the AD converter perform digital IQ demodulation in the FPGA.
2. The carrier frequency measurement circuit of a high-speed pulse modulated signal according to claim 1, characterized in that: the FPGA comprises a control signal generation unit, a digital IQ demodulation unit, a phase calculation unit and a frequency calculation unit; the control signal generating unit, the digital IQ demodulating unit, the phase calculating unit and the frequency calculating unit are sequentially connected through a line;
a control signal generating unit configured to compare arrival times of the AD converter output signal and the comparator output signal, delay and intercept the comparator output signal, and output a control gate signal shorter than the comparator output signal, for controlling an operation period of the digital IQ demodulating unit, so that the digital IQ demodulating unit operates during a pulse-on period and does not operate during a pulse-off period, thereby obtaining effective pulse modulation carrier frequency information;
the digital IQ demodulation unit carries out IQ frequency mixing on an external digital local oscillation signal and an output signal of the AD converter to demodulate an I path signal and a Q path signal;
the phase calculation unit is configured to operate the I-path signal and the Q-path signal to obtain the phase of the pulse modulation signal;
and the frequency calculation unit is configured to obtain the carrier frequency of the pulse modulation signal according to the phase change.
3. A carrier frequency measurement method of a high-speed pulse modulation signal is characterized in that: the carrier frequency measurement circuit using the high-speed pulse modulated signal according to claim 1, comprising:
step 1: dividing a detected signal into two paths through a power divider, wherein one path of the detected signal enters a controllable frequency divider, and the other path of the detected signal enters a detector;
step 2: the frequency conversion compression of the signal is realized through a controllable frequency divider, and the controllable frequency divider outputs an intermediate frequency signal to a filter through frequency dividing ratio setting;
and step 3: filtering 3-order and above harmonic components after frequency division by a filter, and outputting a signal to an AD converter by the filter;
and 4, step 4: the AD converter performs analog-to-digital conversion on the signal and then sends the signal to the FPGA;
and 5: through the control signal generating unit, the arrival time of the output signal of the AD converter and the output signal of the comparator is compared, the output signal of the comparator is delayed and cut off, and a control gate signal which is shorter than the output signal of the comparator is output and is used for controlling the working time period of the digital IQ demodulation unit, so that the digital IQ demodulation unit works in the pulse on period and does not work in the pulse off period, and the effective pulse modulation carrier frequency information is obtained;
step 6: carrying out IQ frequency mixing on an external digital local oscillator signal and an output signal of the AD converter through a digital IQ demodulation unit, and demodulating an I path signal and a Q path signal;
and 7: calculating the I path signal and the Q path signal through a phase calculation unit to obtain the phase of the pulse modulation signal;
and 8: and obtaining the carrier frequency of the pulse modulation signal according to the phase change by a frequency calculation unit.
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| CN116908537A (en) * | 2023-09-13 | 2023-10-20 | 西安西电高压开关有限责任公司 | Current voltage frequency calculation circuit and method |
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Application publication date: 20210416 |