CN113671456A

CN113671456A - Radar signal processing simulation platform and simulation method

Info

Publication number: CN113671456A
Application number: CN202111091206.6A
Authority: CN
Inventors: 张东洁; 谢毅国; 黎强; 纪要; 陈爱琪; 李玉楠; 潘建华
Original assignee: Nanjing National Electronic Technology Co ltd
Current assignee: Nanjing National Electronic Technology Co ltd
Priority date: 2021-09-17
Filing date: 2021-09-17
Publication date: 2021-11-19

Abstract

A radar signal processing simulation platform and a simulation method are provided. The radar signal processing simulation platform and the simulation method can reduce signal interference and enhance communication stability. The system comprises a radar display and control workstation and a signal processing server which are in communication connection, and further comprises a signal generation and transmission unit; the signal generating and transmitting unit comprises a situation resolving unit, a signal generating unit, a microwave unit and a data transmitting unit; the data transmission unit comprises an FPGA 1; the situation resolving unit comprises a DSP and an FPGA 2; the signal generating unit comprises three DRFM, namely DRFM1, DRFM2 and DRFM 3; the synthesizer is used for synthesizing the target signal and the clutter signal into an echo signal and inputting the echo signal into DRFM2, and the DRFM2 outputs the echo signal to the FPGA 2; the FPGA2 is configured to send the radar signal and the echo signal to the FPGA1, and the FPGA1 is configured to send the radar signal and the echo signal to the signal processing server. The invention can effectively reduce signal distortion.

Description

Radar signal processing simulation platform and simulation method

Technical Field

The invention relates to the technical field of radars, in particular to a radar signal processing simulation platform and a simulation method.

Background

Signal processing plays a crucial role in modern radar systems, both military and civil, which determines the overall performance of the radar. In order to facilitate the research or training of radar signal processing, radar simulation by using a simulation system becomes an important means.

Radar simulation systems generally have three categories: (1) physical simulation, also called physical simulation, refers to simulation based on physical models; (2) mathematical simulation, also known as computer simulation, refers to simulation based on a digital model; (3) mathematic-physical simulation, also called semi-physical simulation, refers to simulation combining a physical model and a mathematical model, and the simulation means is mainly used in practical application.

In the mathematical-physical simulation technology, the key premise lies in how to generate real radar signals, target signals and clutter signals which approximate to the actual application environment. Because the simulation platform needs to simultaneously generate a radar signal, a target signal, a clutter signal and an echo signal synthesized by the target signal and the clutter signal, how to effectively generate the signals and avoid mutual interference is the key of the simulation platform. The radar signal processing is mainly used for processing and analyzing radar echo signals, so that the performance of AD sampling of echo intermediate frequency signals is of great importance to the subsequent signal processing effect of the invention. The simulation platform aims to enable a user to deeply understand the characteristics of the radar signal and the radar signal processing algorithm, so how to display the result, situation and algorithm selection in the middle process is also the key for realizing the simulation platform.

Chinese patent CN112578346A discloses a broadband radar target echo signal simulation system and a simulation method, which includes a main control computer, a signal processor and a radio frequency machine; the radio frequency machine comprises an up-conversion module, a signal synthesis module and a down-conversion module. The up-conversion module up-converts the target signal and the radar signal; sending the target signal to a signal synthesis module, sending the radar signal to complex electromagnetic environment simulation equipment to simulate clutter, and sending the clutter to the signal synthesis module; and finally, the signal synthesis module synthesizes and down-converts the target signal and the clutter signal and inputs the target signal and the clutter signal into a signal acquisition module of the signal processor. The technical solution in this document has two disadvantages: the clutter signals are generated by two-stage transmission of a signal generation module, an up-conversion module and complex electromagnetic environment simulation equipment, and the signal interference risk is large; and secondly, the design of feedback verification aiming at radar signals is not provided, so that error risk and poor communication reliability exist.

Therefore, how to improve the fidelity and reliability of signal transmission becomes a technical problem to be solved urgently.

Disclosure of Invention

Aiming at the problems, the invention provides a radar signal processing simulation platform and a simulation method which can reduce signal interference and enhance communication stability.

The technical scheme of the invention is as follows:

a radar signal processing simulation platform comprises a radar display and control workstation and a signal processing server which are in communication connection,

the device also comprises a signal generating and transmitting unit; the signal generating and transmitting unit comprises a situation resolving unit, a signal generating unit, a microwave unit and a data transmitting unit;

the data transmission unit comprises an FPGA 1;

the situation resolving unit comprises a DSP and an FPGA 2;

the microwave unit comprises a synthesizer;

the signal generating unit comprises three DRFM, namely DRFM1, DRFM2 and DRFM 3;

the DSP is used for receiving working parameters from the radar display control workstation, resolving the working parameters and sending the working parameters to the FPGA 2; the FPGA2 is used for respectively issuing radar parameters, target parameters and clutter parameters generated by the working parameters to DRFM1, DRFM2 and DRFM 3;

the DRFM1 is used for generating radar signals and feeding the radar signals back to the FPGA 2;

the DRFM2 is used for generating a target signal and inputting the target signal into the synthesizer, and the DRFM3 is used for generating a clutter signal and inputting the clutter signal into the synthesizer;

the synthesizer is used for synthesizing the target signal and the clutter signal into an echo signal and inputting the echo signal into DRFM2, and the DRFM2 outputs the echo signal to the FPGA 2; the FPGA2 is configured to send the radar signal and the echo signal to the FPGA1, and the FPGA1 is configured to send the radar signal and the echo signal to the signal processing server.

The microwave unit is also provided with an up-conversion module, and the up-conversion module is used for receiving the radar signal of the DRFM1 and performing up-conversion processing on the radar signal; the up-conversion module is connected with an SMA radio frequency interface.

The DRFM comprises an FPGA, an EEPROM, an SRAM, a D/A converter, an A/D converter and a clock generator;

the FPGA is used as a main processor of the DRFM, the EEPROM and the SRAM are used for storing programs and data, the D/A converter and the A/D converter are respectively used for digital-to-analog conversion and analog-to-digital conversion, and the clock generator is used for generating clock signals.

The A/D converter adopts an ADS5500 chip; in a reference clock input circuit of the ADS5500 chip, an adjustable resistor Rt is connected in series between a first-stage clock input end CLKP and a second-stage clock input end CLKM of the ADS5500 chip.

The analog clock input circuit of the ADS5500 chip comprises a transformer T1 and two band-pass filters;

the analog signal is input from the primary side of T1, and is output to the two band-pass filters in two paths from the secondary side of T1;

the band-pass filter comprises a resistor R1, an inductor L1 and a capacitor C1, wherein the inductor L1 is connected with the capacitor C1 in parallel and then connected with a resistor R1 in series; analog signals flow in from the resistor R1 side of the band-pass filter and then are output to the INP port of the ADS5500 chip;

the other band-pass filter comprises a resistor R2, an inductor L2 and a capacitor C2, wherein the inductor L2 is connected with the capacitor C2 in parallel and then connected with a resistor R2 in series; the analog signal flows from the resistor R2 side of the band-pass filter and then is output to the INM port of the ADS5500 chip.

A deburring filter is also connected between the two band-pass filters in series;

the deburring filter comprises a resistor R3, a capacitor C3 and a resistor R4 which are sequentially connected in series, wherein R3 is R4.

The analog clock input circuit is also provided with a low-pass filter;

the low-pass filter comprises a capacitor C4, a capacitor C5 and a resistor R6, wherein the capacitor C4 is connected with the capacitor C5 in parallel and then connected with the resistor R6 in series; one end of the low-pass filter is connected with a secondary central tap of the T1, and the other end of the low-pass filter is connected with a CM port of the ADS5500 chip.

A radar signal processing simulation method comprises the following steps:

1) the radar display and control workstation defines working parameters and sends the working parameters to a DSP of the situation resolving unit;

2) the DSP calculates the working parameters and sends the working parameters to the FPGA 2;

3) the FPGA2 respectively issues radar parameters, target parameters and clutter parameters in the working parameters to three DRFM which are marked as DRFM1, DRFM2 and DRFM 3; the DRFM1 generates and feeds back radar signals to the FPGA 2; the DRFM2 generates a target signal and inputs the target signal into the synthesizer, and the DRFM3 generates a clutter signal and inputs the clutter signal into the synthesizer;

4) the synthesizer synthesizes the target signal and the clutter signal into an echo signal and inputs the echo signal into DRFM2, and DRFM2 samples and down-converts the echo signal and inputs the echo signal into FPGA 2;

5) the FPGA2 sends radar parameters and echo signals, which are collectively called signal data, to the FPGA1, and the FPGA1 sends the signal data to a signal processing server;

6) and the signal processing server processes the signal data and sends the processing result to the radar display and control workstation for display.

In the step 6), the signal processing step of the signal processing server is:

s1, reading signal data;

s2, judging whether the pulse compression processing is needed, if yes, performing the pulse compression processing; if not, directly entering S3;

s3, judging whether MTI processing is needed, if yes, selecting an MTI order and performing MTI processing; if not, directly entering S4;

s4, judging whether the MTD processing is needed, if so, selecting an MTD order and performing the MTD processing; if not, directly entering S5;

s5, selecting a CFAR type, and performing CFAR processing;

s6, forming a dot trace;

and S7, correlating the flight path, and sending the processing result to a radar display control workstation for display.

According to the radar signal processing simulation platform and the simulation method, the working parameters set by the upper computer are respectively issued to the three DRFM, the three DRFM are respectively used for generating radar signals, target signals and clutter signals, the three signals are mutually independent and have no indirect transmission, the anti-interference performance is strong, and meanwhile, the design of the simulation platform also reduces the hardware complexity. The invention also carries out feedback verification design aiming at radar signals, radar parameters are issued to DRFM1 through FPGA2, and the DRFM1 generates radar signals, and the radar signals are subjected to sampling and down-conversion processing and then fed to FPGA 2; the loop feedback can enhance the stability and fault tolerance of the communication system and ensure stable and reliable communication.

On the other hand, in the simulation platform, a reference clock input circuit and an analog clock input circuit of an ADC in the DRFM are innovatively designed; the reference clock input circuit effectively improves the performance of the ADC clock input end by externally connecting an adjustable resistor to the chip; the analog clock input circuit adopts a circuit structure with double band-pass filter coupling and burr absorption to realize the removal of out-of-band signals, and the structure has better amplitude-phase balance characteristic than the traditional circuit, thereby improving the sampling precision of signals and effectively reducing the signal distortion.

Drawings

Figure 1 is a schematic view of the structure of the present invention,

figure 2 is a schematic view of the principle of the invention,

figure 3 is a schematic block diagram of a data transmission unit according to the invention,

figure 4 is a schematic block diagram of a situation resolution unit of the present invention,

figure 5 is a functional block diagram of a motherboard according to the invention,

figure 6 is a functional block diagram of DRFM2 in an embodiment of the invention,

FIG. 7 is a schematic view showing the structure of an ADS5500 chip of the present invention,

figure 8 is a graph of the impedance of the input pin of the ADC of the present invention versus frequency,

figure 9 is a reference clock input circuit for an ADC of the present invention,

figure 10 is an analog clock input circuit of a prior art ADC,

figure 11 is an analog clock input circuit of an ADC of the present invention,

figure 12 is a schematic diagram of the center frequency and bandwidth of the bandpass filter of the present invention,

figure 13 is a schematic diagram of the structure of display control software in the present invention,

figure 14 is a schematic diagram of a prior art canceller,

fig. 15 is a schematic flow chart of signal processing in the present invention.

Detailed Description

The invention is further described below with reference to fig. 1-15.

The related terms in the present invention: the FPGA is a field programmable logic gate array; DRFM is digital radio frequency module; the DSP is a digital signal processor; DDR is a double rate synchronous dynamic random access memory; the EEPROM is a charged erasable programmable read-only memory; the SRAM is a static random access memory; ADC is short for A/D converter; MTI indicates a target indication; MTD indicates target detection; CFAR refers to constant false alarm rate.

The invention relates to a radar signal processing simulation platform which comprises a radar display and control workstation and a signal processing server which are in communication connection; the radar display and control workstation is used for setting a battle situation and displaying a situation; the signal processing server is used for receiving the radar signal data and the echo signal data, performing signal processing and characteristic analysis, and sending a processing result to the radar display and control workstation for displaying;

the data transmission unit comprises an FPGA1 and a DDR, and is also provided with an SFP + interface and a PCIE interface; the DDR is used for data buffering, the SFP + interface is used for receiving radar signal data and echo signal data of the situation resolving unit, and the PCIE interface is used for transmitting data to the signal processing server;

the situation resolving unit comprises a DSP and an FPGA 2; the situation resolving unit is used for receiving the working parameters, resolving information such as distance, attitude, speed and the like of each simulation period according to the simulation beat, and issuing the resolved parameters;

the microwave unit comprises a synthesizer and a clock unit, and the clock unit is used for generating a clock signal;

the DSP is used for receiving the working parameters from the radar display and control workstation, resolving the working parameters and sending the working parameters to the FPGA 2; the FPGA2 is used for respectively issuing radar parameters, target parameters and clutter parameters generated by the working parameters to DRFM1, DRFM2 and DRFM 3;

DRFM1 is used to generate radar signals and feed them back to FPGA 2;

the synthesizer is used for synthesizing the target signal and the clutter signal into an echo signal and inputting the echo signal into the DRFM2, and the DRFM2 which receives the echo signal outputs the echo signal to the FPGA 2; the FPGA2 is used to send radar signals and echo signals to the FPGA1, and the FPGA1 is used to send radar signals and echo signals to the signal processing server.

Example (b): the echo signals synthesized by the synthesizer are transmitted to the FPGA2 via the DRFM2, and a schematic block diagram of the DRFM2 is shown in fig. 6. The 200MHz clock signal generated by the microwave unit is sent to DRFM2, and the 200MHz clock signal generates clock signals required by the work of each chip (including FPGA, EEPROM, SRAM, etc.) of DRFM2 through a clock generator. The FPGA of the DRFM2 receives target parameters sent by the FPGA2 of the situation resolving unit to generate target signals, and the target signals are converted into analog signals through a D/A converter and then sent to the microwave unit through the SMA interface to be used for synthesizing echo signals. The target signal and the clutter signal are sent to a signal input matching circuit for coupling after being synthesized by a microwave unit, then sent to an A/D converter for sampling, the sampled echo signal is sent to an FPGA of DRFM2 for down-conversion to an echo baseband signal, the echo baseband signal is sent to an FPGA2 of a situation resolving unit, then sent to a signal processing server through the FPGA1 for signal processing, and finally a processing result is displayed on a radar display control workstation.

The situation calculation unit, the DRFM1, the DRFM2 and the DRFM3 are all installed on a motherboard, signal transmission is carried out through the motherboard, and a schematic block diagram of the motherboard is shown in FIG. 5. The motherboard mainly includes: 1) the power supply generating circuit is mainly used as a working power supply of each chip and provides a +12V power supply for the microwave unit; 2) the network interface circuit is used for communication between the DSP and the upper computer; 3) the optical fiber interface circuit is used for transmitting the echo signal of the signal generating unit to the data transmission unit; 4) the program downloading port is used for downloading the program; 5) a level shift circuit for level shifting of the internal circuit; 6) the microwave unit control interface is used for sending the generated TTL level frequency control code to the microwave unit; 7) the data interface circuit is used for data transmission between the situation resolving unit and each DRFM; 8) and the state indicating circuit is used for indicating the working state of the situation resolving unit.

The DRFM1 is also internally provided with a sampling module and a down-conversion module; the sampling module and the down-conversion module are respectively used for sampling and down-conversion processing of the radar signals.

The microwave unit is also provided with an up-conversion module, and the up-conversion module is used for receiving the radar signal of the DRFM1 and carrying out up-conversion processing on the radar signal; the up-conversion module is connected with an SMA radio frequency interface. The SMA radio frequency interface is connected to an external interface through a radio frequency cable for signal testing or serving as a signal source of other equipment.

The DRFM comprises an FPGA, an EEPROM, an SRAM, a D/A converter, an A/D converter and a clock generator; the FPGA serves as the main processor for the DRFM, the EEPROM and SRAM for program and data storage, the D/a converter and a/D converter for digital-to-analog and analog-to-digital conversion, respectively, and the clock generator for generating clock signals.

The A/D converter, namely ADC, adopts an ADS5500 chip, and the structure of the A/D converter is shown in figure 7. Wherein Timing circuit is a Timing circuit, CLKOUT is clock Output, S & H is sample hold, 14-bit pipeline ADC Core is a 14-bit pipeline ADC Core, Digital Error Correction is Digital Error Correction, Output Control is Output Control, Internal Reference is Internal Reference, Control Logic is Control Logic, and Serial Programming Register is a Serial Programming Register.

Analyzing the influence of ADC clock jitter on A/D sampling:

SNR of ADC_ADC[dBc]Limited by three factors, namely quantization noise, thermal noise and clock jitter; the signal-to-noise ratios caused by the three are SNR respectively_Quantization _Noise、SNR_Thermal _Noise、SNR_Jitter. Quantization noise and thermal noise generally affect the signal-to-noise ratio at low input frequencies, while clock jitter affects the signal-to-noise ratio at high input frequencies, with the signal-to-noise ratio being calculated as

The signal-to-noise ratio caused by clock jitter is calculated by

SNR_Jitter＝-20·log(2π·f_in·T_Jirrer)

Wherein f is_inIs the input frequency; t is_JitterFor total clock jitter, it has two parts: external clock jitter T_Jitter,extAnd internal aperture dither T_{Aperture_ADC}I.e. by

External clock jitter can be minimized by using a high quality clock source and a bandpass filter at the sample-time clock input, and increasing the clock slew rate can improve internal aperture jitter. As the frequency of the input signal increases, a poor clock jitter performance degrades the signal-to-noise ratio of the overall system. ADC clock jitter is often described in terms of aperture jitter and aperture instability, which are similar in meaning. Aperture instability refers to the variation of sample period to period instability during ADC coding, which has three effects on the system. The first is to increase system noise; secondly, phase instability is brought to the sampling signal; thirdly, mutual interference is brought to ADC coding. In rf or if sampling, low jitter of the ADC clock is important because its a/D sampling has similar analog mixing function, which is equivalent to multiplying the input signal by the sampling clock. The time-domain multiplication is convolution in the frequency domain, which is equivalent to convolution of the spectrum of the sampling clock and the spectrum of the input signal. The aperture instability appears as broadband noise, which appears in the spectrum of the sampling clock. After sampling, the signal spectrum is folded at the sampling frequency, and the noise floor of the ADC output is raised by the wideband noise. In sampling systems where the dynamic range is required to be very high, and the input signal frequency is also very high, the ADC clock must have very low jitter, as is required for the local oscillator in an analog mixer.

Analyzing the influence of phase noise on A/D sampling: the phase noise and clock jitter affect a/D sampling in a slightly different manner, but the resulting effect is very similar. They differ mainly in that: clock jitter is broadband noise, evenly distributed around the sampling clock frequency; the phase noise is distributed unequally, the closer to the main frequency, the larger the phase noise, and the farther away from the main frequency, the smaller the phase noise. As with clock jitter, the smaller the phase noise the better.

Analyzing the influence of the spurious-free dynamic range on A/D sampling: while current high performance a/D sampling chips may provide high resolution and low noise, it may be difficult for designers to achieve nominal SNR performance on a data manual. It may be more difficult to achieve optimal spurious-free dynamic range (SFDR), i.e., to achieve a spurious-free clean noise floor in the system signal chain. Spurious signals may originate from unreasonable circuitry around the ADC and may also be caused by external interference present in harsh operating environments. Spurious-free dynamic range represents the minimum power signal that can be distinguished from a large interfering signal. For current high resolution, precision ADCs, the SFDR generally consists primarily of the dynamic range between the fundamental frequency and the second or third harmonic of the fundamental frequency. However, due to other factors, spurs may be generated and limit the performance of the system. These spurs can be classified as input frequency dependent spurs, which are related to harmonic or non-linear characteristics, and fixed frequency spurs.

Design of reference clock input circuit of ADC:

from the above, clock jitter has a crucial impact on sampling performance. For high input frequency sampling, a very low jitter clock source is typically used, ideally providing a 50% duty cycle. Therefore, in addition to the high requirements for the frequency conversion circuit generating 100MHz clock, the design of the clock input circuit of the a/D sampling chip is also important.

The ADS5500 clock input may be driven with a differential clock signal or a single-ended clock input with little or no difference in performance between the two configurations. However, for optimum performance, it is preferable to drive the clock inputs differentially, thereby reducing susceptibility to common mode noise. In this case, a 0.01 μ F capacitor is preferably used to connect the two clock inputs to the differential input clock signal. The differential resistance and differential capacitance at the input of the ADC vary non-linearly, and FIG. 8 shows the impedance Z across the input pin of the ADC_in(Z_in＝R_in//C_in) A change in situation. Therefore, the input impedance of the ADC must be considered when designing the ADC clock input circuit. In fig. 8: differential Resistance-Differential Resistance, Differential Capacitance-Differential Capacitance.

In the reference clock input circuit of the ADS5500 chip, an adjustable resistor Rt is externally connected between a first-stage clock input terminal CLKP and a second-stage clock input terminal CLKM of the ADS5500 chip, and the resistance value of the adjustable resistor Rt can be adjusted according to the clock frequency adopted by the actual circuit, so as to improve the performance of the reference clock input terminal, as shown in fig. 9.

Design of an analog clock input circuit of the ADC:

the use of differential input topologies for the analog input of the a/D sampling improves the common mode rejection ratio and also results in a very high available input bandwidth, especially for high Intermediate Frequency (IF) or undersampling applications. ADS5500 requires that each analog input port (INP, INM) be externally biased around the common mode level of the internal circuit (CM, pin 17). For a full-scale differential input, each differential line of the input signal (pins 19 and 20) swings symmetrically between VCM +0.575V and VCM-0.575V. This means that each input is driven by a signal up to VCM ± 0.575V, so the maximum differential signal for each input is 1.15Vpp and the total differential input signal swing is 2.3 Vpp. The maximum swing is determined by two reference voltages: a top reference voltage (REFP, pin 29) and a bottom reference voltage (REFM, pin 30). ADS5500 achieves optimal performance when the analog inputs are driven differentially. The analog clock input circuit of the ADC in the prior art is shown in fig. 10, in which: AC Signal Source-an alternating current Signal Source. The single-ended signal is fed into the primary winding of the rf transformer. Since the input signal must be biased towards the common mode voltage of the internal circuitry, the common mode Voltage (VCM) from ADS5500 is connected to the center tap of the secondary winding. The ADS5500 chip manual also provides how to place R_INAnd C_INTo isolate the signal source from the switched input of the ADC and implement a low pass RC filter to limit input noise in the ADC. Any mismatch between the incoming differential lines will result in a degradation of performance at high input frequencies, primarily characterized by an increase in even harmonics. In this case, special care should be taken to maintain as much electrical symmetry as possible between the two.

In the invention, the analog clock input circuit of the ADS5500 chip comprises a transformer T1 and two band-pass filters, as shown in FIG. 11; t1 adopts a transformation ratio of 1: 1 MINI-AT224-1A high-frequency pulse transformer, the highest passing frequency of which is 500 MHz;

the analog signal is input from the primary side of T1, and is output to two band-pass filters from the secondary side of T1 in two paths respectively;

the input-output relationship of the band-pass filter is as follows:

the amplitude ratio T of the output to the input of the band-pass filter is:

wherein, V_outIs the filter output voltage, V_inFor the filter input voltage, j is complex unit, ω is angular frequency, L is inductance, C is capacitance, and R is resistance.

The bandwidth of a bandpass filter is generally defined as the amplitude ratio of

The difference between the upper and lower frequencies in time, i.e., the upper and lower frequency difference when T is 0.707, is shown in fig. 12. Wherein f is₀Is the center frequency,. DELTA.f_3dBNamely, the difference between the upper and lower frequencies when T is 0.707. Quality factor Q ═ f₀/Δf_3dB。

Taking the input signal as 25 + -5 MHz as an example, f₀＝25MHz，Δf _3dB10 MHz. According to

L is 2.7nH, C is 15 nF. Then according to the angular frequency omega of the upper and lower frequencies_3dBThe formula:

or

R is 1 omega; in the formula, the lower bandwidth frequency is taken as-L, and the upper bandwidth frequency is taken as + L.

Referring to fig. 11, a band pass filter includes a resistor R1, an inductor L1, and a capacitor C1, and the inductor L1 is connected in parallel with the capacitor C1 and then connected in series with the resistor R1; the analog signal flows from the resistor R1 side of the band pass filter and is output to the INP port of the ADS5500 chip. The other band-pass filter comprises a resistor R2, an inductor L2 and a capacitor C2, wherein the inductor L2 is connected with the capacitor C2 in parallel and then connected with a resistor R2 in series; the analog signal flows from the resistor R2 side of the band-pass filter and then is output to the INM port of the ADS5500 chip.

A deburring filter is connected between the two band-pass filters in series and is used for absorbing sampling burrs and optimizing input impedance; the deburring filter comprises a resistor R3, a capacitor C3 and a resistor R4 which are sequentially connected in series, wherein R3 is equal to R4, and the deburring filter is used for ensuring the symmetrical absorption of two input ends of the ADC. R3 and R4 can take values of 30-51 omega, and C3 can take values of 22-33 Pf, and the adjustment is carried out according to actual conditions.

The analog clock input circuit is also provided with a low-pass filter for a circuit reference point between the transformer and the sampling chip; the low-pass filter comprises a capacitor C4, a capacitor C5 and a resistor R6, wherein the capacitor C4 is connected with the capacitor C5 in parallel and then connected with the resistor R6 in series; one end of the low-pass filter is connected with a center tap of the secondary of the T1, and the other end is connected with the CM port of the ADS5500 chip.

The implementation result shows that the A/D sampling circuit has higher sampling precision on echo signals, has small signal distortion and improves the reliability of the processing result of a subsequent signal processing algorithm.

The radar display control workstation is provided with display control software; the display control software comprises a parameter configuration software unit, a situation display software unit, a waveform monitoring software unit, a data management software unit, an interface communication software unit and a system control software unit.

The parameter configuration unit comprises radar parameter setting, target parameter setting, clutter parameter setting, signal processing parameter setting and the like. The radar parameter setting includes: (1) various inter-pulse and intra-pulse waveform parameter settings, such as frequency agility point numbers of inter-pulse frequency agility signals, pulse group numbers and frequency agility point numbers of pulse group frequency agility signals, parameter settings of no modulation, various linear frequency modulation and non-linear frequency modulation signals, and various phase encoding signals in a pulse; (2) setting the working mode of the radar, such as the radar works in a tracking state or a scanning (such as circular scanning and fan scanning) state; (3) antenna parameter settings such as antenna gain, side lobe level, scan speed, and beam width. The target parameter setting comprises the following steps: the azimuth and the pitch position of the target, the distance of the target, the heading, the speed, the radar scattering cross-sectional area (RCS), the fluctuation characteristics (such as Swerling 1-4 models and the like), the start-stop time and the like. The clutter parameter setting comprises clutter azimuth, azimuth range, statistical model (such as lognormal distribution, Weibull distribution, K distribution, Rayleigh distribution and the like), and power spectrum model (such as Gaussian spectrum, full polar spectrum, Cauchy spectrum and the like). The signal processing parameter setting includes: (1) signal processing algorithm selection, such as pulse compression, MTI, etc.; (2) and selecting the type of the algorithm, such as the order of the MTI can be selected from 2-5, the order of the MTD can be selected from 4, 8, 16, 32 and 64, the type of the CFAR and the like.

The situation display software unit and the waveform monitoring software unit comprise the following contents: displaying a radar track; radar emission signal I, Q is displayed in orthogonal double channels; radar return signal I, Q is displayed in orthogonal two channels; displaying the envelope of the radar emission signal; displaying the envelope of the radar echo signal; displaying the frequency spectrum of the radar emission signal; displaying the frequency spectrum of the radar echo signal; displaying a pulse compression signal processing result; displaying an MTI signal processing result; displaying the MTD signal processing result; displaying a CFAR signal processing result; and displaying a characteristic analysis signal processing result and the like. The invention has intermediate data output interfaces in the key links of the process matched filtering (pulse compression), clutter suppression, coherent accumulation, target detection, characteristic analysis and the like, so as to be used for analyzing the intermediate processing process. Meanwhile, the data of the original signals and the output results can be stored in the signal processing server and can be directly called when analysis is needed, and algorithm development of scientific research personnel is greatly facilitated.

A radar signal processing simulation method comprises the following steps:

4) the synthesizer synthesizes the target signal and the clutter signal into an echo signal and inputs the echo signal into a DRFM2, and a DRFM2 which receives the echo signal samples and performs down-conversion processing on the echo signal and inputs the echo signal into an FPGA 2;

In the step 3), the DRFM1 generates radar signals, and the radar signals are fed back to the FPGA2 after being sampled and subjected to down-conversion processing. The loop structure is used for carrying out feedback verification on radar signal data, and the stability of a communication system is improved.

In step 6), the signal processing step of the signal processing server is:

s1, reading signal data;

s2, judging whether the pulse compression processing is needed according to whether the signal data is a pulse compression signal, if so, performing the pulse compression processing; if not, directly entering S3;

s5, selecting a CFAR type, and performing CFAR processing;

s6, forming a trace point, namely forming the trace point according to information such as the distance, the direction, the speed and the like of the detection signal;

and S7, respectively carrying out point trace aggregation according to the distance, the direction and the like on each point trace to be dispersed related to the flight path, forming the flight path by the new point trace formed after the point trace aggregation, and sending the processing result to the radar display control workstation for display.

It is said that simple pulse radar has a contradiction between range and range resolution. The radar emission energy E ═ P τ, where P is the emission power and τ is the pulse width. If the radar is far away from the detection distance, a larger transmission energy is needed, and two ways for increasing the transmission energy are available: (1) increase the transmission power, but this is limited by the power tolerance of the radar transmitting device; (2) the pulse width is increased, but a larger pulse width reduces the radar range resolution. Because the radar distance resolution δ is c/2B, where c is the speed of light, i.e. a fixed value, the radar distance resolution δ is inversely proportional to the bandwidth B, and the larger B, the smaller δ, i.e. the higher the radar distance resolution. On the other hand, in the simple pulse radar, B is 1/τ, and therefore, the range resolution δ of the simple pulse radar is c τ/2 as can be seen from the radar range resolution equation. It can be seen that increasing the pulse width increases the radar range, but also decreases range resolution.

The pulse compression technology better solves the contradiction between the range and the range resolution of the conventional pulse radar: the radar transmits wide pulses when transmitting, so that the average power of transmission is improved, and a large action distance is ensured; and narrow pulses are obtained through matching and receiving of the pulse compression network during receiving, so that high distance resolution is ensured. Therefore, a pulse compression radar should be a matched filter system, i.e. it requires the transmitted signal to have a nonlinear phase spectrum, and at the same time, a compression network matched with the transmitted signal spectrum is arranged in the receiver, so that the transmitted signal with wide pulse (i.e. the echo signal at the input end of the receiver) becomes a narrow pulse to maintain good distance resolution. According to the intra-pulse modulation mode, pulse compression radar signals are mainly divided into frequency modulation pulse pressure signals, phase coding pulse pressure signals and mixed modulation pulse pressure signals. The general frequency-modulated pulse pressure signals include linear frequency modulation and various non-linear frequency modulation signals (such as triangular wave frequency modulation and sine wave frequency modulation), and the phase-coded pulse pressure signals include two-phase coding and four-phase coding.

In the radar signal processing, it must first be known whether it is a simple pulse radar or a pulse compression radar. In the case of a simple pulse radar, no matched filtering is required, and in the case of a pulse compression radar, matched filtering must first be performed.

The MTI is a frequency domain filter, which is equivalent to a high pass filter, and is used to suppress stationary targets and slow clutter. In the case of a one-shot cancellation MTI filter, the echo of the first transmit pulse is subtracted from the echo of the second transmit pulse to remove the stationary target and slow clutter, while the information of the moving target is retained and the waveform of the up-and-down vibration in amplitude can be seen by the video display. The MTD is a band pass filter bank, and can be implemented by an FIR bank, but is generally implemented by an FFT, that is, an FFT is performed on the same distance unit of echo signals of different pulse groups. The output of the MTI is a high-pass filtering continuous spectrum after restraining the spectrum around the zero frequency, and the spectrum range is f_L～PRF，f_LThe cut-off frequency at the left end of the high-pass filter; the output of the MTD is obtained by dividing the spectrum from 0 to PRF into N (N is the number of pulses processed at one time, and the size is determined by the beam width, the antenna scanning speed, etc.) equally spaced discrete spectral lines 0, PRF/N,2 PRF/N, …, (N-1) PRF/N, which is aimed at suppressing the noise of the moving platform whose position is not near the frequency 0. This is the most essential difference between MTI and MTD. In addition, the MTD is realized by adding one or more motion clutter maps, so that the radar can detect a large target flying tangentially when the platform moves; moreover, the MTD realizes long-time storage and delay by adopting digital signal processing, and greatly increases the linear dynamic range of signal processing compared with MTI. Both are completely different in implementation. The MTD is a moving target detection technology which is more advanced than the MTI, and can completely replace the MTI, but the MTI is simple to realize and is still largely used in the existing ground radar.

The algorithm type selection is illustrated by taking the MTI order as an example. The clutter canceller is one of the most frequently used MTI filters, and can be divided into two-pulse cancellation (also called first cancellation), three-pulse cancellation (also called second cancellation) and multi-pulse cancellation according to the cancellation times, and the common cancellation is generally below five-pulse cancellation (also called fourth cancellation). The structure of the prior art canceller is shown in fig. 13. The output y of the canceller can be expressed as:

k is the number of times of the canceller, x is the input, n is the number of pulses, ω i is the coefficient of the canceller, and

that is, when the cancellation is performed once (K ═ 1), [ ω 0, ω 1] ═ 1, -1; for second cancellation (K ═ 2), then [ ω 0, ω 1, ω 2] ═ 1, -2,1 ]; for triple cancellation (K ═ 3), then [ ω 0, ω 1, ω 2, ω 3] ═ 1, -3,3,1 ]; when cancellation is performed four times (K ═ 4), [ ω 0, ω 1, ω 2, ω 3, ω 4] ═ 1, -4,6, -4, 1. Therefore, different MTI processing algorithms can be selected by selecting different MTI orders, and the clutter suppression effects of the MTI processing algorithms are compared, so that the understanding of the MTI algorithms is deepened.

Therefore, when radar signals are processed, an MTI algorithm or an MTD algorithm can be selected and adopted according to needs, the MTI algorithm and the MTD algorithm can be adopted at the same time, the MTI algorithm and the MTD algorithm can not be adopted, and sampled echo signals (applicable to simple pulse radar) or matched and filtered signals (applicable to pulse compression radar) directly enter a CFAR signal processing link.

The CFAR detects the above output and determines whether a target exists. CFAR detection is a set of techniques, also known as adaptive threshold detection, that are directed to providing predictable detection and false alarms in real interference environments. In practical applications, many CFAR methods are developed according to various interference environments, such as cell average CFAR (CA-CFAR), various improved cell average CFARs (e.g., small cell average CFAR (SOCA-CFAR), large cell average CFAR (GOCA-CFAR), ordered statistics CFAR (OS-CFAR), adaptive CFAR, and so on. And can be selected as desired.

The disclosure of the present application also includes the following points:

(1) the embodiments disclosed in the present application are only examples, and the technical solutions implemented by other equivalent technical means belong to the scope of protection of the present application;

(2) the technical features disclosed in the present application may be combined with each other to obtain new embodiments, without conflict;

the above embodiments are only examples disclosed in the present application, but the scope of the present disclosure is not limited thereto, and those skilled in the art should, in light of the present disclosure, modify and change some of the technical features of the present disclosure within the scope of the present application.

Claims

1. A radar signal processing simulation platform comprises a radar display and control workstation and a signal processing server which are in communication connection, and is characterized in that,

the data transmission unit comprises an FPGA 1;

the situation resolving unit comprises a DSP and an FPGA 2;

the microwave unit comprises a synthesizer;

2. The radar signal processing simulation platform of claim 1, wherein an up-conversion module is further disposed on the microwave unit, and the up-conversion module is configured to receive the radar signal of the DRFM1 and perform up-conversion processing thereon; the up-conversion module is connected with an SMA radio frequency interface.

3. The radar signal processing simulation platform of claim 1, wherein the DRFM comprises an FPGA, an EEPROM, an SRAM, a D/a converter, an a/D converter, and a clock generator;

4. The radar signal processing simulation platform of claim 3, wherein the A/D converter is an ADS5500 chip; in a reference clock input circuit of the ADS5500 chip, an adjustable resistor Rt is connected in series between a first-stage clock input end CLKP and a second-stage clock input end CLKM of the ADS5500 chip.

5. The radar signal processing simulation platform of claim 4, wherein the analog clock input circuit of the ADS5500 chip comprises a transformer T1 and two band pass filters;

6. The radar signal processing simulation platform of claim 5, wherein a de-burring filter is further connected in series between the two band-pass filters;

7. The radar signal processing simulation platform of claim 6, wherein the analog clock input circuit is further provided with a low-pass filter;

8. A radar signal processing simulation method is characterized by comprising the following steps:

9. The radar signal processing simulation method according to claim 8, wherein in the step 6), the signal processing step of the signal processing server is:

s1, reading signal data;

s5, selecting a CFAR type, and performing CFAR processing;

s6, forming a dot trace;