CN113655456B - Radar active signal source - Google Patents
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- CN113655456B CN113655456B CN202111221308.5A CN202111221308A CN113655456B CN 113655456 B CN113655456 B CN 113655456B CN 202111221308 A CN202111221308 A CN 202111221308A CN 113655456 B CN113655456 B CN 113655456B
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- G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
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Abstract
According to the radar active signal source disclosed by the invention, a frequency synthesis unit is used for generating a down-conversion local oscillator signal, an up-conversion local oscillator signal and a reference clock signal; the down-conversion unit is used for receiving the radio-frequency signals and down-conversion local oscillation signals output by the frequency synthesis unit, performing down-conversion and power conversion on the radio-frequency signals, and outputting intermediate-frequency signals to the intermediate-frequency signal processing unit; the intermediate frequency signal processing unit is used for receiving the intermediate frequency signal output by the down-conversion unit and the reference clock signal output by the frequency synthesis unit, digitally modulating the signal and outputting the modulated signal to the up-conversion unit; the up-conversion unit is used for receiving the signal output by the intermediate frequency signal processing unit and the up-conversion local oscillator signal output by the frequency synthesis unit, mixing and up-converting the signal to an X/Ku wave band and a Ka wave band, and outputting the signal according to the required amplitude. The invention integrates the functions of coherent and non-coherent radar signal simulation of multi-band and complex moving target signals.
Description
Technical Field
The invention relates to the technical field of radar signal sources, in particular to a radar active signal source.
Background
The radar is used as an important device for military avionics detection and positioning, and plays an important role in investigation, positioning, tracking and guided operation in military. The technical system and the working mode of the current radar are numerous, the motion pattern of a detected target signal is complex and changeable, various interference signals can be identified, and the radar can work in a cross-waveband mode in a complex electromagnetic environment. Based on the above new radar technical requirements, the traditional radar signal source cannot completely simulate the radar battle scene in the laboratory environment, and the radar battle capacity is evaluated.
Disclosure of Invention
The purpose of the invention is as follows: the invention aims to provide a radar active signal source aiming at the defects of the prior art, and integrates coherent and non-coherent radar signal simulation functions of multi-band and complex moving target signals.
The technical scheme is as follows: the invention relates to a radar active signal source, which comprises a frequency synthesis unit, a down-conversion unit, an intermediate frequency signal processing unit and an up-conversion unit; the method is characterized in that: the frequency synthesizer unit is used for generating a down-conversion local oscillator signal, an up-conversion local oscillator signal and a reference clock signal; the down-conversion unit is used for receiving the radio frequency signal and a down-conversion local oscillator signal output by the frequency synthesis unit, performing down-conversion and power conversion on the radio frequency signal, and outputting an intermediate frequency signal to the intermediate frequency signal processing unit; the intermediate frequency signal processing unit is used for receiving the intermediate frequency signal output by the down-conversion unit and the reference clock signal output by the frequency synthesis unit, digitally modulating the signal and outputting the modulated signal to the up-conversion unit; the up-conversion unit is used for receiving the signal output by the intermediate frequency signal processing unit and the up-conversion local oscillator signal output by the frequency synthesis unit, mixing and up-converting the signal to an X/Ku wave band and a Ka wave band, and outputting the signal according to the required amplitude.
Further perfecting the technical scheme, the local oscillator output of the frequency synthesis unit is divided into a first local oscillator, a second local oscillator and a third local oscillator, the output frequency of the first local oscillator is 11-18GHz, the output frequency of the second local oscillator is 2.4GHz/3.6GHz, and the output frequency of the third local oscillator is 26 GHz; the first local oscillator, the second local oscillator and the third local oscillator are output in two paths, wherein one path of output is a down-conversion local oscillator signal, and the other path of output is an up-conversion local oscillator signal.
Further, the down-conversion unit comprises a first down-conversion channel and a second down-conversion channel; the first down-conversion channel is used for receiving 8GHz-18GHz input signals, the input signals are divided into a first branch and a second branch through a switch selection branch, the first branch is an amplification branch, the second branch is an attenuation branch, the rear stage of the switch selection branch is a numerical control attenuator, the output end of the numerical control attenuator is amplified and coupled and then divided into two paths for output, one path is used for analog detection, the other path is divided into 8 frequency bands through a switch filter bank to output radio frequency signals, the first local oscillator output signals and the second local oscillator output signals are subjected to secondary frequency mixing to generate intermediate frequency signals, and the intermediate frequency signals are filtered, amplified and then divided into two paths for output; the second down-conversion channel is used for receiving a 34GHz-37GHz input signal, the input signal is output to the switch selection branch after being subjected to band-pass filtering, the switch selection branch is divided into a first branch and a second branch, the first branch is an amplification branch, the second branch is an attenuation branch, the back stage of the switch selection branch is a numerical control attenuator, the output end of the numerical control attenuator is amplified and then mixed with three output signals of a local oscillator, radio-frequency signals generated after mixing are filtered and amplified to be coupled into two paths of output, the output of the coupling branch is used for analog detection, the output of the coupling main path is mixed with the first output signal of the local oscillator and the second output signal of the local oscillator to generate an intermediate-frequency signal, and the intermediate-frequency signal is filtered and amplified and then coupled into two paths of output.
Furthermore, an automatic gain control adjusting unit is arranged between the down-conversion unit and the intermediate-frequency signal processing unit, and comprises an AD chip, a digital amplitude measuring module and a processor; when the intermediate frequency signal power of down the frequency conversion unit output increases, AD chip output power too big pilot signal extremely the treater, the treater increases attenuation control code automatically and down the frequency conversion unit until the AD chip detects power reduction, the too big pilot signal of power becomes invalid by effective, when the intermediate frequency signal power of down frequency conversion unit output reduces, digital amplitude measuring module output value can reduce thereupon and when reducing to setting for the threshold value output power undersize pilot signal extremely the treater, the treater reduces attenuation control code automatically and down the frequency conversion unit until the undersize pilot signal of digital amplitude measuring module output disappears.
Furthermore, the intermediate frequency signal processing unit comprises a main control computer, an intermediate frequency signal processing board card and a cPCI back board; the main control computer is connected between the remote computer and the intermediate frequency signal processing board card; the intermediate frequency signal processing board card receives a reference clock signal output by the frequency synthesizing unit and an intermediate frequency signal output by the down-conversion unit, the intermediate frequency signal is modulated by the intermediate frequency signal processing board card and then output to the up-conversion unit, and a modulated pulse signal of the intermediate frequency signal processing board card is output to the up-conversion unit through the cPCI backboard.
Furthermore, the intermediate frequency signal processing board card comprises an FPGA, an AD converter and a DA converter, the AD converter is used for receiving the intermediate frequency signal output by the down-conversion unit and outputting the intermediate frequency signal to the FPGA, and the signal is divided into two paths after serial-parallel conversion and digital down-converter in the FPGA: one path of the digital amplitude measurement, digital detection and digital frequency measurement outputs a detection pulse instantaneous detection code, the other path of the digital amplitude measurement, digital frequency measurement and digital frequency measurement outputs a detection pulse instantaneous detection code, the other path of the digital amplitude measurement and digital frequency measurement outputs a detection pulse instantaneous detection code through an externally-hung QDR-II memory for storage delay, and then the detection pulse instantaneous detection code is extracted by a fine delay module and 2 times and then sent to a target, interference and clutter generation module, a processed zero intermediate frequency digital sequence is subjected to 2 times of interpolation processing, then is converted into a real number data stream through a digital up-converter, and finally is output to a DA converter through parallel-serial conversion, and the DA converter outputs a final intermediate frequency signal.
Further, the digital down converter is 8 groups of multipliers and filters in parallel; the QDR-II memory comprises a dual-port QDR memory, a write memory address counter and a read memory address adder, wherein a clock signal is output to the dual-port QDR memory after passing through the write memory address counter, and the clock signal is output to the dual-port QDR memory after being added with the delay control quantity through the read memory address adder.
Further, the target, interference and clutter generation module comprises a target signal simulator and a clutter and target signal synthesizer; the target signal simulator is used for receiving target model information, speed information and distance information transmitted by the main control computer, assigning value to the target information, performing Doppler modulation and delay modulation according to a Doppler value, and superposing the modulated signals to obtain a zero intermediate frequency digital sequence; the clutter and target signal synthesizer comprises a target generation module, an aiming frequency noise generation module and an amplitude control module, wherein the output end of the amplitude control module is respectively connected with the target generation module and the aiming frequency noise generation module; the digital frequency measurement comprises an IQ conversion module, a cordic module and a differentiator, wherein the IQ conversion module carries out orthogonal IQ conversion on a digital intermediate-frequency signal and outputs IQ data to the cordic module, the cordic module carries out inverse tangent conversion and then outputs a phase value to the differentiator, and the differentiator carries out differential operation on the phase value and then outputs a frequency value.
Furthermore, the up-conversion unit comprises an up-conversion channel I, an up-conversion channel II and millimeter wave up-conversion, and the up-conversion channel I and the up-conversion channel II respectively comprise an intermediate frequency component, a frequency mixing component, a switch filter component and a radio frequency attenuation and amplification component; the intermediate frequency assembly adjusts the amplitude of the output signal of the intermediate frequency signal processing unit through a numerical control attenuation and detection circuit and performs amplification and filtering processing; the frequency mixing component carries out frequency conversion on the intermediate frequency signal, a second local oscillator and a first local oscillator in sequence twice and outputs a radio frequency signal of 8GHz-18GHz to the switch filter component; the switch filter component divides the radio frequency signal of 8GHz-18GHz into 8 sub-frequency bands and filters stray signals generated in the frequency mixing process in a segmented manner; the radio frequency attenuation amplifying assembly amplifies and attenuates the signal output by the switch filter assembly by adopting a multi-stage programmable attenuator and then outputs the signal; and the millimeter wave up-conversion is used for mixing the signals output by the up-conversion channel I and the up-conversion channel II with the local oscillator three output signals to generate a radio frequency signal of 34GHz-37 GHz.
Has the advantages that: compared with the prior art, the invention has the advantages that: the invention integrates the functions of coherent and non-coherent radar signal simulation of multi-band and complex moving target signals in a CPCI (compact peripheral component interconnect) architecture form, and is mainly characterized in that:
the radio frequency output channels can realize the static characteristics (distance and power) and the dynamic characteristics (distance change and Doppler frequency shift) of the target to be simulated for testing the coherent radar; simulating the target static characteristics of the fully coherent radar: statically setting distance (or delay) and radiation power; simulating the target dynamic characteristics of the fully coherent radar: including the speed, range change, doppler shift, etc. of the target; simulating the target power characteristics under ideal conditions: the signal power is related to changes of radar transmitting power, radar receiving and transmitting antenna gain, RCS, distance and the like, and the changes of the signal power are simulated according to a radar equation; simulating a target motion track: the linear motion and the circular motion of the target are simulated, the direction can be set randomly, and the synthetic distance can be finally synthesized and sent to the delay and Doppler modulation unit; simulating the dragging of a distance door: the dragging direction is divided into far away and close, and the dragging rule is linear and parabolic; simulating speed door dragging: the dragging direction is far away and close, and the dragging rule is linear and parabolic; simulating combined dragging of a distance and speed door: the interference target generates the change of approaching or departing in distance and speed by dragging speed and the real target, and the dragging rule is linear and parabolic.
All radio frequency output channels can realize the function of testing the performance indexes of the non-coherent radar: the radar emission signal can be tracked, and the output signal power and distance can be set; the device has an internal and external synchronization function, provides interference signals required by testing, and comprises multiple targets, trailing interference and clutter interference, wherein the multiple targets, trailing interference and clutter interference can be output in the same physical channel with signals, can be time-shared and superposed, and can set the frequency, power, pulse width and distance of output target signals and interference signals, and can also track radar emission signals; the single-pulse target signal with fixed frequency can be output according to the setting of a user, and the frequency, the power, the repetition frequency period, the pulse width, the distance and the movement speed can be set; the device has the functions of target movement, near point movement, far point movement, movement direction and speed setting; the X/Ku channel and the Ka channel can work simultaneously, two frequency band signals are output simultaneously, and parameters can be set.
Drawings
FIG. 1 is an overall schematic block diagram of the present invention;
FIG. 2 is a schematic diagram of a circuit configuration of a down-conversion unit;
FIG. 3 is a functional block diagram of an automatic gain adjustment unit;
fig. 4 is a functional block diagram of an intermediate frequency signal processing unit;
fig. 5 is a schematic block diagram of an intermediate frequency signal processing board card;
fig. 6 is a functional block diagram of an intermediate frequency signal processing board card;
FIG. 7 is a functional block diagram of a digital quadrature downconverter;
FIG. 8 is a circuit schematic of a digital down converter;
FIG. 9 is a functional block diagram of a delay memory;
FIG. 10 is a functional block diagram of Doppler digital modulation;
FIG. 11 is a functional block diagram of a target, interference, clutter signal generation unit;
FIG. 12 is a schematic block diagram of the synthesis of noise and target;
FIG. 13 is a diagram of clutter and target synthesis effects;
FIG. 14 is a functional block diagram of digital frequency measurement;
FIG. 15 is a functional block diagram of distance and speed pull interference generation;
FIG. 16 is a functional block diagram of an up-conversion channel;
fig. 17 is a schematic block diagram of a frequency synthesizing unit.
Detailed Description
The technical solution of the present invention is described in detail below with reference to the accompanying drawings, but the scope of the present invention is not limited to the embodiments.
The radar active signal source shown in fig. 1 is composed of a down-conversion unit, an intermediate frequency signal processing unit, a frequency synthesis unit and an up-conversion unit, and all the units are placed in a non-standard 4U CPCI chassis. A down-conversion unit: and receiving a radio frequency signal transmitted by a radar, performing down-conversion and power conversion on the radio frequency signal, performing down-conversion on the radio frequency signal to the working frequency range of the intermediate frequency signal processing unit, and outputting the signal after frequency conversion to the intermediate frequency signal processing unit. An intermediate frequency signal processing unit: the core component for generating various target, interference and radiation source target signals is a general software radio platform, comprises 2 channels with the bandwidth of 1000MHz, and adopts the form of an SDFM (software radio based radio frequency memory) component to realize digital modulation of various targets; in addition, control of targets, interference, radiation source signal power, frequency, delay time, and the like is also required to be completed; the control computer transmits data such as relative position relation, motion characteristic vector and the like between a current target platform and tested equipment, the intermediate frequency signal processing unit calculates the data to obtain a target and interference signal echo model, and modulation of a target and an interference signal of a transmitting signal and the like is completed in the unit, and frequency conversion local oscillation and switch control in the system, amplitude control in a channel and the like are realized. An up-conversion unit: the intermediate frequency signal generated by the intermediate frequency signal processing unit is up-converted to 8GHz-18GHz and Ka wave bands, and the signal output with required amplitude is realized through the amplitude level control unit. A frequency synthesis unit: the method mainly comprises the steps of generating local oscillation signals, reference signals, clock signals and the like required by system frequency conversion, wherein the local oscillation signals, the reference signals and the like mainly comprise down-conversion local oscillation signals during receiving, local oscillation signals at all levels during up-conversion, reference clock signals and the like.
1. Down conversion unit
The down-conversion unit carries out down-conversion processing on the received radio frequency signal of the tested device to obtain an intermediate frequency signal, the intermediate frequency signal is sent to the intermediate frequency signal processing unit, and the bandwidth of a subsequent SDFM unit is 1GHz, so that the system agility requirement is met. Because the tested signal has a dynamic range of 50dB in the test, the received radio frequency signal needs to be amplified and filtered, and in order to ensure that the signal entering the intermediate frequency signal processing unit does not burn off the AD, the signal receiving unit needs to have the capability of automatic gain control, and simultaneously, the whole radio frequency receiving channel needs to work in a linear range.
The technical requirements are as follows:
a) inputting a signal: 1 path of SMA (K) carries out 8-18G radio frequency signal input; inputting 34-37G radio frequency signals by 1 path of SMA2.92mm (K); the input power range of 8-18G and 34-37G radio frequency signals is-45 dBm- +12 dBm;
b) outputting a signal: the frequency range of the output intermediate frequency signal is f0 +/-500 MHz; the output power of the intermediate frequency signal is-1 dBm to-3 dBm in the bandwidth of 1G; the flatness of the intermediate frequency output 1G in-band is better than +/-1.5 dB; a filter (1.3 GHz-2.3 GHz) before the intermediate frequency is output is subjected to out-of-band rejection of 53 dBc; intermediate frequency attenuation: 30dB, stepping by 1 dB;
c) the input two paths of radio frequency signals with 8-18GHz and Ka wave bands need video detection, the detection level is 3.3V, and the adaptive pulse width is not less than 25 ns;
d) matching impedance: 50 omega.
As shown in fig. 2, in the down-conversion unit, the radio frequency signal in the 8GHz-18GHz band is divided into 8 sub-bands by the switch filter bank, and then the frequency is converted, in order to solve the problem that the combined intermodulation falls into the passband, 2 times of frequency conversion are adopted for 8GHz-18GHz, and 3 times of frequency conversion are adopted for 34GHz-37 GHz.
The first down-conversion channel sends an externally input 8GHz-18GHz signal to the switch selection branch, the first branch of the switch selection branch is an amplification branch with 20dB gain, the second branch of the switch selection branch is an attenuation branch with 30dB attenuation, and the attenuator of the attenuation branch and a 30dB attenuator at the later stage form 60dB attenuation. The radio frequency input signal is amplified and then coupled into two paths of output, one path of coupled output branch is used for analog detection, and is not only used for a time sequence trigger signal of signal processing of an intermediate frequency signal processing unit, but also used for ensuring that the output power of the module is always kept about 0dBm when the input signal of the system is converted from-45-12 dBm, and the output power of the module is used as a trigger signal for subsequent judgment and control of 60dB numerical control attenuation, namely, the pre-calibration is carried out at the radio frequency input end, so that the fluctuation of the obtained radio frequency preceding stage signal is reduced, and the power of the mixer is basically consistent. The output of the main coupler path is sent to a subsequent switch filter bank, the 8GHz-18GHz signals are divided into 8 frequency bands by the switch filter bank, the sideband of each frequency band is widened by 500MHz, and the coverage of working frequency points is realized. The 8GHz-18GHz radio frequency input signal and the 11GHz-18GHz local oscillator signal are mixed to 3GHz, and then mixed with two local oscillators of 3.6GHz or 2.4GHz to f0 +/-500 MHz for output. And f0 +/-500 MHz intermediate frequency signals are filtered, amplified and coupled into two paths of output.
And the second down-conversion channel outputs an externally input 34GHz-37GHz radio frequency signal to the switch selection branch after the bandpass filtering processing, the first branch of the switch selection branch is an amplification branch with 20dB gain, the second branch of the switch selection branch is an attenuation branch with 30dB attenuation, and the attenuator of the attenuation branch and the 30dB attenuator of the rear stage form attenuation more than 60 dB. The radio frequency signal output by the attenuator is amplified and then mixed with a 26GHz point frequency local oscillator to be within the range of 8GHz-11GHz for filtering and amplification, the amplified radio frequency signal is coupled into two paths of output, a coupling output branch is used for analog detection, a main coupler path outputs the frequency mixed with a 11GHz-14GHz local oscillator signal to be 3GHz, and then the frequency mixed with a secondary local oscillator 3.6GHz or 2.4GHz to be f0 +/-500 MHz for output. And f0 +/-500 MHz intermediate frequency signals are filtered, amplified and coupled into two paths of output.
In the working process, the dynamic range of the input signal power is-40-10 dBm, the input signal is output to the baseband processing module through the down-conversion module, the output power can dynamically change along with the input signal power, and the down-conversion attenuation needs to be dynamically adjusted because the final output power is required to be controllable by the system, namely the system output power does not dynamically change along with the input signal, so that the down-conversion output signal power is a stable value.
The automatic gain control unit shown in fig. 3 includes an AD chip, a digital amplitude measuring module, and a processor, and the working principle is as follows:
a) when the power of an input signal is increased, the power of the signal output by the down-conversion unit is increased, the power is increased, then an over-range indicating signal of an AD chip is triggered, the processor automatically increases a down-conversion attenuation control code after the power is increased, so that the down-conversion output power is reduced, after the power is reduced, the power over-range indicating signal of the AD chip is changed from effective to ineffective, and after the processor detects that the power over-range signal of the AD chip is ineffective, the attenuation code is stopped to be increased, so that the maximum value of the output power of the down-conversion unit is slightly smaller than the over-range power of the AD chip;
b) when the power of the input signal of the system is reduced, the output power of the down-conversion unit is reduced along with the reduction of the output power of the down-conversion unit, the output value of the digital amplitude measuring module is reduced along with the reduction of the output power of the down-conversion unit, when the digital power value is reduced to a set threshold value, an over-low power indicating signal is generated, after the processor detects the signal, the attenuation control code is automatically reduced, so that the down-conversion output power is increased, after the power is increased, the over-low power indicating signal disappears, the controller stops reducing the attenuation control code, so that the minimum value of the down-conversion output power is slightly larger than the set threshold value;
c) the set threshold is adjusted to enable the power of the AD chip exceeding the measuring range to be close to the power of the AD chip exceeding the measuring range, and the down-conversion output power can be limited in a dynamic range of +/-1 dBm, so that the system requirement is met.
2. Intermediate frequency signal processing unit
The intermediate frequency signal processing unit realizes the acquisition of signals, digital down conversion and the digital modulation of target signals and interference signals, and meanwhile, the intermediate frequency signal processing unit has a detection function and can automatically realize synchronization by detecting radar signals. According to the requirements of radar active signal sources, classifying the radar active signal sources according to an implementation mode, namely: for the simulation of target signals and interference signals, the same method is adopted to carry out the modulation processing of different signal characteristic modulation sequences; for the radiation type signal, the method is realized by adopting a mode of storing a waveform and updating a pulse description word by a large-capacity memory; and for the clutter interference signal, the direct generation of the broadband DDS is adopted.
When a target signal and an interference signal are simulated, the intermediate frequency signal processing unit receives the intermediate frequency signal output by the down-conversion unit, performs digital down-conversion, delay modulation, amplitude modulation, Doppler modulation, digital up-conversion and the like on the intermediate frequency signal, and sends the modulated signal to the up-conversion unit.
The hardware technical requirements of the intermediate frequency signal processing unit are as follows: an FPGA of XC7VX690T is integrated, and 2 pieces of 72Mb QDR II + SRAM are externally expanded; realizing large-bandwidth data transmission between boards and inside the board by adopting RapidLink and GTX, and carrying out communication between FPGAs by adopting a shared bus; integrating two-channel ADC sampling: the sampling rate is 2.4GSPS, the resolution is 10bit, and the input power is not more than-4.5 dBm; the dual channels are synchronously collected, and the stray is better than-50 dBc; and (3) dual-channel DAC output: the dual-channel DAC sampling clock is 2.4GSPS, the resolution is 14bit, and dual-channel synchronous output is realized; spurs better than-50 dBc; PCI bus: 1 path of standard PCI bus communication; the maximum delay of each path of radio frequency signal is 2ms (point target), and the delay precision is better than 5 ns.
The hardware platform of the intermediate frequency signal processing unit integrates all functional modules into an intermediate frequency signal processing board card for realization, the modulation information calculation module is realized by adopting a main control computer, and the composition principle is as shown in figure 4: the intermediate frequency signal processing board card and a main control computer carry out control signal transmission through a bus, the main control computer is connected with the display for output, and the main control computer is communicated with a remote computer through a LAN; the reference clock signal output by the frequency synthesis unit and the intermediate frequency signal output by the down-conversion unit enter the signal input end of the intermediate frequency signal processing board card; the intermediate frequency signal processing board processes the intermediate frequency signal and outputs the processed intermediate frequency signal to the up-conversion unit, and the frequency modulation pulse of the intermediate frequency signal processing board is output to the up-conversion unit through the ePCI back plate. According to the existing resources and functional requirements of the if signal processing board, a schematic block diagram of the if signal processing board is shown in fig. 5.
a) Design of functional module
The function division of the intermediate frequency signal processing board card is as shown in fig. 6, the AD module receives the intermediate frequency signal input from the down-conversion unit, after analog-to-digital conversion, the signal is sent to the FPGA, the data after serial-to-parallel conversion in the FPGA is subjected to DDC (digital down conversion) to change the group of data to zero intermediate frequency, and digital amplitude measurement, digital detection and digital evaluation are performed by a phase comparison method to obtain an instantaneous frequency measurement code and detection pulse. Digital detection is performed by first obtaining an absolute value of a signal, converting an input sine wave signal into a unipolar signal, and then low-pass filtering the signal to obtain a level of a pulse signal.
And (3) delaying the signal waveform according to the detection pulse, and directly delaying by adopting a QDR-II memory externally hung on the FPGA. And obtaining the read-write control of the QDR-II memory according to the delay amount and the interference pattern, and realizing the long delay of data by the read-write control of the QDR-II memory. In order to realize various required interferences and reduce the resource use of the FPGA at the same time, 2 times of extraction is carried out on the delayed data, and the data of the parallel multi-channel data is decelerated and sent to a target, interference and clutter generation module. And performing 2-time interpolation processing on the processed zero intermediate frequency interference data, converting I/Q orthogonal data into real data stream through a digital up-converter, and converting the real data stream into DA input data stream through parallel-serial conversion. And obtaining an output carrier frequency signal, namely an intermediate frequency signal with the bandwidth of 1000MHz through a DA converter.
b) Signal acquisition module
After the AD data is acquired and enters the FPGA, in order to prevent phase jump of dynamic delay, delay should be implemented on zero intermediate frequency, and meanwhile, in order to facilitate calculation of signal modulation, digital down-conversion and orthogonal transformation need to be performed on a signal, and a structure of the digital down-conversion is shown in fig. 7: for parallel input data streams, 8 groups of parallel multiplication and filters are needed to realize signal processing and down conversion, and in order to reduce the occupation degree of resources, the digital down converter can be simplified into a four-quadrant multiplier instead of a digital NCO component. In the subsequent FIR filters, a parallel FIR filter structure is still employed. In order to meet the requirement of in-band flatness of signals, inverse SINC modulation and digital equalization modulation functions are also applied in the FIR filter bank.
In the system, because the input signal is a parallel data stream of 1:8, for the design of the digital down converter, parallel down-conversion logic needs to be adopted to realize down-conversion of the signal. Now observe the relationship that the data rate of the input signal is 2.4Gsps, the center frequency is f0, and the sampling rate is 4 times the center frequency, so that when performing down-conversion modulation, it is only necessary to multiply by sine wave data of fixed phase without using NCO components, as shown in fig. 8.
c) Delay assembly
In a digital signal processing unit, a delay component mainly realizes a signal delay function, and in the delay component, delay control of a signal is mainly realized, and the purpose of the delay control is mainly to realize step delay of a digital signal. The composition of the delay element is shown in fig. 9.
In the system, the read address counter is a free accumulation counter, and the output count value is divided into two paths, one path is used as read data of digital signal data, and the other path is added with delay control quantity to obtain data as write memory address. In this way, the address written into the memory always leads the read address by a controlled delay amount in units of the count clock cycles of the memory, each clock cycle being the coarse delay resolution of the target simulation.
d) Doppler modulation assembly
The output end of the filter is a register with 8 sampling points in total, and the signal is output in an 8-path parallel data format in the 8 registers at the output end. The amplitude and Doppler modulation of the digital signal are carried out at the output end, the Doppler modulation and digital up-conversion processing are carried out on the amplitude of the output signal, and the serial-to-parallel conversion processing of the MUX is carried out at the output signal end. The tap modulation unit composition is shown in fig. 10: because the output data is parallel 8-sample data, 8 orthogonal sets of DDS are required to be adopted for digital multiplication to realize Doppler frequency modulation, the Doppler frequency generated by the 8 orthogonal sets of DDS components is 1/8 of the Doppler frequency required to be modulated, and the signals of each two adjacent DDS components have a fixed phase difference. When the doppler frequency control is performed, the phase difference is also used as control data. In the subsequent four-quadrant multiplication digital up-converter, an up-converter with fixed center frequency is realized, and the adopted center frequency is consistent with the center frequency of the previous digital down-converter. The output of the digital up-converter is a real signal sequence.
In the above design, the existing clock frequency is 2.4GHz, the phase accumulation control word length of DDS is 32bit, according to the formula
The Doppler step which can be modulated is 0.5588Hz, the DDS is adopted in the scheme to modulate the Doppler, and the accuracy is superior to the system requirement.
e) Target, interference and clutter signal implementation design
In the system, target simulation, interference simulation and background signal simulation are all completed in the FPGA, and the target simulation, the interference simulation and the background signal simulation are all associated with a transmitting signal of the tested equipment, so that the target simulation, the interference simulation and the background signal simulation are separately processed in design. The resources of the FPGA are limited, in an actual design, the resources can be repeatedly utilized, various signal patterns can be distinguished through mode selection, and a specific implementation schematic block diagram is shown in fig. 11.
f) Simulation of a target signal
By receiving target model information (in the system, complex numbers Ai with target information, i =1, 2 …, different Doppler values fdi, i =1, 2 … and different delay values Ri, i =1, 2 … in the system) sent by a master computer, the complex numbers Ai with the target information are sent to a product to be assigned, Doppler modulation is carried out through DDS according to the different Doppler values, delay modulation is carried out through Block Ram according to the different delay values, and multiplied signals are superposed, so that a zero intermediate frequency digital sequence with target modulation characteristics is obtained.
g) Clutter and target synthesis
The synthesis of the clutter and the target signal is realized in the FPGA, a target generator generates the required target signal, and the power, the distance and the pulse width of the target signal can be randomly set according to the test requirement. The noise generator is used for generating an aiming frequency noise signal, and the power, the pulse width and the distance of the noise signal can be set according to requirements. The specific implementation manner is shown in fig. 12, and the output effect of combining clutter and targets is shown in fig. 13.
h) Digital frequency measurement
The device need measure the frequency of input signal when carrying out fd modulation and production clutter interference signal to input signal, and conventional equipment generally adopts fast Fourier to change and carries out the frequency measurement, for guaranteeing the frequency measurement precision, needs to prestore a large amount of AD data to it is great to lead to the frequency measurement time delay, is difficult to satisfy the system requirement, and this system adopts the frequency measurement algorithm based on cordic module, can show improvement frequency measurement precision and frequency measurement speed. The algorithm principle is as shown in FIG. 14:
the working principle is as follows:
1) performing orthogonal IQ conversion on the AD sampling data, wherein IQ data obtained by conversion are used as cordic input data;
2) the Cordic module performs arc tangent transformation on input data to obtain a phase value;
3) the frequency can be obtained by carrying out differential operation on the phase;
i) the range-speed synchronous drags the disturbance.
The modulation amplitude of 10 channels is selected to be A1-A10, the modulation amplitude of the other 30 channels is 0, and the frequency output by the DDS is modulated by noise, so that the interference generation is simplified to be the structure shown in FIG. 15: according to the test requirements, the DDS output value is kept unchanged, the change of the distance of the output interference signal is realized by controlling the Block Ram read-write address, and meanwhile, the Doppler value is updated according to the change rate of the distance, so that the simultaneous dragging of the distance and the speed is realized.
3. Up-conversion unit
According to the requirements of system functions and technical indexes, signals generated by the intermediate frequency signal processing unit enter an up-conversion channel and are mixed with local oscillation signals to generate target echo signals of X, Ku wave bands and Ka wave bands. The up-conversion unit has the main functions of up-converting the intermediate frequency signal output by the intermediate frequency signal processing unit, converting the signal into the frequency of the input signal, and controlling the amplitude level of the signal on the radio frequency band.
The technical requirements are as follows:
a) inputting a signal: 2-path; the joint form is as follows: sma (k); input intermediate frequency signal frequency range: f0 +/-500 MHz; input intermediate frequency signal power range: -7dBm to-13 dBm; inhibiting 50dB out of band (1.3 GHz-2.3 GHz) of the intermediate frequency filter after the intermediate frequency is input; attenuation of intermediate frequency input: 30dB, stepping by 1 dB;
b) outputting a signal: 8-18G signals: path 2 sma (k); ka-band signal: 1 lane SMA2.92mm (K); monitoring signals: way 1 sma (k);
c) instantaneous bandwidth of signal: 1000 MHz;
d) signal operating bandwidth: 500 MHz;
e) and (3) outputting a radio frequency signal: output power range: 12dBm to-110 dBm; attenuation precision: 1dB, stepping 0.5dB (attenuation before combining is 40dB, attenuation after combining is 80dB, total dynamic is 120 dB); flatness in a 1G bandwidth of radio frequency signal output is better than +/-1.5 dB, the flatness is the flatness requirement of a system, and down-conversion and up-conversion need to be considered during design; the two radio frequency transmitting channels can independently set control parameters and independently work; output spurs: better than-53 dBc; matching impedance: 50 omega;
f) the system has the requirement of having the working function of switching the internal clock and the external clock; external clock input signal: external reference signal input: 1-path frequency 10MHz, power: 5 dBm. + -. 5dBm, linker form: sma (k); 2 internal reference source phase noise: better than-150 dBc @1 kHz; 3) frequency synthesis control: TTL;
g) the clock signal output by the radio frequency component is a 100MHz clock signal: path 2 sma (k);
h) system frequency interval: 5MHz, frequency precision of 1MHz, and frequency hopping time of 300 mus.
In the system, the intermediate frequency signal output by the intermediate frequency signal processing unit needs to be mixed twice to obtain radio frequency signals of X, Ku wave bands and Ka wave bands. The system comprises 2 up-conversion channels with the bandwidth of 1000MHz, and each channel can independently control the signal amplitude and the pulse modulation function. The schematic block diagram of the up-conversion channel is shown in fig. 16:
in the system, the up-conversion unit and the down-conversion unit adopt the same local oscillation signal, and the frequency is synchronously controlled, so that the requirement of consistent performance is met. The up-conversion is an inversion process of radio frequency receiving, so the up-conversion realizes the frequency conversion from f0 to 8GHz-18GHz and 34GHz-37 GHz. The local oscillator frequency of the first frequency mixing of the up-conversion channel is 11GHz-18GHz, the local oscillator is stepped by 5MHz, and the local oscillator meets the 5MHz frequency interval index requirement required by the system. The two local oscillation frequencies of the up-conversion mixing are 2.4GHz or 3.6 GHz. The frequency band of 34GHz-37GHz is obtained by mixing 8GHz-18GHz signals with a local oscillator, and the frequency of the local oscillator is 26 GHz. According to module division, an up-conversion channel comprises the following components:
a) intermediate frequency subassembly: the intermediate frequency assembly has the main functions of filtering and amplifying the signal output by the intermediate frequency signal processing unit, and simultaneously, the signal amplitude input to the intermediate frequency assembly by the intermediate frequency signal processing unit is adjusted through the matching use of numerical control attenuation and threshold detection;
b) a frequency mixing component: the function of the mixing component is to convert the intermediate frequency signal of f0 into a radio frequency signal output. The up-conversion 1 is to output 8GHz-18GHz radio frequency signals after the f0 intermediate frequency signals are subjected to twice frequency conversion, and the radio frequency signals are output to a subsequent switch filtering component. The 8GHz-18GHz frequency conversion scheme of the up-conversion 2 is completely the same as that of the up-conversion 1, and a radio frequency signal of 34GHz-37GHz is obtained after the radio frequency signal of 8GHz-18GHz and the spot frequency local oscillator are subjected to three frequency mixing;
c) a switching filter assembly: the switching filter component divides the 8-18GHz signal into 8 sub-frequency bands, and the switching filter component is mainly used for filtering stray signals generated in the frequency mixing process in a segmented manner;
d) radio frequency attenuation amplification assembly: the radio frequency attenuation amplifying assembly has the main functions of amplifying and attenuating 8GHz-18GHz radio frequency signals, and the system requires that the radio frequency signals with up-changing output have 120dB of dynamic state, so that a multi-stage programmable attenuator is adopted to realize the high dynamic state of the output signals and the high-precision control of the power level, the dynamic range of the programmable attenuator selected by the system can reach 70dB, the theoretical dynamic range of two-stage ATT can reach 140dB, the actual test of the two-stage ATT dynamic state 120dB and the stepping amount 0.5dB can meet the corresponding technical index requirements that the output signals of a simulator have the dynamic state of not less than 120dB and the signal amplitude control precision is 0.5 dB.
4. Frequency synthesizer unit
The frequency synthesis unit has the main function of generating local oscillation signals, millimeter wave frequency conversion local oscillation signals and a clock for digital system operation, which are required by each frequency conversion link of the system. The system mainly comprises a fixed local oscillator signal, a variable local oscillator signal generating part, a reference frequency signal circuit and the like, and can realize the phase switching work of an internal reference signal and an external reference signal.
The technical requirements are as follows: all local oscillator signals of the system adopt a phase-locking scheme: each frequency comprehensive signal is an independent module and is connected with each frequency conversion component through a cable, so that the production and the maintenance are more convenient. The frequency synthesizer unit is shown in fig. 17: local oscillation is 1: 11-18 GHz; local oscillation is 2.4GHz/3.6 GHz; and the local oscillator is 3: 26 GHz.
As noted above, while the present invention has been shown and described with reference to certain preferred embodiments, it is not to be construed as limited thereto. Various changes in form and detail may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.
Claims (7)
1. A radar active signal source comprises a frequency synthesis unit, a down-conversion unit, an intermediate frequency signal processing unit and an up-conversion unit; the method is characterized in that: the frequency synthesizer unit is used for generating a down-conversion local oscillator signal, an up-conversion local oscillator signal and a reference clock signal; the down-conversion unit is used for receiving the radio frequency signal and a down-conversion local oscillator signal output by the frequency synthesis unit, performing down-conversion and power conversion on the radio frequency signal, and outputting an intermediate frequency signal to the intermediate frequency signal processing unit; the intermediate frequency signal processing unit is used for receiving the intermediate frequency signal output by the down-conversion unit and the reference clock signal output by the frequency synthesis unit, digitally modulating the signal and outputting the modulated signal to the up-conversion unit; the up-conversion unit is used for receiving the signal output by the intermediate frequency signal processing unit and the up-conversion local oscillator signal output by the frequency synthesis unit, mixing and up-converting the signal to an X/Ku wave band and a Ka wave band, and outputting the signal according to the required amplitude; the local oscillator output of the frequency synthesis unit is divided into a first local oscillator, a second local oscillator and a third local oscillator, the output frequency of the first local oscillator is 11-18GHz, the output frequency of the second local oscillator is 2.4GHz/3.6GHz, and the output frequency of the third local oscillator is 26 GHz; the first local oscillator, the second local oscillator and the third local oscillator are output in two paths, wherein one path of output is a down-conversion local oscillator signal, and the other path of output is an up-conversion local oscillator signal; the down-conversion unit comprises a down-conversion channel I and a down-conversion channel II; the first down-conversion channel is used for receiving 8GHz-18GHz input signals, the input signals are divided into a first branch and a second branch through a switch selection branch, the first branch is an amplification branch, the second branch is an attenuation branch, the rear stage of the switch selection branch is a numerical control attenuator, the output end of the numerical control attenuator is amplified and coupled and then divided into two paths for output, one path is used for analog detection, the other path is divided into 8 frequency bands through a switch filter bank to output radio frequency signals, the first local oscillator output signals and the second local oscillator output signals are subjected to secondary frequency mixing to generate intermediate frequency signals, and the intermediate frequency signals are filtered, amplified and then divided into two paths for output; the second down-conversion channel is used for receiving a 34GHz-37GHz input signal, the input signal is output to the switch selection branch after being subjected to band-pass filtering, the switch selection branch is divided into a first branch and a second branch, the first branch is an amplification branch, the second branch is an attenuation branch, the back stage of the switch selection branch is a numerical control attenuator, the output end of the numerical control attenuator is amplified and then mixed with three output signals of a local oscillator, radio-frequency signals generated after mixing are filtered and amplified to be coupled into two paths of output, the output of the coupling branch is used for analog detection, the output of the coupling main path is mixed with the first output signal of the local oscillator and the second output signal of the local oscillator to generate an intermediate-frequency signal, and the intermediate-frequency signal is filtered and amplified and then coupled into two paths of output.
2. The radar active signal source of claim 1, wherein: an automatic gain control and regulation unit is arranged between the down-conversion unit and the intermediate-frequency signal processing unit, and comprises an AD chip, a digital amplitude measuring module and a processor; when the intermediate frequency signal power of down the frequency conversion unit output increases, AD chip output power too big pilot signal extremely the treater, the treater increases attenuation control code automatically and down the frequency conversion unit until the AD chip detects power reduction, the too big pilot signal of power becomes invalid by effective, when the intermediate frequency signal power of down frequency conversion unit output reduces, digital amplitude measuring module output value can reduce thereupon and when reducing to setting for the threshold value output power undersize pilot signal extremely the treater, the treater reduces attenuation control code automatically and down the frequency conversion unit until the undersize pilot signal of digital amplitude measuring module output disappears.
3. The radar active signal source of claim 1, wherein: the intermediate frequency signal processing unit comprises a main control computer, an intermediate frequency signal processing board card and a cPCI back board; the main control computer is connected between the remote computer and the intermediate frequency signal processing board card; the intermediate frequency signal processing board card receives a reference clock signal output by the frequency synthesizing unit and an intermediate frequency signal output by the down-conversion unit, the intermediate frequency signal is modulated by the intermediate frequency signal processing board card and then output to the up-conversion unit, and a modulated pulse signal of the intermediate frequency signal processing board card is output to the up-conversion unit through the cPCI backboard.
4. The radar active signal source of claim 3, wherein: the intermediate frequency signal processing board card comprises an FPGA, an AD converter and a DA converter, the AD converter is used for receiving intermediate frequency signals output by the down-conversion unit and outputting the intermediate frequency signals to the FPGA, and the signals are divided into two paths after serial-parallel conversion and a digital down converter in the FPGA: one path of the digital amplitude measurement, digital detection and digital frequency measurement outputs a detection pulse instantaneous detection code, the other path of the digital amplitude measurement, digital frequency measurement and digital frequency measurement outputs a detection pulse instantaneous detection code, the other path of the digital amplitude measurement and digital frequency measurement outputs a detection pulse instantaneous detection code through an externally-hung QDR-II memory for storage delay, and then the detection pulse instantaneous detection code is extracted by a fine delay module and 2 times and then sent to a target, interference and clutter generation module, a processed zero intermediate frequency digital sequence is subjected to 2 times of interpolation processing, then is converted into a real number data stream through a digital up-converter, and finally is output to a DA converter through parallel-serial conversion, and the DA converter outputs a final intermediate frequency signal.
5. Radar active signal source according to claim 4, characterized in that: the digital down converter is 8 groups of parallel multipliers and filters; the QDR-II memory comprises a dual-port QDR memory, a write memory address counter and a read memory address adder, wherein a clock signal is output to the dual-port QDR memory after passing through the write memory address counter, and the clock signal is output to the dual-port QDR memory after being added with the delay control quantity through the read memory address adder.
6. Radar active signal source according to claim 5, characterised in that: the target, interference and clutter generation module comprises a target signal simulator and a clutter and target signal synthesizer; the target signal simulator is used for receiving target model information, speed information and distance information transmitted by the main control computer, assigning value to the target information, performing Doppler modulation and delay modulation according to a Doppler value, and superposing the modulated signals to obtain a zero intermediate frequency digital sequence; the clutter and target signal synthesizer comprises a target generation module, an aiming frequency noise generation module and an amplitude control module, wherein the output end of the amplitude control module is respectively connected with the target generation module and the aiming frequency noise generation module; the digital frequency measurement comprises an IQ conversion module, a cordic module and a differentiator, wherein the IQ conversion module carries out orthogonal IQ conversion on a digital intermediate-frequency signal and outputs IQ data to the cordic module, the cordic module carries out inverse tangent conversion and then outputs a phase value to the differentiator, and the differentiator carries out differential operation on the phase value and then outputs a frequency value.
7. The radar active signal source of claim 1, wherein: the up-conversion unit comprises an up-conversion channel I, an up-conversion channel II and millimeter wave up-conversion, and the up-conversion channel I and the up-conversion channel II respectively comprise an intermediate frequency component, a frequency mixing component, a switch filter component and a radio frequency attenuation and amplification component; the intermediate frequency assembly adjusts the amplitude of the output signal of the intermediate frequency signal processing unit through a numerical control attenuation and detection circuit and performs amplification and filtering processing; the frequency mixing component carries out frequency conversion on the intermediate frequency signal, a second local oscillator and a first local oscillator in sequence twice and outputs a radio frequency signal of 8GHz-18GHz to the switch filter component; the switch filter component divides the radio frequency signal of 8GHz-18GHz into 8 sub-frequency bands and filters stray signals generated in the frequency mixing process in a segmented manner; the radio frequency attenuation amplifying assembly amplifies and attenuates the signal output by the switch filter assembly by adopting a multi-stage programmable attenuator and then outputs the signal; and the millimeter wave up-conversion is used for mixing the signals output by the up-conversion channel I and the up-conversion channel II with the local oscillator three output signals to generate a radio frequency signal of 34GHz-37 GHz.
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