CN110911406A - Memory and forming method thereof, and semiconductor device - Google Patents
Memory and forming method thereof, and semiconductor device Download PDFInfo
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- CN110911406A CN110911406A CN201811075311.9A CN201811075311A CN110911406A CN 110911406 A CN110911406 A CN 110911406A CN 201811075311 A CN201811075311 A CN 201811075311A CN 110911406 A CN110911406 A CN 110911406A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 9
- 239000000758 substrate Substances 0.000 claims abstract description 62
- 238000002955 isolation Methods 0.000 claims abstract description 26
- 239000002131 composite material Substances 0.000 claims abstract description 22
- 230000006870 function Effects 0.000 claims description 17
- 230000008569 process Effects 0.000 claims description 12
- 150000004767 nitrides Chemical class 0.000 claims description 6
- 238000000151 deposition Methods 0.000 claims description 4
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 claims description 3
- 238000000059 patterning Methods 0.000 claims description 2
- 230000003071 parasitic effect Effects 0.000 abstract description 10
- 238000002360 preparation method Methods 0.000 abstract description 5
- 238000000429 assembly Methods 0.000 description 10
- 230000000712 assembly Effects 0.000 description 10
- 238000010586 diagram Methods 0.000 description 7
- 239000000463 material Substances 0.000 description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 229910052814 silicon oxide Inorganic materials 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 3
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 2
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- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
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- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- 229910003481 amorphous carbon Inorganic materials 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
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- 239000003989 dielectric material Substances 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
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- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
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- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
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Abstract
The invention provides a memory, a forming method thereof and a semiconductor device. The forming method of the memory comprises the steps of forming sacrificial layer patterns on a substrate and between adjacent bit line combined structures, wherein the sacrificial layer patterns define a plurality of contact areas on the substrate between the bit line combined structures; a node contact is formed on the contact region; removing the sacrificial layer pattern to form a second cavity; and then forming an insulating capping layer which is overlapped on the top of the adjacent bit line composite structure and covers and seals the top opening of the second cavity, so that a plurality of isolation cavities between the node contacts are defined by the insulating capping layer and the adjacent bit line composite structure. Therefore, the preparation process is simple, and the gaps in the formed isolation cavity structure are uniform, so that the parasitic capacitance is effectively controlled, and the performance of the obtained device is improved.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a memory, a forming method thereof and a semiconductor device.
Background
The memory typically includes a storage capacitor for storing charge representing stored information, and a storage transistor connected to the storage element. An active region, a drain region and a gate structure are formed in the memory transistor. The gate structure is connected to a word line for controlling current flow between the source and drain regions. The source region is used for forming a bit line composite structure contact region for connecting to a bit line composite structure, and the drain region is used for forming a storage node contact region for connecting to a storage capacitor. However, parasitic capacitance is inevitably generated between adjacent bit line combination structures, so that bit line combination structure interference is generated, and the performance of the memory is affected.
Fig. 1-7 illustrate a method of forming a memory device, comprising:
as shown in fig. 1, bit line composite structures 2 are formed on a substrate 1, and a space 3 is formed between adjacent bit line composite structures 2; as shown in fig. 2, a first dielectric layer 4 is formed on the bit line combination structure 2; as shown in fig. 3, a second dielectric layer 5 is formed in the space 3 on the substrate 1, and the second dielectric layer 5 fills the lower half of the space 3; as shown in fig. 4-5, a third dielectric layer 6 is formed to fill the space 3, and is etched to form a sidewall 7, wherein the sidewall 7 is located on two sides of the upper half portion of the space 3, is not in contact with the upper half portion, and has a second cavity; referring to fig. 6, the second dielectric layer in the lower half of the space 3 is etched from the second cavity, and removed to form a cavity 8; finally, a fourth dielectric layer 9 is formed to seal the cavity 8.
However, the above process has many steps, complicated process, increased cost and increased risk of potential defects.
Disclosure of Invention
The invention aims to provide a memory, a forming method thereof and a semiconductor device, which optimize a preparation process and better reduce parasitic capacitance.
According to a first aspect of the present invention, there is provided a method of forming a memory, comprising:
providing a front-end structure which comprises a substrate and a plurality of bit line combined structures arranged on the substrate in a protruding mode;
forming a sacrificial layer pattern on the substrate, wherein the sacrificial layer pattern at least is filled between the adjacent bit line combination structures in a patterning mode to define a plurality of contact regions on the substrate;
providing a plurality of node contacts on the substrate, wherein the node contacts are accommodated in a plurality of first cavities formed by the bit line assembly structure and the sacrificial layer patterns in a staggered manner and electrically contact with the underlying substrate;
removing the sacrificial layer pattern to form a second cavity between the node contacts; and
and forming an insulating capping layer on the front-end structure, wherein the insulating capping layer is lapped on the top of the adjacent bit line composite structure and covers and seals the top opening of the second cavity, so that a plurality of isolation cavities between the node contacts are defined by the insulating capping layer and the adjacent bit line composite structure.
Optionally, for the method for forming the memory, the bit line combination structure includes: the work function layer, be located conducting layer on the work function layer and be located on the conducting layer and cover the insulating layer of conducting layer and work function layer.
Optionally, for the method for forming a memory, the step of forming an insulating capping layer on the front end structure includes: and depositing to form the insulating capping layer, wherein the insulating capping layer partially fills the second cavity towards the substrate direction, but the filling depth is not as deep as the conductive layer.
Optionally, for the method for forming a memory, the step of forming an insulating capping layer on the front end structure further includes: and thinning the insulating capping layer until the node contact is exposed, so that the insulating capping layer is formed at the pattern part at the upper part of the isolation cavity to seal the second cavity.
Optionally, for the method for forming the memory, the insulating layer includes a nitride layer.
Optionally, for the method for forming the memory, the depth-to-width ratio of the isolation cavity is greater than 3.
Optionally, for the method for forming the memory, the sacrificial layer includes an oxide layer, and the insulating capping layer includes a nitride layer.
Optionally, as for the forming method of the memory, a plasma enhanced chemical vapor deposition process is adopted to form the insulating capping layer.
According to a second aspect of the present invention, there is provided a memory comprising:
the array substrate comprises a substrate, a plurality of bit line combined structures and a plurality of contact areas, wherein the plurality of bit line combined structures are positioned on the substrate, and the plurality of contact areas are defined between the adjacent bit line combined structures;
a plurality of node contacts disposed on the contact region on the substrate and in electrical contact with the substrate; and
and the insulating capping layer is lapped on the top of the adjacent bit line composite structure, and the insulating capping layer and the adjacent bit line composite structure define a plurality of isolation cavities between the node contacts.
Optionally, for the memory, the bit line combination structure includes: the work function layer, be located conducting layer on the work function layer and be located on the conducting layer and cover the insulating layer of conducting layer and work function layer.
Optionally, for the memory, the insulating capping layer is formed at a pattern part on the upper part of the isolation cavity, but the bottom end of the insulating capping layer is not as far as the conductive layer.
Optionally, for the memory, the aspect ratio of the isolation cavity is greater than 3.
According to a third aspect of the present invention, there is also provided a semiconductor device including the memory as described above.
The forming method of the memory comprises the steps of forming sacrificial layer patterns on a substrate and between adjacent bit line combined structures, wherein the sacrificial layer patterns define a plurality of contact areas on the substrate between the bit line combined structures; a node contact is formed on the contact region; removing the sacrificial layer pattern to form a second cavity; and then forming an insulating capping layer which is overlapped on the top of the adjacent bit line composite structure and covers and seals the top opening of the second cavity, so that a plurality of isolation cavities between the node contacts are defined by the insulating capping layer and the adjacent bit line composite structure. Therefore, the preparation process is simple, and the gaps in the formed isolation cavity structure are uniform, so that the parasitic capacitance is effectively controlled, and the performance of the obtained device is improved.
Drawings
FIGS. 1-7 are schematic diagrams of a memory structure during a formation process;
FIG. 8 is a flow chart of a method for forming a memory according to one embodiment of the present invention;
FIG. 9 is a schematic diagram of a front end structure provided in a method for forming a memory according to a first embodiment of the invention;
FIG. 10 is a schematic cross-sectional view taken along line A-A' of FIG. 9;
FIG. 11 is a schematic diagram illustrating the formation of a sacrificial layer pattern in a method for forming a memory according to a first embodiment of the invention;
FIG. 12 is a schematic cross-sectional view taken along line A-A' of FIG. 11;
FIG. 13 is a schematic cross-sectional view of B-B' of FIG. 11;
FIG. 14 is a schematic diagram illustrating the formation of a node contact in a method for forming a memory according to a first embodiment of the invention;
FIG. 15 is a schematic cross-sectional view A-A' of FIG. 14;
FIG. 16 is a schematic cross-sectional view of B-B' of FIG. 14;
fig. 17 is a schematic diagram illustrating the removal of the sacrificial layer pattern in the method for forming a memory according to the first embodiment of the invention;
FIG. 18 is a schematic cross-sectional view taken along line A-A' of FIG. 17;
FIG. 19 is a schematic cross-sectional view of B-B' of FIG. 17;
FIG. 20 is a schematic diagram illustrating a deposition of an insulating capping layer in a method for forming a memory according to a first embodiment of the invention;
FIG. 21 is a schematic cross-sectional view taken along line A-A' of FIG. 20;
FIG. 22 is a schematic cross-sectional view taken along line B-B' of FIG. 20;
FIG. 23 is a diagram illustrating a planarized insulating capping layer in a method of forming a memory device according to a first embodiment of the present invention;
FIG. 24 is a schematic cross-sectional view taken along line A-A' of FIG. 23;
FIG. 25 is a schematic cross-sectional view of B-B' of FIG. 23.
Wherein the reference numbers are as follows:
1. 10-a substrate;
101-a contact zone;
102-a first cavity;
2. 20-bit line composite structure;
201-work function layer;
202-a conductive layer;
203-an insulating layer;
3-spacing;
30-node contact;
4-a first dielectric layer;
40-sacrificial layer pattern;
5-a second dielectric layer;
50-a second cavity;
6-a third dielectric layer;
60-an insulating capping layer;
7-side wall;
8-a cavity;
9-fourth dielectric layer.
Detailed Description
The memory of the present invention and method of forming the same will now be described in greater detail with reference to the schematic drawings in which preferred embodiments of the invention are shown, it being understood that one skilled in the art may modify the invention herein described while still achieving the advantageous results of the invention. Accordingly, the following description should be construed as broadly as possible to those skilled in the art and not as limiting the invention.
In the description that follows, it will be understood that when a layer (or film), region, pattern, or structure is referred to as being "on" a substrate, layer (or film), region, pad, and/or pattern, it can be directly on another layer or substrate, and/or intervening layers may also be present. In addition, it will be understood that when a layer is referred to as being "under" another layer, it can be directly under the other layer, and/or one or more intervening layers may also be present. In addition, references to "on" and "under" layers may be made based on the drawings.
The main idea of the present invention is to provide a method for forming a memory, as shown in fig. 8, the method mainly includes:
step S11, providing a front end structure including a substrate and a plurality of bit line assembly structures protrudingly disposed on the substrate;
step S12, forming a sacrificial layer pattern on the substrate, wherein the sacrificial layer pattern at least is patterned and filled between adjacent bit line assembly structures to define a plurality of contact regions on the substrate;
step S13, providing a plurality of node contacts on the contact region of the substrate, wherein the node contacts are accommodated in a plurality of first cavities formed by the alternating bit line assembly structure and the sacrificial layer pattern and electrically contacted with the substrate at the bottom layer;
step S14 of removing the sacrificial layer pattern to form a second cavity between the node contacts; and
step S15, forming an insulating capping layer on the front end structure, where the insulating capping layer overlaps the top of the adjacent bit line assembly structure and covers and seals the top opening of the second cavity, so as to define a plurality of isolation cavities between the node contacts by using the insulating capping layer and the adjacent bit line assembly structure.
The method has simple preparation process, and the formed isolation cavity structure has uniform gaps, so that the parasitic capacitance is effectively controlled, and the performance of the obtained device is improved.
Specifically, referring to fig. 9 and 10, for step S11, a front end structure is provided, which includes a substrate 10 and a plurality of bit line assemblies 20 protrudingly disposed on the substrate 10.
For example, the substrate 10 may be a silicon substrate, such as a single crystal silicon substrate or the like. Active regions, word lines, etc. may also be formed in the substrate 10.
In one embodiment, as can be seen in fig. 10 and 11, for example, the bitline assembly structure 20 includes a work function layer 201, a conductive layer 202 on the work function layer 201, and an insulating layer 203 on the conductive layer 202 and covering the conductive layer 202 and the work function layer 201.
According to practical requirements, a bottom insulating layer (not shown) may be further disposed in a portion of the region between the work function layer 201 and the substrate 10, so as to prevent the non-bit line combination contact region in the substrate 10 from being electrically connected to the formed bit line combination 20.
For example, the conductive layer 202 may be made of tungsten, and other materials may be selected, such as copper, gold, and silver.
The insulating layer 203 may be, for example, a nitride layer, such as a silicon nitride material, or may be silicon oxide, silicon oxynitride, or the like.
As shown in fig. 10, the bit line assembly structure 20 is higher than the substrate 10, which is equivalent to forming a plurality of isolation barriers on the surface of the substrate 10. The isolation barrier can be fully utilized in the subsequent process of preparing the storage node contact, and the boundary of the storage node contact is defined in a self-alignment mode.
Referring to fig. 11 to 13, for step S12, a sacrificial layer pattern 40 is formed on the substrate 10, wherein the sacrificial layer pattern 40 at least is patterned and filled between adjacent bit line assemblies 20 to define a plurality of contact regions 101 on the substrate 10; the bit line assembly structure 20 and the sacrificial layer pattern 40 are staggered to form a plurality of first cavities 102.
For example, the material of the sacrificial layer pattern 40 may be an oxide layer, such as silicon oxide, or a carbon-rich dielectric layer, germanium, hydrocarbon polymer, or amorphous carbon. For example, a silicon oxide layer is selected here. It is understood that the material of the sacrificial layer pattern 40 may be selected from other materials, which are not listed here.
The sacrificial layer pattern 40 may have various forms, for example, the sacrificial layer pattern 40 may be formed in a block shape having a height higher than the bit line assembly 20, or may be formed in a stripe shape having a height higher than the bit line assembly 20.
Next, referring to fig. 14 to 16, for step S13, a plurality of node contacts 30 are disposed on the contact region 101 of the substrate 10, wherein the node contacts 30 are received in a plurality of first cavities 102 formed by the alternating bit line assembly 20 and the sacrificial layer pattern 40 and electrically contact with the underlying substrate 10.
For example, the top surfaces of the bit line assembly 20, the sacrificial layer 40 and the node contact 30 may be flush.
Referring to fig. 17 to 19, for step S14, the sacrificial layer pattern is removed to form the second cavities 50 between the node contacts 30.
The removal of the sacrificial layer pattern may be performed by a wet etching process.
For example, a dilute hydrofluoric acid solution (DHF) may be selected.
Since the sacrificial layer pattern is designed in the present invention, the second cavity 50 obtained after removal has a uniform dimension.
As can be seen from fig. 18 and 19, the removal of the sacrificial layer pattern does not affect the node contacts 30. The adjacent node contacts 30 between the adjacent bit line composite structures 20 are changed from sacrificial layers to second cavities 50.
The size range of the second cavity 50 can be set according to actual requirements.
Thereafter, referring to fig. 20 to fig. 25, for step S15, an insulating capping layer 60 is formed on the front end structure, and the insulating capping layer 60 overlaps the top of the adjacent bitline assemblies 20 and covers the top openings of the second cavities 50, so as to define a plurality of isolation cavities between the node contacts 30 by using the insulating capping layer 60 and the adjacent bitline assemblies 20.
Specifically, the insulating capping layer 60 is formed, for example, the insulating capping layer 60 may be formed by a plasma enhanced chemical vapor deposition process.
The insulating capping layer 60 may be selected from nitride, oxide, oxynitride, etc., for example, silicon nitride material is selected here.
After the deposition process, the insulating capping layer 60 is deposited on the front end structure, the insulating capping layer 60 covers the bit line combination structure 20 and also covers the node contact 30, and meanwhile, the insulating capping layer 60 partially fills the second cavity 50 towards the substrate 10, as shown in fig. 22, the upper portion of the second cavity 50 is filled and sealed by the insulating capping layer 60, but the filling depth is not as deep as the conductive layer 202, that is, the bottom surface of the insulating capping layer 60 covering the top end of the second cavity 50 is far away from the substrate 10 than the top surface of the conductive layer 202.
In one embodiment, the aspect ratio of the second cavity 50 (i.e., isolation cavity) after the insulating capping layer 60 covers the second cavity is greater than 3.
After the deposition of the insulating capping layer 60 is completed, referring to fig. 23 to 25, the insulating capping layer 60 is thinned until the node contact 30 is exposed, so that the insulating capping layer 60 is formed at the pattern portion of the upper portion of the isolation cavity to close the second cavity 50.
For example, a planarization process is performed to thin the insulating capping layer 60, such as a Chemical Mechanical Polishing (CMP) process, and the insulating capping layer 60 is polished until the bit line assembly 20 and the node contact 30 are exposed.
Thus, in practice, the insulating capping layer 60 is only located at the top of the second cavity 50, and the insulating capping layer 60 can better overlap with the bit line assembly due to the presence of the insulating layer 203 of the bit line assembly 20. For the case with the node contacts 30, the insulating capping layer 60 also overlaps the plurality of node contacts 30.
In the invention, the second cavity is obtained by utilizing the sacrificial layer pattern, and the second cavity is not blocked before the sacrificial layer pattern is removed, namely, the removal process of the sacrificial layer pattern is simple and the removal effect is good. For example, in the case shown in fig. 6, the removal of the sacrificial layer is affected due to the existence of the side wall 7, and the effect is poor. The second cavity obtained in the present invention is of good quality and contributes even more to the improvement of the parasitic capacitance.
Through the above process, a memory of the present invention can be obtained, including:
a substrate 10, a plurality of bit line composite structures 20 located on the substrate 10, and a plurality of contact regions 101 defined on the substrate 10 between adjacent bit line composite structures 20;
a plurality of node contacts 30 disposed on a contact region 101 on the substrate 10 and electrically contacting the substrate 10; and
an insulating capping layer 60 overlapping the top of the adjacent bitline assemblies 20, the insulating capping layer 60 and the adjacent bitline assemblies 20 defining a plurality of isolation cavities between the node contacts 30.
Thus, the parasitic capacitance between the adjacent bit line assemblies 20, i.e., the parasitic capacitance between the conductive layers 202 of the adjacent bit line assemblies 20, is calculated as C ═ ε a/d, where ε is the dielectric constant, a is the relative area of the conductors between the adjacent bit line assemblies, and d is the spacing between the adjacent bit line assemblies. It is known that the second cavity is located between adjacent bit line combination structures, and the second cavity is filled with air, wherein ∈ 1.00059, which is effectively improved in parasitic capacitance C compared to other dielectrics, such as silicon oxide, and ∈ 3.9.
The invention also provides a semiconductor device comprising the memory as described above.
The forming method of the memory comprises the steps of forming sacrificial layer patterns on a substrate and between adjacent bit line combined structures, wherein the sacrificial layer patterns define a plurality of contact areas on the substrate between the bit line combined structures; a node contact is formed on the contact region; removing the sacrificial layer pattern to form a second cavity; and then forming an insulating capping layer which is overlapped on the top of the adjacent bit line composite structure and covers and seals the top opening of the second cavity, so that a plurality of isolation cavities between the node contacts are defined by the insulating capping layer and the adjacent bit line composite structure. Therefore, the preparation process is simple, and the gaps in the formed isolation cavity structure are uniform, so that the parasitic capacitance is effectively controlled, and the performance of the obtained device is improved.
The above description is only for the purpose of describing the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention, and any variations and modifications made by those skilled in the art based on the above disclosure are within the scope of the appended claims.
Claims (13)
1. A method for forming a memory, comprising:
providing a front-end structure which comprises a substrate and a plurality of bit line combined structures arranged on the substrate in a protruding mode;
forming a sacrificial layer pattern on the substrate, wherein the sacrificial layer pattern at least is filled between the adjacent bit line combination structures in a patterning mode to define a plurality of contact regions on the substrate;
providing a plurality of node contacts on the substrate, wherein the node contacts are accommodated in a plurality of first cavities formed by the bit line assembly structure and the sacrificial layer patterns in a staggered manner and electrically contact with the underlying substrate;
removing the sacrificial layer pattern to form a second cavity between the node contacts; and
and forming an insulating capping layer on the front-end structure, wherein the insulating capping layer is lapped on the top of the adjacent bit line composite structure and covers and seals the top opening of the second cavity, so that a plurality of isolation cavities between the node contacts are defined by the insulating capping layer and the adjacent bit line composite structure.
2. The method of claim 1, wherein the bit line combination structure comprises: the work function layer, be located conducting layer on the work function layer and be located on the conducting layer and cover the insulating layer of conducting layer and work function layer.
3. The method of claim 2, wherein forming an insulating capping layer on the front end structure comprises: and depositing to form the insulating capping layer, wherein the insulating capping layer partially fills the second cavity towards the substrate direction, but the filling depth is not as deep as the conductive layer.
4. The method of claim 3, wherein forming an insulating capping layer on the front-end structure further comprises: and thinning the insulating capping layer until the node contact is exposed, so that the insulating capping layer is formed at the pattern part at the upper part of the isolation cavity to seal the second cavity.
5. The method of claim 2, wherein the insulating layer comprises a nitride layer.
6. The method of claim 1, wherein an aspect ratio of the isolation cavity is greater than 3.
7. The method of claim 1, wherein the sacrificial layer comprises an oxide layer and the insulating capping layer comprises a nitride layer.
8. The method of claim 1, wherein the insulating capping layer is formed using a plasma enhanced chemical vapor deposition process.
9. A memory, comprising:
the array substrate comprises a substrate, a plurality of bit line combined structures and a plurality of contact areas, wherein the plurality of bit line combined structures are positioned on the substrate, and the plurality of contact areas are defined between the adjacent bit line combined structures;
a plurality of node contacts disposed on the contact region on the substrate and in electrical contact with the substrate; and
and the insulating capping layer is lapped on the top of the adjacent bit line composite structure, and the insulating capping layer and the adjacent bit line composite structure define a plurality of isolation cavities between the node contacts.
10. The memory of claim 9, wherein the bit line bank structure comprises: the work function layer, be located conducting layer on the work function layer and be located on the conducting layer and cover the insulating layer of conducting layer and work function layer.
11. The memory of claim 10, wherein the insulating capping layer is formed in a pattern portion on an upper portion of the isolation cavity, but a bottom end of the insulating capping layer is not as close to the conductive layer.
12. The memory of claim 9, wherein the isolation cavity has an aspect ratio greater than 3.
13. A semiconductor device comprising the memory according to any one of claims 9 to 12.
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Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20120121795A (en) * | 2011-04-27 | 2012-11-06 | 에스케이하이닉스 주식회사 | Method for manufacturing of semiconductor device having spacer with air gap |
| KR20130022872A (en) * | 2011-08-26 | 2013-03-07 | 에스케이하이닉스 주식회사 | Semiconductor device with air gap spacer and method for manufacturing the same |
| CN102986022A (en) * | 2010-06-19 | 2013-03-20 | 桑迪士克科技股份有限公司 | Non-volatile memory comprising bit line air gaps and word line air gaps and corresponding manufacturing method |
| CN103066075A (en) * | 2011-09-01 | 2013-04-24 | 三星电子株式会社 | Semiconductor device and method of fabricating same |
| US20130146958A1 (en) * | 2011-12-09 | 2013-06-13 | You-Song Kim | Method for forming buried bit line, semiconductor device having the same, and fabricating method thereof |
| CN103489866A (en) * | 2012-06-07 | 2014-01-01 | 爱思开海力士有限公司 | Semiconductor device with spacers for capping air gaps and method for fabricating the same |
| KR20150005817A (en) * | 2013-07-05 | 2015-01-15 | 삼성전자주식회사 | Semiconductor device and method of manufacturing the same |
| CN208819880U (en) * | 2018-09-14 | 2019-05-03 | 长鑫存储技术有限公司 | Memory and semiconductor devices |
-
2018
- 2018-09-14 CN CN201811075311.9A patent/CN110911406B/en active Active
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102986022A (en) * | 2010-06-19 | 2013-03-20 | 桑迪士克科技股份有限公司 | Non-volatile memory comprising bit line air gaps and word line air gaps and corresponding manufacturing method |
| KR20120121795A (en) * | 2011-04-27 | 2012-11-06 | 에스케이하이닉스 주식회사 | Method for manufacturing of semiconductor device having spacer with air gap |
| KR20130022872A (en) * | 2011-08-26 | 2013-03-07 | 에스케이하이닉스 주식회사 | Semiconductor device with air gap spacer and method for manufacturing the same |
| CN103066075A (en) * | 2011-09-01 | 2013-04-24 | 三星电子株式会社 | Semiconductor device and method of fabricating same |
| US20130146958A1 (en) * | 2011-12-09 | 2013-06-13 | You-Song Kim | Method for forming buried bit line, semiconductor device having the same, and fabricating method thereof |
| CN103489866A (en) * | 2012-06-07 | 2014-01-01 | 爱思开海力士有限公司 | Semiconductor device with spacers for capping air gaps and method for fabricating the same |
| KR20150005817A (en) * | 2013-07-05 | 2015-01-15 | 삼성전자주식회사 | Semiconductor device and method of manufacturing the same |
| CN208819880U (en) * | 2018-09-14 | 2019-05-03 | 长鑫存储技术有限公司 | Memory and semiconductor devices |
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