TWI774410B - Semiconductor device and method of forming the same - Google Patents

Abstract

Provided is a semiconductor device including a substrate, a plurality of first gate structures, and a protective structure. The substrate includes a first region and a second region. The first gate structures are disposed on the substrate in the first region. The protective structure conformally covers a sidewall of one of the first gate structures adjacent to the second region. The protective structure includes a lower portion and an upper portion disposed on the lower portion. The lower and upper portions have different dielectric materials. A method of forming a semiconductor device is also provided.

Description

Semiconductor element and method of forming the same

The present invention relates to a semiconductor device having a flash memory and a method for forming the same.

With the improvement of semiconductor technology, the size of semiconductor elements is getting smaller and smaller, so that the integration of semiconductor elements is increased, thereby integrating elements with more functions on the same wafer. Under this circumstance, the line width in the semiconductor device is also gradually reduced, so that the electronic products meet the requirements of being light, thin, and short.

However, as the critical dimensions in semiconductor devices are getting smaller and smaller, the semiconductor process technology will also face many challenges. For example, tungsten residues around a stitch region or around a peripheral circuit region can form leakage paths between source/drain contacts, which can lead to a decrease in the yield of semiconductor devices.

The present invention provides a semiconductor element and a method for forming the same, which can solve the problem of tungsten residues around the seam area or around the peripheral circuit area, thereby improving the yield of the semiconductor element.

The invention provides a semiconductor element, comprising: a substrate, a plurality of first gate structures and a protection structure. The substrate includes a first region and a second region. The first gate structure is configured on the substrate of the first region. The protection structure conformally covers a sidewall of one of the plurality of first gate structures adjacent to the second region. The protective structure includes a lower portion and an upper portion disposed on the lower portion. The lower part and the upper part have different dielectric materials.

The present invention provides a method for forming a semiconductor device, comprising: providing a substrate including a unit cell region and a peripheral region; forming a plurality of first gate structures on the substrate in the unit cell region; forming at least one second gate structure on the substrate in the peripheral region gate structure; forming sacrificial material on a plurality of first gate structures in the unit cell region; forming a stop layer to conformally cover at least one second gate structure in the plurality of first gate structures adjacent to the peripheral region a sidewall of one of the sacrificial materials and the surface of the sacrificial material; an interlayer dielectric layer is formed on the stop layer in the peripheral region; a first etching process is performed to remove the stop layer on the top surface of the sacrificial material and further etch the sacrificial material and the interlayer a stop layer between the electrical layers, thereby forming a first opening; forming a protective layer to fill the first opening, wherein the protective layer and the stop layer have different dielectric materials; and patterning the sacrificial material to form a plurality of first gate electrodes A plurality of virtual contact windows are formed between the structures.

Based on the above, in the embodiments of the present invention, the protection structure is formed between the unit cell area and the seam area and/or between the unit cell area and the peripheral area to avoid the loss of the stop layer during the etch-back process. In this case, after the contact window replacement process, the metal tungsten will not remain around the seam area or around the peripheral circuit area. Therefore, the embodiments of the present invention can avoid the leakage paths between the source/drain contacts formed by the tungsten residues, thereby improving the yield of the semiconductor device.

The present invention is more fully described with reference to the drawings of this embodiment. However, the present invention may be embodied in various forms and should not be limited to the embodiments described herein. The thicknesses of layers and regions in the drawings are exaggerated for clarity. The same or similar reference numerals denote the same or similar elements, and will not be repeated in the following paragraphs.

1A to 1J are schematic cross-sectional views of the manufacturing process of the semiconductor device according to the first embodiment of the present invention.

Referring to FIG. 1A , the present embodiment provides a method for manufacturing a semiconductor device 1 (as shown in FIG. 1J ), the steps of which are as follows. First, an initial structure 1 a is provided, which includes a substrate 100 , a plurality of first gate structures 110 and at least one second gate structure 120 . The substrate 100 may include a first region R1 and a second region R2. In one embodiment, the first region R1 may be a unit cell region, and the second region R2 may be a peripheral region. In one embodiment, the substrate 100 may be, for example, a semiconductor substrate, a semiconductor compound substrate, or a semiconductor over insulator (SOI) substrate. In this embodiment, the substrate 100 may be a silicon substrate.

A plurality of first gate structures 110 may be disposed on the substrate 100 of the first region R1. In this embodiment, the first gate structure 110 may be a flash memory structure. Specifically, each first gate structure 110 includes a tunnel dielectric layer 112 , a floating gate 114 , an inter-gate dielectric layer 116 , a control gate 118 and a capping layer 119 sequentially from bottom to top. That is, the tunnel dielectric layer 112 is disposed on the substrate 100 of the first region R1. The floating gate 114 is disposed on the tunnel dielectric layer 112 . The inter-gate dielectric layer 116 is disposed on the floating gate 114 . The control gate 118 is disposed on the inter-gate dielectric layer 116 . The cap layer 119 is disposed on the control gate 118 .

In one embodiment, the material of the tunnel dielectric layer 112 may be, for example, silicon oxide, and the formation method thereof may be chemical vapor deposition (CVD), thermal oxidation, or the like. In one embodiment, the material of the floating gate 114 may include a conductive material, such as doped polysilicon, undoped polysilicon, or a combination thereof, and the formation method may be chemical vapor deposition. In one embodiment, the inter-gate dielectric layer 116 may be, for example, a composite layer composed of nitride/oxide/nitride/oxide/nitride (Nitride/Oxide/Nitride/Oxide/Nitride, NONON), but The present invention is not limited thereto, and the composite layer may be three, five or more layers; the formation method of the inter-gate dielectric layer 116 may be, for example, chemical vapor deposition. In one embodiment, the material of the control gate 118 may include a conductive material, such as doped polysilicon, undoped polysilicon, or a combination thereof, and the formation method may be chemical vapor deposition. In one embodiment, the material of the capping layer 119 may include a dielectric material, such as silicon nitride, silicon oxynitride or a combination thereof, and the formation method may be chemical vapor deposition.

At least one second gate structure 120 may be disposed on the substrate 100 of the second region R2. Specifically, the second gate structure 120 may include a gate dielectric layer 122 and a gate electrode 124 disposed on the gate dielectric layer 122 . In one embodiment, the material of the gate dielectric layer 122 may be, for example, silicon oxide, and the formation method thereof may be chemical vapor deposition, thermal oxidation, or the like. In one embodiment, the material of the gate electrode 124 may include a conductive material, such as doped polysilicon, undoped polysilicon or a combination thereof, and the formation method may be chemical vapor deposition. In this embodiment, the first gate structure 110 and the second gate structure 120 may have different sizes, such as different heights and/or different widths. In addition, the thickness of the gate dielectric layer 122 of the second gate structure 120 may be different from the thickness of the tunnel dielectric layer 112 of the first gate structure 110 . In addition, although FIG. 1A only shows a single second gate structure 120 , the present invention is not limited thereto. In other embodiments, the number of the second gate structures 120 can be adjusted according to requirements.

As shown in FIG. 1A , the initial structure 1 a further includes spacers 102 , 126 , a sacrificial material 130 , a stop layer 132 and an interlayer dielectric layer (ILD layer) 134 . Specifically, the spacer 102 may include a single-layer structure, a double-layer structure, or a multi-layer structure. For example, the spacers 102 may include a silicon oxide layer 104 , a silicon nitride layer 106 and a silicon oxide layer 108 . The spacer 102 may conformally cover the surface of the first gate structure 110 . On the other hand, the spacer 126 may be disposed on the sidewall of the second gate structure 120 . In one embodiment, the material of the spacer 126 may include a dielectric material, such as silicon oxide, silicon nitride, or a combination thereof. Although the spacer 126 shown in FIG. 1A is a single-layer structure, the present invention is not limited thereto. In other embodiments, the spacer 126 may also be a double-layer structure or a multi-layer structure.

Sacrificial material 130 may be disposed on spacers 102 . In detail, the sacrificial material 130 may fill the spaces between the first gate structures 110 and extend to cover the top surfaces of the first gate structures 110 . In one embodiment, the material of the sacrificial material 130 may include a conductive material, such as doped polysilicon, undoped polysilicon, or a combination thereof, and the formation method may be chemical vapor deposition.

The stop layer 132 may conformally cover the second gate structure 120 , the sidewall 110s of the first gate structure 110 adjacent to the second region R2 (or the sidewall 102s of the spacer 102 ) and the surface of the sacrificial material 130 . In one embodiment, the material of the stop layer 132 may include a dielectric material, such as a nitrogen-containing dielectric material such as silicon nitride, silicon oxynitride, etc., and the formation method may be chemical vapor deposition.

The interlayer dielectric layer 134 may be disposed on the stop layer 132 of the second region R2. In one embodiment, the material of the interlayer dielectric layer 134 includes dielectric materials such as silicon oxide and low-k dielectric materials. Here, the so-called low dielectric constant means that the dielectric constant is 4 or less. The steps of forming the interlayer dielectric layer 134 may include: forming an interlayer dielectric material on the substrate 100; and performing a planarization process (eg, a CMP process) to expose the top surface 132t of the stop layer 132 of the first region R1. It should be noted that the stop layer 132 and the interlayer dielectric layer 134 of the first region R1 may have different dielectric materials with different polishing rates. For example, the stop layer 132 may be silicon nitride, and the interlayer dielectric layer 134 may be silicon oxide. In this case, the above-mentioned planarization process can remove most of the interlayer dielectric material composed of silicon oxide and stop on the top surface 132t of the stop layer 132 . That is, the stop layer 132 can be regarded as the polishing stop layer of the above-mentioned planarization process. In this embodiment, the top surface 132t of the stop layer 132 of the first region R1 and the top surface 134t of the interlayer dielectric layer 134 may be considered to be substantially coplanar.

Referring to FIG. 1B , a first etching process 140 is performed to remove the stop layer 132 on the top surface 130 t of the sacrificial material 130 and further a portion of the stop layer 132 between the sacrificial material 130 and the interlayer dielectric layer 134 is further etched, thereby forming a first Opening 10. In one embodiment, the first etching process 140 may be a wet etching process. For example, when the stop layer 132 is silicon nitride, the first etching process 140 may use an etchant containing phosphoric acid, thereby removing the stop layer 132 . Since the etchant used in the first etching process 140 has high etching selectivity to the stop layer 132, the stop layer 132 made of silicon nitride can be largely removed, while the sacrificial material 130 made of polysilicon and the The interlayer dielectric layer 134 made of silicon oxide is not removed or is only removed in a small amount. In this case, the first opening 10 may have a width 10w and a depth 10d, wherein the depth 10d is the distance between the top surface 130t of the sacrificial material 130 and the bottom surface 10bt of the first opening 10 . In this embodiment, the width 10w of the first opening 10 may be between 30 nm and 40 nm, for example, 35 nm. The depth 10d of the first opening 10 may be between 130 nm and 150 nm, for example, 140 nm. The aspect ratio of the first opening 10 may be between 5 and 3.25, eg, 4.

Referring to FIG. 1C , a protective material 142 is formed to cover the top surface 130t of the sacrificial material 130 and the top surface 134t of the interlayer dielectric layer 134 and fill the first opening 10 . In one embodiment, the protective material 142 and the stop layer 132a have different dielectric materials. For example, the protective material 142 may be an oxide material such as silicon oxide, and the stop layer 132 may be a nitride material such as silicon nitride. However, the present invention is not limited to this, as long as the protective material 142 and the stop layer 132a are materials with a high etching selectivity ratio, it is within the scope of the present invention. In addition, it is worth noting that since the first opening 10 has a high aspect ratio, in this embodiment, an enhanced high aspect ratio (eHARP) process can be used to form the protective material 142 , and then the protective material 142 can be formed. The voids of the protective material 142 in the first opening 10 are reduced. In this case, the protective material 142 may be an eHARP oxide. However, the present invention is not limited to this. In other embodiments, chemical vapor deposition or atomic layer deposition (ALD) can also be used to form the protective material 142 . In one embodiment, the holes in the eHARP oxide are smaller than those in the CVD oxide or the ALD oxide. From another point of view, the density of eHARP oxide is greater than that of CVD oxide or ALD oxide.

1C and FIG. 1D, a planarization process (eg, a CMP process) is performed to remove the protective material 142 on the top surface 130t of the sacrificial material 130, the protective material 142 on the top surface 134t of the interlayer dielectric layer 134, and part The interlayer dielectric layer 134 is formed, and the protective layer 142 a is formed in the first opening 10 . In this case, the top surface 130t of the sacrificial material 130, the top surface 142t of the protective layer 142a, and the top surface 134t of the interlayer dielectric layer 134 may be considered to be coplanar.

Referring to FIGS. 1E and 1F , the sacrificial material 130 is patterned to form a plurality of dummy contacts 130 a between the first gate structures 110 . Specifically, as shown in FIG. 1E , a mask pattern 144 is formed on the substrate 100 . The mask pattern 144 may or may not cover the top surface 142t of the protective layer 142a. In one embodiment, the material of the mask pattern 144 includes a dielectric material, such as a nitrogen-containing dielectric material such as silicon nitride, silicon oxynitride, etc., and the formation method may be chemical vapor deposition. Next, using the mask pattern 144 as a mask, a second etching process 150 is performed to remove part of the sacrificial material 130 , thereby forming a plurality of second openings 12 . In this case, as shown in FIG. 1F , the second opening 12 exposes the spacer 102 directly above the first gate structure 110 and exposes a part of the surface of the protective layer 142 a. In one embodiment, the second etching process 150 may be a dry etching process, such as a reactive ion etching (RIE) process.

Referring to FIG. 1G , a liner 152 may be selectively formed to cover conformally. The mask pattern 144 and the surface of the second opening 12 . In one embodiment, the material of the lining layer 152 may include a dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride or a combination thereof, and the formation method may be chemical vapor deposition.

Referring to FIG. 1G and FIG. 1H , a dielectric layer 154 is formed in the second opening 12 . In one embodiment, the material of the dielectric layer 154 may include a dielectric material, such as tetraethoxysilane (TEOS). The steps of forming the dielectric layer 154 may include: forming a dielectric material on the substrate 100 ; and performing a planarization process (eg, a CMP process) to expose the top surface 144t of the mask pattern 144 .

1I, an etch-back process 160 is performed to remove part of the liner 152, part of the dielectric layer 154 and the mask pattern 144, thereby exposing the top surface 130t of the dummy contact 130a and the top surface 142t of the protective layer 142a. In one embodiment, the etch back process 160 may be a dry etching process, such as a reactive ion etching (RIE) process. In the present embodiment, the etch-back process 160 has a high etch selectivity for the mask pattern 144, and thus, the mask pattern 144 made of silicon nitride can be completely removed. In this case, the etch-back process 160 can stop on the dummy contact 130a formed of polysilicon and the protective layer 142a formed of silicon oxide. As shown in FIG. 1I , dummy contacts 130 a may be formed between the first gate structures 110 and separated from the first gate structures 110 by spacers 102 .

It is worth noting that, in this embodiment, the upper part of the stop layer is replaced by silicon nitride with silicon oxide. Therefore, the protective layer 142a formed of silicon oxide can protect the stop layer 132a formed of silicon nitride from etching back The etching process 160 forms grooves. In this embodiment, the stop layer 132 a and the protective layer 142 a can be regarded as the protective structure 162 . The protection structure 162 may conformally cover the sidewall 110s of the first gate structure 110 adjacent to the second region R2 and may be sandwiched between the interlayer dielectric layer 134 and the spacer 102 . From another perspective, the protection structure 162 may have a lower portion (ie, the stop layer 132 a ) and an upper portion (ie, the protection layer 142 a ) disposed on the lower portion 132 a . The interface S1 between the lower portion 132 a and the upper portion 142 a may be higher than the top surface 110 t of the first gate structure 110 . The top surface 142t of the upper portion 142a may be exposed to the interlayer dielectric layer 134 . The lower portion 132a and the upper portion 142a may have different dielectric materials, and the upper portion 142a and the mask pattern 144 (FIG. 1H) may be of the same material. For example, the material of the lower portion 132a includes silicon nitride, and the material of the upper portion 142a and the mask pattern 144 includes silicon nitride.

Referring to FIGS. 1I and 1J , a replacement process is performed to replace the dummy contacts 130 a with metal contacts 230 . Specifically, the dummy contact window 130 a and a portion of the spacer 102 thereunder are removed to form a plurality of contact window openings exposing the substrate 100 . Next, a conductor material is formed to fill the contact openings. In one embodiment, the aforementioned conductor material is different from the sacrificial material 130 . The above-mentioned conductor materials may include metal materials (such as W, Cu, AlCu, etc.), barrier metals (such as Ti, TiN, Ta, TaN, etc.) or combinations thereof, and the formation methods may be electroplating, physical vapor deposition, etc. Suitable formation methods such as PVD, chemical vapor deposition, etc. Then, a planarization process (eg, a CMP process) is performed to remove excess conductor material above the dielectric layer 154, the interlayer dielectric layer 134 and the protective layer 142a, thereby forming the source contact SC and the drain contact DC. In this case, the top surface 142t of the protective layer 142a may be substantially coplanar with the top surface SCt of the source contact SC and the top surface DCt of the drain contact DC. That is, after the CMP process, no metal residue will be formed above the stop layer 132a between the unit cell region R1 and the peripheral region R2. Therefore, the present embodiment can avoid forming a leakage path between the source contact window SC and/or the drain contact window DC, thereby improving the yield of the semiconductor device 1 .

In one embodiment, the source contact window SC may be disposed on the first side of the first gate structure 110 , and the drain contact window DC may be disposed on the second side of the first gate structure 110 relative to the first side. . That is, the source contact windows SC and the drain contact windows DC may be alternately arranged along the direction D1 parallel to the substrate 100 . In addition, as shown in FIG. 1J , the source contact window SC and the drain contact window DC may be separated from the first gate structure 110 by the spacer 102 .

FIG. 2 is a schematic top view of a semiconductor device according to a second embodiment of the present invention.

Referring to FIG. 2, a second embodiment of the present invention provides a semiconductor device 2 including a substrate 100, a plurality of first gate structures 110, a plurality of source contacts SC, a plurality of drain contacts DC, and a plurality of control gates For the contact window CC, the substrate 100 includes a first region R1 and a second region R2'. In one embodiment, the first region R1 may be a unit cell region, and the second region R2' may be a stitch region. The seam region R2 may be disposed between two adjacent unit cell regions R1.

The first gate structure 110 can be disposed on the substrate 100 of the unit cell region R1 , and the configuration and material of the first gate structure 110 have been described in detail in the above embodiments, and will not be repeated here. In one embodiment, the source contact window SC may be disposed on the first side of the first gate structure 110 , and the drain contact window DC may be disposed on the second side of the first gate structure 110 relative to the first side. . That is, the source contact windows SC and the drain contact windows DC may be alternately arranged along the X direction. It is worth noting that the source contact SC and the drain contact DC have different shapes in the top view. Specifically, as shown in FIG. 2 , the source contact window SC may be a stripe pattern extending along the Y direction. The drain contact window DC may be a plurality of dot patterns alternately arranged along the Y direction, and the plurality of dot patterns are separated from each other. The source contact window SC and the drain contact window DC may extend along the Z direction and be in contact with the substrate 100 , as shown in FIG. 1J .

In addition, the control gate contact window CC may be disposed on the substrate 100 in the seam region R2' to electrically connect the control gate 118 of the first gate structure 110 (as shown in FIG. 1J ). Specifically, the control gate contact window CC may be disposed in the extending direction of the first gate structure 110 between the source contact window SC and the drain contact window DC. The control gate contacts CC may be staggered along the X direction.

3A to 3E are schematic cross-sectional views of the manufacturing process of the semiconductor device 2 along the line A-A' in FIG. 2 .

Referring to FIG. 3A , while the first etching process 140 is performed to form the first opening 12 (as shown in FIG. 1B ), the stop layer 132 between the unit cell region R1 and the seam region R2 ′ can also be etched, and further The third opening 14 is formed. Next, a protective material 142 is formed to cover the top surface 130t of the sacrificial material 130 and the top surface 134t of the interlayer dielectric layer 134 and fill in the third opening 14 . It should be noted that the angle θ1 between the side wall 14s and the bottom surface 14bt of the third opening 14 is an acute angle, and the third opening 14 has a high aspect ratio. Therefore, in the present embodiment, the protection material 142 can be formed by the enhanced high aspect ratio trench filling process (eHARP), thereby reducing the voids of the protection material 142 in the third opening 14 and increasing the density of the protection material 142 . In this embodiment, the included angle θ1 may be between 0 degrees and 87 degrees, for example, 65 degrees. The aspect ratio of the third opening 14 may be between 5 and 3.25, eg, 4.

3A and 3B, a planarization process (eg, a CMP process) is performed to remove the protective material 142 on the top surface 130t of the sacrificial material 130, the protective material 142 on the top surface 134t of the interlayer dielectric layer 134, and part The interlayer dielectric layer 134 is formed, and the protective layer 242 is formed in the third opening 14 . In this case, the top surface 130t of the sacrificial material 130, the top surface 242t of the protective layer 242, and the top surface 134t of the interlayer dielectric layer 134 may be considered to be coplanar.

Referring to FIG. 3C , the sacrificial material 130 is patterned to form a plurality of dummy contacts 130 a between the first gate structures 110 . Specifically, as shown in FIG. 3C , a mask pattern 144 is formed on the substrate 100 . The mask pattern 144 may cover the top surface 242t of the protective layer 242 . Next, using the mask pattern 144 as a mask, a second etching process 150 is performed to remove part of the sacrificial material 130 , thereby forming a plurality of second openings 12 (as shown in FIG. 1F ). In this embodiment, the structures along the line A-A' are covered by the mask pattern 144, so the second opening 12 is not shown in FIG. 3C.

Referring to FIG. 3D , after forming the liner layer 152 and the dielectric layer 154 (as shown in FIG. 1H ), an etch-back process 160 is performed to remove the mask pattern 144 , thereby exposing the top surface 130t and the protection of the dummy contact window 130a Top surface 242t of layer 242. In the present embodiment, the etch-back process 160 has a high etch selectivity for the mask pattern 144, and thus, the mask pattern 144 made of silicon nitride can be completely removed. In this case, the etch-back process 160 may stop on the dummy contact 130a formed of polysilicon and the protective layer 242 formed of silicon oxide.

Referring to FIG. 3E , a replacement process is performed to replace the dummy contacts 130 a with the metal contacts 230 . Specifically, the dummy contact windows 130 a and the spacers thereunder are removed to form a plurality of contact window openings exposing the substrate 100 . Next, a conductor material is formed to fill the contact openings. Then, a planarization process (such as a CMP process) is performed to remove the excess conductor material above the interlayer dielectric layer 134 and the protective layer 242, thereby forming the metal contact window 230 (ie, the source contact window SC and the drain contact window DC) ). In this case, the top surface 242t of the protective layer 242 may be substantially coplanar with the top surface 230t of the metal contact window 230 and the top surface 134t of the interlayer dielectric layer 134 . In this embodiment, the stop layer 132 a and the protective layer 242 can be regarded as the protective structure 262 . The protective structure 262 may have a lower portion (ie, the stop layer 132 a ) and an upper portion (ie, the protective layer 242 ) disposed on the lower portion 132 a . In one embodiment, the included angle θ2 between the sidewall of the protection structure 262 and the top surface of the substrate 100 is an acute angle. In this embodiment, the included angle θ2 may be between 0 degrees and 87 degrees, for example, 65 degrees.

It is worth noting that, in this embodiment, the upper part of the stop layer 132a can be replaced by silicon nitride with silicon oxide. Therefore, the protective layer 242 formed of silicon oxide can protect the stop layer 132a formed of silicon nitride from The grooves are formed by the erosion of the etch-back process 160 . In this case, after the contact window replacement process is performed, no metal residue is formed over the stop layer 132a between the unit cell region R1 and the seam region R2'. Therefore, the present embodiment can avoid forming a leakage path between the source contact windows SC and/or the drain contact windows DC, thereby improving the yield of the semiconductor device 2 .

To sum up, in the embodiments of the present invention, the protection structure is formed between the unit cell area and the seam area and/or between the unit cell area and the peripheral area to avoid the formation of the stop layer during the etch-back process. loss. In this case, after the contact window replacement process, the metal tungsten will not remain around the seam area or around the peripheral circuit area. Therefore, the embodiments of the present invention can avoid the leakage paths between the source/drain contacts formed by the tungsten residues, thereby improving the yield of the semiconductor device.

1, 2: Semiconductor components 1a: Initial structure 10: The first opening 10bt: Underside 10d: Depth 10w: width 12: Second opening 14: The third opening 14bt: Underside 14s: Sidewall 100: base 102, 126: Spacers 102s, 110s: Sidewall 104, 108: Silicon oxide layer 106: Silicon nitride layer 110: The first gate structure 112: Tunneling Dielectric Layer 114: floating gate 116: Intergate dielectric layer 118: Control gate 119: Cap layer 120: Second gate structure 122: gate dielectric layer 124: Gate electrode 130: Sacrificial Materials 130a: Virtual Contact Window 130t, 132t, 134t, 142t, 230t, 242t, DCt, SCt: Top surface 132, 132a: stop layer (lower part) 134: Interlayer dielectric layer 140: The first etching process 142: Protective Materials 142a, 242: protective layer (upper) 144: Virtual Contact Window 150: The second etching process 152: Liner 154: Dielectric layer 160: Etch back process 162, 262: Protection structure 230: Metal Contact Window D1, X, Y, Z: direction DC: drain contact window S1: Interface SC: source contact window R1: The first area (unit cell area) R2: The second area (surrounding area) R2': The second area (joint area) θ1, θ2: included angle

1A to 1J are schematic cross-sectional views of the manufacturing process of the semiconductor device according to the first embodiment of the present invention. FIG. 2 is a schematic top view of a semiconductor device according to a second embodiment of the present invention. 3A to 3E are schematic cross-sectional views of the manufacturing process of the semiconductor device along the line A-A' of FIG. 2 .

2: Semiconductor components

100: base

132a: stop layer (lower part)

134: Interlayer dielectric layer

134t, 230t, 242t: top surface

230: Metal Contact Window

242: Protective layer (upper)

262: Protection Structure

θ2: included angle

Claims (12)

A semiconductor element, comprising: a substrate including a first region and a second region; a plurality of first gate structures disposed on the substrate in the first region; a protection structure conformally covering the second region a sidewall of one of the plurality of first gate structures adjacent to the region, wherein the protection structure includes: a lower portion; and an upper portion disposed on the lower portion, wherein the lower portion and the upper portion have different distances an electrical material; a source contact window disposed on a first side of the plurality of first gate structures; and a drain contact window disposed on the first side of the plurality of first gate structures relative to the first side The second side, wherein the source contact and the drain contact have different shapes in top view. The semiconductor element of claim 1, wherein the material of the upper portion includes silicon oxide, and the material of the lower portion includes silicon nitride. The semiconductor device according to claim 1, wherein the first region is a unit cell region, the second region is a peripheral region, and the semiconductor device further comprises at least one second gate structure disposed in the peripheral region on the substrate. The semiconductor device according to claim 3, further comprising: spacers that conformally cover the surfaces of the plurality of first gate structures, wherein the source contacts and the drain contacts pass through the gaps a wall spaced apart from the plurality of first gate structures; and an interlayer dielectric layer disposed on the at least one second gate structure in the peripheral region, wherein the protection structure is sandwiched between the interlayer dielectric layer and the spacer, and the protection structure The top surface of the upper portion is exposed to the interlayer dielectric layer. The semiconductor device according to claim 1, wherein the first region is a unit cell region, the second region is a seam region, and the semiconductor device further comprises a plurality of control gate contacts disposed on the seam On the substrate of the region, the control gate is electrically connected. The semiconductor device according to claim 5, wherein the included angle between the sidewall of the protection structure and the top surface of the substrate is an acute angle. The semiconductor element of claim 1, wherein an interface between the lower portion and the upper portion is higher than top surfaces of the plurality of first gate structures. A method for forming a semiconductor element, comprising: providing a substrate including a unit cell region and a peripheral region; forming a plurality of first gate structures on the substrate in the unit cell region; and forming a plurality of first gate structures on the substrate in the peripheral region forming at least one second gate structure; forming a sacrificial material on the plurality of first gate structures in the unit cell region; forming a stop layer to conformally cover the at least one second gate structure, and the a sidewall of one of the plurality of first gate structures adjacent to the peripheral region and the surface of the sacrificial material; forming an interlayer dielectric layer on the stop layer in the peripheral region; performing a first etching process , remove the stop layer on the top surface of the sacrificial material and further etch the stop between the sacrificial material and the interlayer dielectric layer layer to form a first opening; forming a protective layer to fill the first opening, wherein the protective layer and the stop layer have different dielectric materials; and patterning the sacrificial material so that the plurality of A plurality of dummy contact windows are formed between the first gate structures. The method for forming a semiconductor device according to claim 8, wherein the patterning of the sacrificial material comprises: forming a mask pattern on the substrate; using the mask pattern as a mask, performing a second etching process, Part of the sacrificial material is removed to form a plurality of second openings; a dielectric layer is formed in the plurality of second openings; and an etch-back process is performed to remove part of the dielectric layer and the mask pattern , thereby exposing the top surfaces of the plurality of dummy contact windows and the top surface of the protective layer. The method for forming a semiconductor element according to claim 8, wherein before forming the sacrificial material, the forming method further comprises: forming spacers to conformally cover the surfaces of the plurality of first gate structures, And the plurality of dummy contact windows are separated from the plurality of first gate structures by the spacers. The method for forming a semiconductor device according to claim 10, further comprising: removing the plurality of dummy contact windows and the spacers below them to form a plurality of contact window openings exposing the substrate; and Conductive material is filled into the plurality of contact openings to form source contacts and drain contacts, wherein the source contacts and the drain contacts have different shapes in top view. The method for forming a semiconductor element according to claim 8, wherein the aspect ratio of the first opening is between 5 and 3.25.

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